diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se')
47 files changed, 19722 insertions, 19525 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index ef2534218..2d36751f4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062409 # Number of seconds simulated -sim_ticks 62408957500 # Number of ticks simulated -final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062421 # Number of seconds simulated +sim_ticks 62420912500 # Number of ticks simulated +final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176281 # Simulator instruction rate (inst/s) -host_op_rate 177159 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121425676 # Simulator tick rate (ticks/s) -host_mem_usage 399932 # Number of bytes of host memory used -host_seconds 513.97 # Real time elapsed on the host +host_inst_rate 255603 # Simulator instruction rate (inst/s) +host_op_rate 256876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176097831 # Simulator tick rate (ticks/s) +host_mem_usage 405340 # Number of bytes of host memory used +host_seconds 354.47 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62408863500 # Total gap between requests +system.physmem.totGap 62420817500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation -system.physmem.totQLat 75120250 # Total ticks spent queuing -system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation +system.physmem.totQLat 72080000 # Total ticks spent queuing +system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s @@ -217,48 +217,48 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14020 # Number of row buffer hits during reads +system.physmem.readRowHits 14024 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4007246.92 # Average gap between requests -system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4008014.48 # Average gap between requests +system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.544396 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states +system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.524455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.428274 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states +system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.484088 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 20808236 # Number of BP lookups -system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 20808241 # Number of BP lookups +system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 124817915 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 124841825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.377638 # CPI: cycles per instruction -system.cpu.ipc 0.725880 # IPC: instructions per cycle +system.cpu.cpi 1.377902 # CPI: cycles per instruction +system.cpu.ipc 0.725741 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -432,60 +432,60 @@ system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits -system.cpu.dcache.overall_hits::total 26267146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits +system.cpu.dcache.overall_hits::total 26267147 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses -system.cpu.dcache.overall_misses::total 980615 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses +system.cpu.dcache.overall_misses::total 980613 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -494,28 +494,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,14 +524,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses @@ -542,16 +542,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194 system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -562,71 +562,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55672985 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits -system.cpu.icache.overall_hits::total 27835291 # number of overall hits +system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27835051 # number of overall hits +system.cpu.icache.overall_hits::total 27835051 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses system.cpu.icache.overall_misses::total 801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60780500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27835852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,48 +641,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801 system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -711,18 +709,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses system.cpu.l2cache.overall_misses::total 15581 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1081439500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58471000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1161563000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58471000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) @@ -751,18 +749,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,18 +789,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 954685000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses @@ -815,25 +813,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -867,7 +865,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 1201999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution @@ -888,9 +892,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0313fa682..a9bdce95d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058199 # Number of seconds simulated -sim_ticks 58199030500 # Number of ticks simulated -final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058328 # Number of seconds simulated +sim_ticks 58328364500 # Number of ticks simulated +final_tick 58328364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122100 # Simulator instruction rate (inst/s) -host_op_rate 122709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78442850 # Simulator tick rate (ticks/s) -host_mem_usage 487108 # Number of bytes of host memory used -host_seconds 741.93 # Real time elapsed on the host +host_inst_rate 135523 # Simulator instruction rate (inst/s) +host_op_rate 136198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87259482 # Simulator tick rate (ticks/s) +host_mem_usage 492508 # Number of bytes of host memory used +host_seconds 668.45 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory -system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory -system.physmem.bytes_written::total 11200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory -system.physmem.num_writes::total 175 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16517 # Number of read requests accepted -system.physmem.writeReqs 175 # Number of write requests accepted -system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue -system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 218752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 921408 # Number of bytes read from this memory +system.physmem.bytes_read::total 1184896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5696 # Number of bytes written to this memory +system.physmem.bytes_written::total 5696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18514 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 89 # Number of write requests responded to by this memory +system.physmem.num_writes::total 89 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 766968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3750354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15796911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20314233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 766968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 766968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97654 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97654 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 766968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3750354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15796911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20411887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18515 # Number of read requests accepted +system.physmem.writeReqs 89 # Number of write requests accepted +system.physmem.readBursts 18515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 89 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1179904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue +system.physmem.bytesWritten 4480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1184960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1166 # Per bank write bursts -system.physmem.perBankRdBursts::1 920 # Per bank write bursts -system.physmem.perBankRdBursts::2 953 # Per bank write bursts +system.physmem.perBankRdBursts::0 3247 # Per bank write bursts +system.physmem.perBankRdBursts::1 921 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts system.physmem.perBankRdBursts::4 1061 # Per bank write bursts -system.physmem.perBankRdBursts::5 1122 # Per bank write bursts -system.physmem.perBankRdBursts::6 1094 # Per bank write bursts -system.physmem.perBankRdBursts::7 1089 # Per bank write bursts -system.physmem.perBankRdBursts::8 1025 # Per bank write bursts +system.physmem.perBankRdBursts::5 1117 # Per bank write bursts +system.physmem.perBankRdBursts::6 1095 # Per bank write bursts +system.physmem.perBankRdBursts::7 1097 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 933 # Per bank write bursts -system.physmem.perBankRdBursts::11 900 # Per bank write bursts -system.physmem.perBankRdBursts::12 903 # Per bank write bursts -system.physmem.perBankRdBursts::13 900 # Per bank write bursts -system.physmem.perBankRdBursts::14 1411 # Per bank write bursts -system.physmem.perBankRdBursts::15 910 # Per bank write bursts -system.physmem.perBankWrBursts::0 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 932 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 902 # Per bank write bursts +system.physmem.perBankRdBursts::13 896 # Per bank write bursts +system.physmem.perBankRdBursts::14 1399 # Per bank write bursts +system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 6 # Per bank write bursts +system.physmem.perBankWrBursts::2 2 # Per bank write bursts system.physmem.perBankWrBursts::3 1 # Per bank write bursts -system.physmem.perBankWrBursts::4 3 # Per bank write bursts -system.physmem.perBankWrBursts::5 16 # Per bank write bursts -system.physmem.perBankWrBursts::6 40 # Per bank write bursts -system.physmem.perBankWrBursts::7 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 2 # Per bank write bursts +system.physmem.perBankWrBursts::5 9 # Per bank write bursts +system.physmem.perBankWrBursts::6 10 # Per bank write bursts +system.physmem.perBankWrBursts::7 8 # Per bank write bursts system.physmem.perBankWrBursts::8 2 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 2 # Per bank write bursts -system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 3 # Per bank write bursts system.physmem.perBankWrBursts::12 2 # Per bank write bursts -system.physmem.perBankWrBursts::13 17 # Per bank write bursts -system.physmem.perBankWrBursts::14 37 # Per bank write bursts -system.physmem.perBankWrBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::13 9 # Per bank write bursts +system.physmem.perBankWrBursts::14 13 # Per bank write bursts +system.physmem.perBankWrBursts::15 6 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58199022000 # Total gap between requests +system.physmem.totGap 58328356000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16517 # Read request sizes (log2) +system.physmem.readPktSize::6 18515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 175 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see +system.physmem.writePktSize::6 89 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 13470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 283 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -149,24 +149,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -198,98 +198,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads -system.physmem.totQLat 175730624 # Total ticks spent queuing -system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 3107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.704216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.847183 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.867268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1088 35.02% 35.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 865 27.84% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 3.03% 65.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 72 2.32% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 2.09% 70.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 68 2.19% 72.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 56 1.80% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 51 1.64% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 24.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 3107 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4608 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 1496.681558 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7484.705695 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 1 25.00% 25.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 25.00% 50.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.500000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.477704 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 25.00% 25.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3 75.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads +system.physmem.totQLat 204802662 # Total ticks spent queuing +system.physmem.totMemAccLat 550477662 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11108.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29858.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 20.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage -system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.16 # Data bus utilization in percentage +system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14651 # Number of row buffer hits during reads -system.physmem.writeRowHits 51 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes -system.physmem.avgGap 3486641.62 # Average gap between requests -system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ) -system.physmem_0.averagePower 672.381118 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states -system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.38 # Average write queue length when enqueuing +system.physmem.readRowHits 15382 # Number of row buffer hits during reads +system.physmem.writeRowHits 10 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.49 # Row buffer hit rate for writes +system.physmem.avgGap 3135258.87 # Average gap between requests +system.physmem.pageHitRate 83.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 17803800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 9714375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 81876600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 162000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6575109030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29228595750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39722884515 # Total energy per rank (pJ) +system.physmem_0.averagePower 681.036990 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48583441495 # Time in different power states +system.physmem_0.memoryStateTime::REF 1947660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7795971005 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.780705 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states -system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem_1.actEnergy 5609520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3060750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 61760400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 187920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2425538385 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32868570000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39174349935 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.632528 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54671634140 # Time in different power states +system.physmem_1.memoryStateTime::REF 1947660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1708703360 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28233538 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28233990 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266525 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835401 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829630 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11747896 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 99.309074 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74550 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 27225 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 1747 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -319,7 +323,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -349,7 +353,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,7 +383,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,84 +414,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 116398062 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 116656730 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746133 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134907690 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28233990 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11847924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115018036 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674227 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275439 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 555 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116602964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.162155 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318550 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59067374 50.66% 50.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13933709 11.95% 62.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9228635 7.91% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34373246 29.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483152587 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116602964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242026 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.156450 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8835100 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64368120 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33012562 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9561783 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825399 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097891 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11814 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114395515 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1985251 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825399 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15271601 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50089085 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 110009 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35409630 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14897240 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110872720 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412183 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133547 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1231881 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1645196 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 486344 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129945840 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483153679 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119447461 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 433 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22632921 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21513680 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805319 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347286 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 522469 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 256366 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109667529 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41667039 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101366370 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074686 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18634782 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41671490 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116602964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.869329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988911 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54969091 47.14% 47.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31363076 26.90% 74.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22007447 18.87% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7065313 6.06% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197724 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -495,9 +499,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116602964 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9783594 48.67% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available @@ -526,13 +530,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615674 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702930 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970691 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -556,86 +560,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337594 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047205 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued -system.cpu.iq.rate 0.870864 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101366370 # Type of FU issued +system.cpu.iq.rate 0.868929 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20102261 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340512191 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128311283 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99607990 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121468392 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288047 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329408 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602442 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130712 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825399 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8206553 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 706266 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109688634 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26805319 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347286 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 180569 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 362078 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847487 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100109489 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23802993 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1256881 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12822 # number of nop insts executed -system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621209 # Number of branches executed -system.cpu.iew.exec_stores 4915850 # Number of stores executed -system.cpu.iew.exec_rate 0.860065 # Inst execution rate -system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59691637 # num instructions producing a value -system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value -system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28718621 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621294 # Number of branches executed +system.cpu.iew.exec_stores 4915628 # Number of stores executed +system.cpu.iew.exec_rate 0.858154 # Inst execution rate +system.cpu.iew.wb_sent 99693258 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99608103 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59691284 # num instructions producing a value +system.cpu.iew.wb_consumers 95529167 # num instructions consuming a value +system.cpu.iew.wb_rate 0.853856 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624849 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17363279 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823687 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113915056 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.799312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.736114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77490817 68.03% 68.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18611366 16.34% 84.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7154135 6.28% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469454 3.05% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644903 1.44% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541342 0.48% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703110 0.62% 96.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178773 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4121156 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113915056 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -681,80 +685,80 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217947492 # The number of ROB reads -system.cpu.rob.rob_writes 219521309 # The number of ROB writes -system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4121156 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218205084 # The number of ROB reads +system.cpu.rob.rob_writes 219522331 # The number of ROB writes +system.cpu.timesIdled 576 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53766 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108097873 # number of integer regfile reads -system.cpu.int_regfile_writes 58692304 # number of integer regfile writes -system.cpu.fp_regfile_reads 59 # number of floating regfile reads -system.cpu.fp_regfile_writes 96 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes -system.cpu.misc_regfile_reads 28410105 # number of misc regfile reads +system.cpu.cpi 1.287747 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.287747 # CPI: Total CPI of All Threads +system.cpu.ipc 0.776550 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.776550 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108097252 # number of integer regfile reads +system.cpu.int_regfile_writes 58691902 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 93 # number of floating regfile writes +system.cpu.cc_regfile_reads 369002875 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686679 # number of cc regfile writes +system.cpu.misc_regfile_reads 28409649 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470634 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 5470636 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.779483 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249262 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471148 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335545 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 36545500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.779483 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999569 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999569 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61906894 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906894 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13887138 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887138 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353836 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353836 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits -system.cpu.dcache.overall_hits::total 18241600 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18240974 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18240974 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18241496 # number of overall hits +system.cpu.dcache.overall_hits::total 18241496 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587451 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587451 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381145 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381145 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses -system.cpu.dcache.overall_misses::total 9968505 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9968596 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968596 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968603 # number of overall misses +system.cpu.dcache.overall_misses::total 9968603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88929958000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88929958000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000514273 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4000514273 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 284000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 284000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92930472273 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92930472273 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92930472273 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92930472273 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474589 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474589 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -763,470 +767,474 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209570 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210099 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210099 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408418 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408418 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353376 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353376 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353370 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353370 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9275.662322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9275.662322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10496.042905 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10496.042905 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20285.714286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20285.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9322.323051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9322.323051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9322.316504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9322.316504 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 330469 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 108734 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121517 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks -system.cpu.dcache.writebacks::total 5470634 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.719529 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.469699 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470636 # number of writebacks +system.cpu.dcache.writebacks::total 5470636 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338792 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338792 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158657 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158657 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4497449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4497449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4497449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4497449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248659 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248659 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222488 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222488 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5471147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471151 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43429617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43429617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285050165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285050165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 217500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 217500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45714667165 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45714667165 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45714884665 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45714884665 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8274.421524 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8274.421524 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.442294 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.442294 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54375 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54375 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8355.591097 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8355.591097 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8355.624742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8355.624742 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 447 # number of replacements -system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 427.481000 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32274286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35701.643805 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 427.481000 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.834924 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.834924 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits -system.cpu.icache.overall_hits::total 32273898 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses -system.cpu.icache.overall_misses::total 1145 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64551760 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64551760 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32274286 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32274286 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32274286 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32274286 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32274286 # number of overall hits +system.cpu.icache.overall_hits::total 32274286 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1142 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1142 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1142 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1142 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1142 # number of overall misses +system.cpu.icache.overall_misses::total 1142 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61976480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61976480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61976480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61976480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61976480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61976480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32275428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32275428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32275428 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32275428 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32275428 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32275428 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54270.122592 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54270.122592 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54270.122592 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54270.122592 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19008 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.794521 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.600000 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 447 # number of writebacks system.cpu.icache.writebacks::total 447 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 237 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 237 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 237 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 237 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 237 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50842984 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50842984 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50842984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50842984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50842984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50842984 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56180.092818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56180.092818 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 4982437 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296601 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 273114 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 248 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074231 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 123 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11197.361342 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5291777 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14677 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 360.548954 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::writebacks 11137.339599 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 60.021743 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.679769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003663 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.683433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 61 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14493 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3478 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9594 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 837 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003723 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884583 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180526187 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180526187 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 5457780 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5457780 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10426 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10426 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 226022 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 226022 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 241570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 285879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44309000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 241570000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1152510987 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.773481 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000753 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058605 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2737.542327 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95681.818182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95681.818182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63298.571429 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63298.571429 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67882.553606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67882.553606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69404.952658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3593.825187 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943139 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_filter.tot_snoops 302176 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5457869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318447 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226521 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415198 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 319939 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 11456 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318574 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5952 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790626 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052683 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223400 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485560 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305065 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5790626 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942652515 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206727492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 16175 # Transaction distribution -system.membus.trans_dist::WritebackDirty 175 # Transaction distribution -system.membus.trans_dist::CleanEvict 63 # Transaction distribution +system.membus.snoop_filter.tot_requests 18642 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3008 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18174 # Transaction distribution +system.membus.trans_dist::WritebackDirty 89 # Transaction distribution +system.membus.trans_dist::CleanEvict 34 # Transaction distribution system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 341 # Transaction distribution -system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 18175 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37156 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1190592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1190592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 16759 # Request fanout histogram +system.membus.snoop_fanout::samples 18519 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18519 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16759 # Request fanout histogram -system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_fanout::total 18519 # Request fanout histogram +system.membus.reqLayer0.occupancy 29524488 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 97237655 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b912f8d81..b27dfcb1b 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361598 # Number of seconds simulated -sim_ticks 361597758500 # Number of ticks simulated -final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361613 # Number of seconds simulated +sim_ticks 361613361500 # Number of ticks simulated +final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1165746 # Simulator instruction rate (inst/s) -host_op_rate 1165794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1728825291 # Simulator tick rate (ticks/s) -host_mem_usage 381188 # Number of bytes of host memory used -host_seconds 209.16 # Real time elapsed on the host +host_inst_rate 1370596 # Simulator instruction rate (inst/s) +host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2032709522 # Simulator tick rate (ticks/s) +host_mem_usage 385816 # Number of bytes of host memory used +host_seconds 177.90 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory system.physmem.bytes_read::total 998592 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 56256 # Nu system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 723195517 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 723226723 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles +system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -92,25 +92,25 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -131,16 +131,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -161,16 +161,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,16 +189,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -209,26 +209,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id @@ -237,7 +237,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 781 system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -250,12 +250,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -268,12 +268,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -288,48 +288,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits @@ -358,18 +356,18 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) @@ -398,18 +396,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -428,18 +426,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses @@ -452,25 +450,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution @@ -504,7 +502,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 4b965d579..1e87ba0e2 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065987 # Number of seconds simulated -sim_ticks 65986743500 # Number of ticks simulated -final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065554 # Number of seconds simulated +sim_ticks 65553895500 # Number of ticks simulated +final_tick 65553895500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86207 # Simulator instruction rate (inst/s) -host_op_rate 151797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36005878 # Simulator tick rate (ticks/s) -host_mem_usage 411344 # Number of bytes of host memory used -host_seconds 1832.67 # Real time elapsed on the host +host_inst_rate 122580 # Simulator instruction rate (inst/s) +host_op_rate 215844 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50862026 # Simulator tick rate (ticks/s) +host_mem_usage 417260 # Number of bytes of host memory used +host_seconds 1288.86 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory -system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 69632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1890944 # Number of bytes read from this memory +system.physmem.bytes_read::total 1960576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69632 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory system.physmem.bytes_written::total 17920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29546 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30634 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory system.physmem.num_writes::total 280 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30622 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 1062210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28845639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29907849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1062210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1062210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 273363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 273363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 273363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1062210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28845639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30181212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30634 # Number of read requests accepted system.physmem.writeReqs 280 # Number of write requests accepted -system.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 30634 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue -system.physmem.bytesWritten 16064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 1951616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue +system.physmem.bytesWritten 16000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1960576 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1932 # Per bank write bursts -system.physmem.perBankRdBursts::1 2084 # Per bank write bursts -system.physmem.perBankRdBursts::2 2041 # Per bank write bursts -system.physmem.perBankRdBursts::3 1935 # Per bank write bursts -system.physmem.perBankRdBursts::4 2086 # Per bank write bursts -system.physmem.perBankRdBursts::5 1909 # Per bank write bursts -system.physmem.perBankRdBursts::6 1974 # Per bank write bursts -system.physmem.perBankRdBursts::7 1865 # Per bank write bursts -system.physmem.perBankRdBursts::8 1948 # Per bank write bursts +system.physmem.perBankRdBursts::0 1938 # Per bank write bursts +system.physmem.perBankRdBursts::1 2083 # Per bank write bursts +system.physmem.perBankRdBursts::2 2040 # Per bank write bursts +system.physmem.perBankRdBursts::3 1941 # Per bank write bursts +system.physmem.perBankRdBursts::4 2041 # Per bank write bursts +system.physmem.perBankRdBursts::5 1918 # Per bank write bursts +system.physmem.perBankRdBursts::6 1976 # Per bank write bursts +system.physmem.perBankRdBursts::7 1870 # Per bank write bursts +system.physmem.perBankRdBursts::8 1951 # Per bank write bursts system.physmem.perBankRdBursts::9 1940 # Per bank write bursts -system.physmem.perBankRdBursts::10 1806 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1799 # Per bank write bursts -system.physmem.perBankRdBursts::14 1828 # Per bank write bursts +system.physmem.perBankRdBursts::14 1827 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts system.physmem.perBankWrBursts::0 10 # Per bank write bursts system.physmem.perBankWrBursts::1 107 # Per bank write bursts -system.physmem.perBankWrBursts::2 30 # Per bank write bursts -system.physmem.perBankWrBursts::3 12 # Per bank write bursts -system.physmem.perBankWrBursts::4 60 # Per bank write bursts -system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::2 31 # Per bank write bursts +system.physmem.perBankWrBursts::3 25 # Per bank write bursts +system.physmem.perBankWrBursts::4 39 # Per bank write bursts +system.physmem.perBankWrBursts::5 13 # Per bank write bursts system.physmem.perBankWrBursts::6 16 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 1 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65986546500 # Total gap between requests +system.physmem.totGap 65553697500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30622 # Read request sizes (log2) +system.physmem.readPktSize::6 30634 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,11 +98,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 280 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -147,18 +147,18 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see @@ -194,336 +194,335 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 687.860091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 477.665686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 399.129385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 441 15.42% 15.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 263 9.20% 24.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 134 4.69% 29.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 136 4.76% 34.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 118 4.13% 38.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 116 4.06% 42.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 85 2.97% 45.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 96 3.36% 48.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1470 51.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2859 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2173.928571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.222071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8074.812153 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.857143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.849200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.534522 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 13 92.86% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads -system.physmem.totQLat 136557750 # Total ticks spent queuing -system.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst +system.physmem.totQLat 136299000 # Total ticks spent queuing +system.physmem.totMemAccLat 708061500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4469.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23219.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing -system.physmem.readRowHits 27745 # Number of row buffer hits during reads -system.physmem.writeRowHits 178 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes -system.physmem.avgGap 2135348.73 # Average gap between requests -system.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.125124 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.62 # Average write queue length when enqueuing +system.physmem.readRowHits 27721 # Number of row buffer hits during reads +system.physmem.writeRowHits 161 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.50 # Row buffer hit rate for writes +system.physmem.avgGap 2120518.13 # Average gap between requests +system.physmem.pageHitRate 90.60 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11740680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6406125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 123169800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1568160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3052855305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36653676000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 44130982710 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.213820 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60959756000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2188940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2404016500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9873360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5387250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114558600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.182663 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem_1.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3230070300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36498224250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 44139732240 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.347293 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 60700713000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2188940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2663059500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40828848 # Number of BP lookups -system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40360668 # Number of BP lookups +system.cpu.branchPred.condPredicted 40360668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1392637 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26664097 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 5988252 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 86625 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26664097 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21157452 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5506645 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 511906 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131973488 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131107792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30523578 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219647427 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40360668 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27145704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 98945290 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2900833 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 518 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 114030 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29742559 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 352958 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 20 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131040277 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.407509 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65532629 50.01% 50.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4015050 3.06% 53.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3611452 2.76% 55.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6110552 4.66% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7743592 5.91% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5553299 4.24% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3377797 2.58% 73.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2818268 2.15% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32277638 24.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40712149 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44736331 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131040277 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307843 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.675319 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15257836 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64260169 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40205069 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9866787 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1450416 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 361840570 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1450416 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20789312 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11161609 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17754 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44252475 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53368711 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352352816 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16475 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 802883 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46797603 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4838735 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 354809982 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 933969547 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575070468 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 25233 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 501 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75597235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 487 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 488 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64661942 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112312024 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38476139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51587404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9144280 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343861767 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317818488 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169830 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65674018 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 101673382 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4270 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131040277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.425350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.164581 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35194225 26.86% 26.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20112862 15.35% 42.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17093441 13.04% 55.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17641161 13.46% 68.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15328111 11.70% 80.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12869587 9.82% 90.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6689257 5.10% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4093724 3.12% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2017909 1.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131040277 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 366862 8.95% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3538662 86.29% 95.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 195200 4.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181791277 57.20% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11724 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 408 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 305 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101272470 31.86% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34708964 10.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 319025181 # Type of FU issued -system.cpu.iq.rate 2.417343 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317818488 # Type of FU issued +system.cpu.iq.rate 2.424101 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4100724 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012903 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770927721 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 409562927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313648272 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 20086 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 38326 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4607 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321877132 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8740 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57541030 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21532639 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67356 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 63407 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7036387 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3908 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141249 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1450416 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8045146 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3020269 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343866482 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 122594 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112312024 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38476139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1910 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3213 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3025719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 63407 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 529775 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1033204 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1562979 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315414153 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100518036 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2404335 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 135188403 # number of memory reference insts executed -system.cpu.iew.exec_branches 32185799 # Number of branches executed -system.cpu.iew.exec_stores 34371814 # Number of stores executed -system.cpu.iew.exec_rate 2.398114 # Inst execution rate -system.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314642345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 238446717 # num instructions producing a value -system.cpu.iew.wb_consumers 344411432 # num instructions consuming a value -system.cpu.iew.wb_rate 2.384133 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134824639 # number of memory reference insts executed +system.cpu.iew.exec_branches 32104448 # Number of branches executed +system.cpu.iew.exec_stores 34306603 # Number of stores executed +system.cpu.iew.exec_rate 2.405762 # Inst execution rate +system.cpu.iew.wb_sent 314286106 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313652879 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237682188 # num instructions producing a value +system.cpu.iew.wb_consumers 343423954 # num instructions consuming a value +system.cpu.iew.wb_rate 2.392328 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 65797430 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1399141 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121633848 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.287130 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.051606 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56556051 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16464352 13.54% 60.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11233282 9.24% 69.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8748892 7.19% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2045691 1.68% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1756798 1.44% 79.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 927336 0.76% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727466 0.60% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23173980 19.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 121633848 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,337 +568,336 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 445462066 # The number of ROB reads -system.cpu.rob.rob_writes 702797421 # The number of ROB writes -system.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23173980 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 442449762 # The number of ROB reads +system.cpu.rob.rob_writes 697455131 # The number of ROB writes +system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 67515 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.835336 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads -system.cpu.ipc 1.197123 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 504041942 # number of integer regfile reads -system.cpu.int_regfile_writes 248656420 # number of integer regfile writes -system.cpu.fp_regfile_reads 4180 # number of floating regfile reads -system.cpu.fp_regfile_writes 782 # number of floating regfile writes -system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads -system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes -system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads +system.cpu.cpi 0.829856 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829856 # CPI: Total CPI of All Threads +system.cpu.ipc 1.205028 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.205028 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502814986 # number of integer regfile reads +system.cpu.int_regfile_writes 247784196 # number of integer regfile writes +system.cpu.fp_regfile_reads 4396 # number of floating regfile reads +system.cpu.fp_regfile_writes 732 # number of floating regfile writes +system.cpu.cc_regfile_reads 109093589 # number of cc regfile reads +system.cpu.cc_regfile_writes 65488596 # number of cc regfile writes +system.cpu.misc_regfile_reads 201890594 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073508 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073601 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.108072 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71473739 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077697 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.400463 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21041764500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.108072 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993190 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 507 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3433 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits -system.cpu.dcache.overall_hits::total 71894591 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses -system.cpu.dcache.overall_misses::total 2787704 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150601371 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150601371 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40127755 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40127755 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345984 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345984 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71473739 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71473739 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71473739 # number of overall hits +system.cpu.dcache.overall_hits::total 71473739 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2694330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2694330 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93768 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93768 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2788098 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2788098 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2788098 # number of overall misses +system.cpu.dcache.overall_misses::total 2788098 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32345718500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32345718500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2982305493 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2982305493 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35328023993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35328023993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35328023993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35328023993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42822085 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42822085 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74261837 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74261837 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74261837 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74261837 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062919 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062919 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002982 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002982 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037544 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037544 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037544 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037544 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12005.106464 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12005.106464 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31805.152003 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31805.152003 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12671.012279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12671.012279 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 218790 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 393 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43059 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks -system.cpu.dcache.writebacks::total 2066969 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 710100 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 710100 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995754 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995754 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81850 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81850 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077604 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27017191493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046153 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046153 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002603 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002603 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 93 # number of replacements -system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.081168 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.250000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2067196 # number of writebacks +system.cpu.dcache.writebacks::total 2067196 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698496 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 698496 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11905 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11905 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 710401 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 710401 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 710401 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 710401 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995834 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995834 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81863 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81863 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077697 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077697 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077697 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077697 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24223051500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24223051500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2825101993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2825101993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27048153493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27048153493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27048153493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27048153493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046608 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046608 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.806718 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.806718 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34510.120482 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34510.120482 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 91 # number of replacements +system.cpu.icache.tags.tagsinuse 875.979350 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29741086 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26625.860340 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits -system.cpu.icache.overall_hits::total 29996478 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses -system.cpu.icache.overall_misses::total 1445 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 106088999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 106088999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 106088999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 106088999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29997923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29997923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29997923 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29997923 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29997923 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29997923 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000048 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29988 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29650 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915161 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33250579 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33250579 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2067196 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2067196 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78090.073529 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75660.682226 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75660.682226 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74214.973559 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74214.973559 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -908,122 +906,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks system.cpu.l2cache.writebacks::total 280 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28989 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28989 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1856506500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74082000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74082000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 36573000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36573000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74082000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1893079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1967161500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74082000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1893079500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1967161500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354004 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354004 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974038 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000279 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000279 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014736 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64041.757218 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64041.757218 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68090.073529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68090.073529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65660.682226 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65660.682226 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4152506 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073696 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 650 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 91 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995808 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231320 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265273152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 663 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 17920 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2079477 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012972 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079127 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 350 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079477 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143540000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1640 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 3116545500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 30966 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 332 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1645 # Transaction distribution system.membus.trans_dist::WritebackDirty 280 # Transaction distribution -system.membus.trans_dist::CleanEvict 45 # Transaction distribution -system.membus.trans_dist::ReadExReq 28982 # Transaction distribution -system.membus.trans_dist::ReadExResp 28982 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 52 # Transaction distribution +system.membus.trans_dist::ReadExReq 28989 # Transaction distribution +system.membus.trans_dist::ReadExResp 28989 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1645 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1978496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1978496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1978496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30947 # Request fanout histogram +system.membus.snoop_fanout::samples 30634 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30634 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30947 # Request fanout histogram -system.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30634 # Request fanout histogram +system.membus.reqLayer0.occupancy 43502500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161439750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 8197faf7d..683cfaa02 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366199 # Number of seconds simulated -sim_ticks 366199170500 # Number of ticks simulated -final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366229 # Number of seconds simulated +sim_ticks 366229314500 # Number of ticks simulated +final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 454673 # Simulator instruction rate (inst/s) -host_op_rate 800606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1053878980 # Simulator tick rate (ticks/s) -host_mem_usage 406480 # Number of bytes of host memory used -host_seconds 347.48 # Real time elapsed on the host +host_inst_rate 561124 # Simulator instruction rate (inst/s) +host_op_rate 988050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1300728257 # Simulator tick rate (ticks/s) +host_mem_usage 412916 # Number of bytes of host memory used +host_seconds 281.56 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory -system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory +system.physmem.bytes_read::total 1922944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory -system.physmem.bytes_written::total 6528 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory +system.physmem.bytes_written::total 6656 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory -system.physmem.num_writes::total 102 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30046 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732398341 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 732458629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -66,7 +66,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles +system.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -105,25 +105,25 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits @@ -140,14 +140,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25500310500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2830649000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28330959500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28330959500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28330959500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28330959500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -164,14 +164,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13707.452092 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13707.452092 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,14 +188,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26264130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26264130500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -204,22 +204,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.626582 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.626582 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -229,7 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 715 system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits @@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50660000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50660000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50660000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50660000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50660000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62698.019802 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62698.019802 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,48 +280,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49852000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 313 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 315 # number of replacements +system.cpu.l2cache.tags.tagsinuse 21080.806353 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4100347 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30047 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 136.464439 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::writebacks 0.624695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000019 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.626347 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.643335 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29732 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33073199 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33073199 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits @@ -330,38 +330,38 @@ system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1960501 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2037586 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2037591 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits -system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2037586 # number of overall hits +system.cpu.l2cache.overall_hits::total 2037591 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 219 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 219 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29243 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30046 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses -system.cpu.l2cache.overall_misses::total 30044 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 29243 # number of overall misses +system.cpu.l2cache.overall_misses::total 30046 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1755983000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 48585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1769232500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1817817500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 48585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1769232500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1817817500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) @@ -382,91 +382,91 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014532 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014532 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks -system.cpu.l2cache.writebacks::total 102 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks +system.cpu.l2cache.writebacks::total 104 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30046 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 29243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30046 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution @@ -479,53 +479,59 @@ system.cpu.toL2Bus.pkt_count::total 6198031 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 313 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6528 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoops 315 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6656 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2067952 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2067952 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1020 # Transaction distribution -system.membus.trans_dist::WritebackDirty 102 # Transaction distribution +system.membus.snoop_filter.tot_requests 30164 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 118 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1022 # Transaction distribution +system.membus.trans_dist::WritebackDirty 104 # Transaction distribution system.membus.trans_dist::CleanEvict 14 # Transaction distribution system.membus.trans_dist::ReadExReq 29024 # Transaction distribution system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1022 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929600 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30160 # Request fanout histogram +system.membus.snoop_fanout::samples 30046 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30046 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30160 # Request fanout histogram -system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30046 # Request fanout histogram +system.membus.reqLayer0.occupancy 30614500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 150230000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 2a8feed05..eadbc59cf 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417310 # Number of seconds simulated -sim_ticks 417309765500 # Number of ticks simulated -final_tick 417309765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417806 # Number of seconds simulated +sim_ticks 417805983500 # Number of ticks simulated +final_tick 417805983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274693 # Simulator instruction rate (inst/s) -host_op_rate 274693 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187337647 # Simulator tick rate (ticks/s) -host_mem_usage 252076 # Number of bytes of host memory used -host_seconds 2227.58 # Real time elapsed on the host +host_inst_rate 243916 # Simulator instruction rate (inst/s) +host_op_rate 243916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 166545939 # Simulator tick rate (ticks/s) +host_mem_usage 257728 # Number of bytes of host memory used +host_seconds 2508.65 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 156544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24144128 # Number of bytes read from this memory -system.physmem.bytes_read::total 24300672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18790848 # Number of bytes written to this memory -system.physmem.bytes_written::total 18790848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 379698 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293607 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293607 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 375127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57856609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58231736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 375127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 375127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45028536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45028536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45028536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 375127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57856609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 103260272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 379698 # Number of read requests accepted -system.physmem.writeReqs 293607 # Number of write requests accepted -system.physmem.readBursts 379698 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293607 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24277632 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23040 # Total number of bytes read from write queue -system.physmem.bytesWritten 18789440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24300672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18790848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 360 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 156672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24196352 # Number of bytes read from this memory +system.physmem.bytes_read::total 24353024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18839232 # Number of bytes written to this memory +system.physmem.bytes_written::total 18839232 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 378068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294363 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294363 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 374987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57912890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58287878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 374987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 374987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45090862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45090862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45090862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 374987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57912890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 103378740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380516 # Number of read requests accepted +system.physmem.writeReqs 294363 # Number of write requests accepted +system.physmem.readBursts 380516 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294363 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24332224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue +system.physmem.bytesWritten 18837888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24353024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18839232 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23694 # Per bank write bursts -system.physmem.perBankRdBursts::1 23158 # Per bank write bursts -system.physmem.perBankRdBursts::2 23444 # Per bank write bursts -system.physmem.perBankRdBursts::3 24500 # Per bank write bursts -system.physmem.perBankRdBursts::4 25443 # Per bank write bursts -system.physmem.perBankRdBursts::5 23576 # Per bank write bursts -system.physmem.perBankRdBursts::6 23654 # Per bank write bursts -system.physmem.perBankRdBursts::7 23908 # Per bank write bursts -system.physmem.perBankRdBursts::8 23181 # Per bank write bursts -system.physmem.perBankRdBursts::9 23984 # Per bank write bursts -system.physmem.perBankRdBursts::10 24716 # Per bank write bursts -system.physmem.perBankRdBursts::11 22779 # Per bank write bursts -system.physmem.perBankRdBursts::12 23723 # Per bank write bursts -system.physmem.perBankRdBursts::13 24392 # Per bank write bursts -system.physmem.perBankRdBursts::14 22740 # Per bank write bursts -system.physmem.perBankRdBursts::15 22446 # Per bank write bursts -system.physmem.perBankWrBursts::0 17782 # Per bank write bursts -system.physmem.perBankWrBursts::1 17457 # Per bank write bursts -system.physmem.perBankWrBursts::2 17944 # Per bank write bursts -system.physmem.perBankWrBursts::3 18853 # Per bank write bursts -system.physmem.perBankWrBursts::4 19512 # Per bank write bursts -system.physmem.perBankWrBursts::5 18592 # Per bank write bursts -system.physmem.perBankWrBursts::6 18778 # Per bank write bursts -system.physmem.perBankWrBursts::7 18657 # Per bank write bursts -system.physmem.perBankWrBursts::8 18440 # Per bank write bursts -system.physmem.perBankWrBursts::9 18940 # Per bank write bursts -system.physmem.perBankWrBursts::10 19258 # Per bank write bursts -system.physmem.perBankWrBursts::11 18049 # Per bank write bursts -system.physmem.perBankWrBursts::12 18265 # Per bank write bursts -system.physmem.perBankWrBursts::13 18732 # Per bank write bursts -system.physmem.perBankWrBursts::14 17195 # Per bank write bursts -system.physmem.perBankWrBursts::15 17131 # Per bank write bursts +system.physmem.perBankRdBursts::0 23763 # Per bank write bursts +system.physmem.perBankRdBursts::1 23178 # Per bank write bursts +system.physmem.perBankRdBursts::2 23498 # Per bank write bursts +system.physmem.perBankRdBursts::3 24610 # Per bank write bursts +system.physmem.perBankRdBursts::4 25501 # Per bank write bursts +system.physmem.perBankRdBursts::5 23627 # Per bank write bursts +system.physmem.perBankRdBursts::6 23703 # Per bank write bursts +system.physmem.perBankRdBursts::7 23985 # Per bank write bursts +system.physmem.perBankRdBursts::8 23235 # Per bank write bursts +system.physmem.perBankRdBursts::9 24022 # Per bank write bursts +system.physmem.perBankRdBursts::10 24757 # Per bank write bursts +system.physmem.perBankRdBursts::11 22829 # Per bank write bursts +system.physmem.perBankRdBursts::12 23792 # Per bank write bursts +system.physmem.perBankRdBursts::13 24451 # Per bank write bursts +system.physmem.perBankRdBursts::14 22759 # Per bank write bursts +system.physmem.perBankRdBursts::15 22481 # Per bank write bursts +system.physmem.perBankWrBursts::0 17837 # Per bank write bursts +system.physmem.perBankWrBursts::1 17476 # Per bank write bursts +system.physmem.perBankWrBursts::2 17996 # Per bank write bursts +system.physmem.perBankWrBursts::3 18950 # Per bank write bursts +system.physmem.perBankWrBursts::4 19553 # Per bank write bursts +system.physmem.perBankWrBursts::5 18644 # Per bank write bursts +system.physmem.perBankWrBursts::6 18825 # Per bank write bursts +system.physmem.perBankWrBursts::7 18731 # Per bank write bursts +system.physmem.perBankWrBursts::8 18487 # Per bank write bursts +system.physmem.perBankWrBursts::9 18977 # Per bank write bursts +system.physmem.perBankWrBursts::10 19289 # Per bank write bursts +system.physmem.perBankWrBursts::11 18103 # Per bank write bursts +system.physmem.perBankWrBursts::12 18331 # Per bank write bursts +system.physmem.perBankWrBursts::13 18779 # Per bank write bursts +system.physmem.perBankWrBursts::14 17209 # Per bank write bursts +system.physmem.perBankWrBursts::15 17155 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417309678500 # Total gap between requests +system.physmem.totGap 417805895500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 379698 # Read request sizes (log2) +system.physmem.readPktSize::6 380516 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293607 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1069 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294363 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 379108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1078 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,37 +145,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -194,102 +194,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142524 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.166540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.513789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.994907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50939 35.74% 35.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38821 27.24% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13298 9.33% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8416 5.90% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5517 3.87% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3864 2.71% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2991 2.10% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2664 1.87% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16014 11.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142524 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.890986 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 236.476851 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17319 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 138680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.287453 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.207223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.580337 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47172 34.01% 34.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38791 27.97% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13255 9.56% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8020 5.78% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5116 3.69% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3846 2.77% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3216 2.32% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2646 1.91% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16618 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 138680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.716228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.015056 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.517715 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17502 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.942809 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.869717 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.235744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 17276 99.70% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 34 0.20% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads -system.physmem.totQLat 4040781000 # Total ticks spent queuing -system.physmem.totMemAccLat 11153368500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1896690000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10652.19 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.812818 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.784450 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.984212 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10318 58.94% 58.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 249 1.42% 60.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6843 39.09% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 94 0.54% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads +system.physmem.totQLat 4112094750 # Total ticks spent queuing +system.physmem.totMemAccLat 11240676000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1900955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10815.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29402.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.03 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.03 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29565.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.45 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.54 # Average write queue length when enqueuing -system.physmem.readRowHits 314151 # Number of row buffer hits during reads -system.physmem.writeRowHits 216242 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.65 # Row buffer hit rate for writes -system.physmem.avgGap 619792.93 # Average gap between requests -system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 548954280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299528625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1492608000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 956117520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27256273200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62660545740 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 195417206250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 288631233615 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.656457 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 324545157250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13934700000 # Time in different power states +system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing +system.physmem.readRowHits 314275 # Number of row buffer hits during reads +system.physmem.writeRowHits 221571 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.27 # Row buffer hit rate for writes +system.physmem.avgGap 619082.67 # Average gap between requests +system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 534363480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 291567375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1496445600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 959027040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27288821040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62100331785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 196207614000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 288878170320 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.422544 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 325857976500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13951340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78824485250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77993346000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 528194520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288201375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465682400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 946002240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27256273200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59613271875 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 198090253500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288187879110 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.594032 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 329008482750 # Time in different power states -system.physmem_1.memoryStateTime::REF 13934700000 # Time in different power states +system.physmem_1.actEnergy 513853200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280376250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1468724400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 948101760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27288821040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59269027500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 198691214250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288460118400 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.421947 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 330008811500 # Time in different power states +system.physmem_1.memoryStateTime::REF 13951340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 74361159750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73843223000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 124433672 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 124433678 # Number of BP lookups system.cpu.branchPred.condPredicted 87996740 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6213240 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71713354 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67453022 # Number of BTB hits +system.cpu.branchPred.BTBLookups 71713362 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67453030 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 94.059221 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15161941 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 15161942 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1121063 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 7034 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 4431 # Number of indirect target hits. @@ -300,22 +298,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149830728 # DTB read hits +system.cpu.dtb.read_hits 149830726 # DTB read hits system.cpu.dtb.read_misses 559355 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150390083 # DTB read accesses +system.cpu.dtb.read_accesses 150390081 # DTB read accesses system.cpu.dtb.write_hits 57603616 # DTB write hits system.cpu.dtb.write_misses 71398 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 57675014 # DTB write accesses -system.cpu.dtb.data_hits 207434344 # DTB hits +system.cpu.dtb.data_hits 207434342 # DTB hits system.cpu.dtb.data_misses 630753 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 208065097 # DTB accesses -system.cpu.itb.fetch_hits 227957182 # ITB hits +system.cpu.dtb.data_accesses 208065095 # DTB accesses +system.cpu.itb.fetch_hits 227957240 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 227957230 # ITB accesses +system.cpu.itb.fetch_accesses 227957288 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,16 +327,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 834619531 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 835611967 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14840405 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 14840404 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.363977 # CPI: cycles per instruction -system.cpu.ipc 0.733150 # IPC: instructions per cycle +system.cpu.cpi 1.365599 # CPI: cycles per instruction +system.cpu.ipc 0.732280 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction @@ -374,59 +372,59 @@ system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 611901617 # Class of committed instruction -system.cpu.tickCycles 746834256 # Number of cycles that the object actually ticked -system.cpu.idleCycles 87785275 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 746834854 # Number of cycles that the object actually ticked +system.cpu.idleCycles 88777113 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2535509 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.685849 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 203187427 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4087.671717 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 203187431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2539605 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 80.007492 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1653740500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.685849 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997970 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 80.007494 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1657773500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.671717 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997967 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997967 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 415624619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 415624619 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tag_accesses 415624617 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 415624617 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 147521260 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147521260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666167 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666167 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 203187427 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 203187427 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 203187427 # number of overall hits -system.cpu.dcache.overall_hits::total 203187427 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1811213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1811213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543867 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543867 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3355080 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3355080 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3355080 # number of overall misses -system.cpu.dcache.overall_misses::total 3355080 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36182187000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36182187000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 47720909500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 47720909500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83903096500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83903096500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83903096500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83903096500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 149332473 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 149332473 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::cpu.data 55666171 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666171 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 203187431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 203187431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 203187431 # number of overall hits +system.cpu.dcache.overall_hits::total 203187431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1811212 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1811212 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543863 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543863 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3355075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3355075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3355075 # number of overall misses +system.cpu.dcache.overall_misses::total 3355075 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36424837000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36424837000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48227162000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48227162000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84651999000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84651999000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84651999000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84651999000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 149332472 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 149332472 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206542507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206542507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206542507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206542507 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206542506 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206542506 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206542506 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206542506 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012129 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012129 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses @@ -435,30 +433,30 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016244 system.cpu.dcache.demand_miss_rate::total 0.016244 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19976.770816 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19976.770816 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30909.987389 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30909.987389 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25007.778205 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25007.778205 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25007.778205 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25007.778205 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20110.752910 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20110.752910 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31237.980313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31237.980313 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25231.030305 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25231.030305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25231.030305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25231.030305 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2339608 # number of writebacks -system.cpu.dcache.writebacks::total 2339608 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46417 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 46417 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769058 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769058 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 815475 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 815475 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 815475 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 815475 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 2339290 # number of writebacks +system.cpu.dcache.writebacks::total 2339290 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46416 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 46416 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769054 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769054 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 815470 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 815470 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 815470 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 815470 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764796 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1764796 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774809 # number of WriteReq MSHR misses @@ -467,14 +465,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2539605 system.cpu.dcache.demand_mshr_misses::total 2539605 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2539605 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2539605 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33173534500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33173534500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23341678000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23341678000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56515212500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56515212500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56515212500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56515212500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33407226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33407226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23596131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23596131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57003358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 57003358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57003358000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 57003358000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011818 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011818 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -483,24 +481,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012296 system.cpu.dcache.demand_mshr_miss_rate::total 0.012296 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012296 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18797.376297 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18797.376297 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30125.718726 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30125.718726 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22253.544350 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22253.544350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22253.544350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22253.544350 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18929.795002 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18929.795002 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30454.126759 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30454.126759 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22445.757510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22445.757510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.757510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.757510 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3176 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.866766 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 227952177 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1116.932847 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 227952235 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5005 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45544.890509 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 45544.902098 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.866766 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545345 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545345 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.932847 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545377 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545377 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id @@ -508,45 +506,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 17 system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1592 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 455919369 # Number of tag accesses -system.cpu.icache.tags.data_accesses 455919369 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 227952177 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 227952177 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 227952177 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 227952177 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 227952177 # number of overall hits -system.cpu.icache.overall_hits::total 227952177 # number of overall hits +system.cpu.icache.tags.tag_accesses 455919485 # Number of tag accesses +system.cpu.icache.tags.data_accesses 455919485 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 227952235 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 227952235 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 227952235 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 227952235 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 227952235 # number of overall hits +system.cpu.icache.overall_hits::total 227952235 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5005 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5005 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5005 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5005 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5005 # number of overall misses system.cpu.icache.overall_misses::total 5005 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 230776000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 230776000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 230776000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 230776000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 230776000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 230776000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 227957182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 227957182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 227957182 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 227957182 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 227957182 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 227957182 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 240293500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 240293500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 240293500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 240293500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 240293500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 240293500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 227957240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 227957240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 227957240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 227957240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 227957240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 227957240 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46109.090909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46109.090909 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46109.090909 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46109.090909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46109.090909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46109.090909 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48010.689311 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48010.689311 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48010.689311 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48010.689311 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48010.689311 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48010.689311 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,90 +559,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5005 system.cpu.icache.demand_mshr_misses::total 5005 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5005 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5005 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 225771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 225771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 225771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 225771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 225771000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 225771000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 235288500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 235288500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 235288500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 235288500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 235288500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 235288500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45109.090909 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45109.090909 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45109.090909 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 45109.090909 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45109.090909 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 45109.090909 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 347716 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29508.447379 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3909297 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380147 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.283646 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 191524989500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21334.159610 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.927719 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8013.360050 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.651067 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004911 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.244548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.900526 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32431 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18759 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989716 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41824659 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41824659 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2339608 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2339608 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47010.689311 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47010.689311 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47010.689311 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47010.689311 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47010.689311 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12292449000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12292449000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176434000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26702568500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26879002500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176434000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26702568500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26879002500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.488711 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097049 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097049 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148548 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149217 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148548 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149217 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68611.667192 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68611.667192 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68240.188062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68240.188062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70542.753017 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70542.753017 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68240.188062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69486.714451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69478.684375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68240.188062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69486.714451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69478.684375 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.489111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097425 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097425 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149538 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149538 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69796.856988 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69796.856988 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72072.712418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72072.712418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71630.143931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71630.143931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72072.712418 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70629.009861 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70638.297733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72072.712418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70629.009861 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70638.297733 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 5083295 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538685 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2395 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2395 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2446 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2446 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1766458 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 250010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 250480 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 778152 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 778152 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 5005 # Transaction distribution @@ -762,53 +760,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614719 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7627905 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 523584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312269632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312793216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 347716 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18790848 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2892326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.028764 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312249280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312772864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348624 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18839232 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2893234 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029064 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2889931 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2395 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2890788 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2446 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2892326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4884431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2893234 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4884113500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7507500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809407500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 173393 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution -system.membus.trans_dist::CleanEvict 51719 # Transaction distribution -system.membus.trans_dist::ReadExReq 206305 # Transaction distribution -system.membus.trans_dist::ReadExResp 206305 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 173393 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1104722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43091520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43091520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 726699 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 346183 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 174058 # Transaction distribution +system.membus.trans_dist::WritebackDirty 294363 # Transaction distribution +system.membus.trans_dist::CleanEvict 51820 # Transaction distribution +system.membus.trans_dist::ReadExReq 206458 # Transaction distribution +system.membus.trans_dist::ReadExResp 206458 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174058 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1107215 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1107215 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43192256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43192256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 725024 # Request fanout histogram +system.membus.snoop_fanout::samples 380516 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 725024 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 380516 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 725024 # Request fanout histogram -system.membus.reqLayer0.occupancy 2021857500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 380516 # Request fanout histogram +system.membus.reqLayer0.occupancy 2021728500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2009466000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2014027500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 55f9db9e0..3a2939b58 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366439 # Number of seconds simulated -sim_ticks 366439129500 # Number of ticks simulated -final_tick 366439129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366632 # Number of seconds simulated +sim_ticks 366631719500 # Number of ticks simulated +final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188596 # Simulator instruction rate (inst/s) -host_op_rate 204275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136422977 # Simulator tick rate (ticks/s) -host_mem_usage 271112 # Number of bytes of host memory used -host_seconds 2686.05 # Real time elapsed on the host +host_inst_rate 211005 # Simulator instruction rate (inst/s) +host_op_rate 228546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152712719 # Simulator tick rate (ticks/s) +host_mem_usage 277288 # Number of bytes of host memory used +host_seconds 2400.79 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9028544 # Number of bytes read from this memory -system.physmem.bytes_read::total 9208384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory +system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6219648 # Number of bytes written to this memory -system.physmem.bytes_written::total 6219648 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory +system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97182 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97182 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 490777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24638591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25129369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 490777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16973209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16973209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16973209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 490777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24638591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143881 # Number of read requests accepted -system.physmem.writeReqs 97182 # Number of write requests accepted -system.physmem.readBursts 143881 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97182 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9201344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue -system.physmem.bytesWritten 6217600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9208384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6219648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144269 # Number of read requests accepted +system.physmem.writeReqs 97528 # Number of write requests accepted +system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9364 # Per bank write bursts -system.physmem.perBankRdBursts::1 8912 # Per bank write bursts -system.physmem.perBankRdBursts::2 8949 # Per bank write bursts -system.physmem.perBankRdBursts::3 8655 # Per bank write bursts -system.physmem.perBankRdBursts::4 9392 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 8959 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8596 # Per bank write bursts -system.physmem.perBankRdBursts::9 8629 # Per bank write bursts -system.physmem.perBankRdBursts::10 8739 # Per bank write bursts -system.physmem.perBankRdBursts::11 9451 # Per bank write bursts -system.physmem.perBankRdBursts::12 9334 # Per bank write bursts -system.physmem.perBankRdBursts::13 9512 # Per bank write bursts -system.physmem.perBankRdBursts::14 8707 # Per bank write bursts -system.physmem.perBankRdBursts::15 9117 # Per bank write bursts -system.physmem.perBankWrBursts::0 6231 # Per bank write bursts -system.physmem.perBankWrBursts::1 6102 # Per bank write bursts -system.physmem.perBankWrBursts::2 6028 # Per bank write bursts -system.physmem.perBankWrBursts::3 5879 # Per bank write bursts -system.physmem.perBankWrBursts::4 6243 # Per bank write bursts -system.physmem.perBankWrBursts::5 6239 # Per bank write bursts -system.physmem.perBankWrBursts::6 6050 # Per bank write bursts -system.physmem.perBankWrBursts::7 5507 # Per bank write bursts -system.physmem.perBankWrBursts::8 5786 # Per bank write bursts -system.physmem.perBankWrBursts::9 5859 # Per bank write bursts -system.physmem.perBankWrBursts::10 5978 # Per bank write bursts -system.physmem.perBankWrBursts::11 6493 # Per bank write bursts -system.physmem.perBankWrBursts::12 6351 # Per bank write bursts -system.physmem.perBankWrBursts::13 6319 # Per bank write bursts -system.physmem.perBankWrBursts::14 5995 # Per bank write bursts -system.physmem.perBankWrBursts::15 6090 # Per bank write bursts +system.physmem.perBankRdBursts::0 9376 # Per bank write bursts +system.physmem.perBankRdBursts::1 8929 # Per bank write bursts +system.physmem.perBankRdBursts::2 8964 # Per bank write bursts +system.physmem.perBankRdBursts::3 8666 # Per bank write bursts +system.physmem.perBankRdBursts::4 9423 # Per bank write bursts +system.physmem.perBankRdBursts::5 9371 # Per bank write bursts +system.physmem.perBankRdBursts::6 8974 # Per bank write bursts +system.physmem.perBankRdBursts::7 8126 # Per bank write bursts +system.physmem.perBankRdBursts::8 8634 # Per bank write bursts +system.physmem.perBankRdBursts::9 8697 # Per bank write bursts +system.physmem.perBankRdBursts::10 8760 # Per bank write bursts +system.physmem.perBankRdBursts::11 9487 # Per bank write bursts +system.physmem.perBankRdBursts::12 9347 # Per bank write bursts +system.physmem.perBankRdBursts::13 9550 # Per bank write bursts +system.physmem.perBankRdBursts::14 8728 # Per bank write bursts +system.physmem.perBankRdBursts::15 9135 # Per bank write bursts +system.physmem.perBankWrBursts::0 6252 # Per bank write bursts +system.physmem.perBankWrBursts::1 6118 # Per bank write bursts +system.physmem.perBankWrBursts::2 6042 # Per bank write bursts +system.physmem.perBankWrBursts::3 5901 # Per bank write bursts +system.physmem.perBankWrBursts::4 6273 # Per bank write bursts +system.physmem.perBankWrBursts::5 6263 # Per bank write bursts +system.physmem.perBankWrBursts::6 6069 # Per bank write bursts +system.physmem.perBankWrBursts::7 5534 # Per bank write bursts +system.physmem.perBankWrBursts::8 5815 # Per bank write bursts +system.physmem.perBankWrBursts::9 5920 # Per bank write bursts +system.physmem.perBankWrBursts::10 5985 # Per bank write bursts +system.physmem.perBankWrBursts::11 6510 # Per bank write bursts +system.physmem.perBankWrBursts::12 6360 # Per bank write bursts +system.physmem.perBankWrBursts::13 6344 # Per bank write bursts +system.physmem.perBankWrBursts::14 6013 # Per bank write bursts +system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366439104000 # Total gap between requests +system.physmem.totGap 366631694000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143881 # Read request sizes (log2) +system.physmem.readPktSize::6 144269 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97182 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97528 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,118 +194,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.015914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.088937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.071665 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24900 37.96% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18453 28.13% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7121 10.85% 76.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7867 11.99% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1977 3.01% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1093 1.67% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 809 1.23% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 630 0.96% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2754 4.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65604 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.620745 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 380.610137 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.314204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.219748 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.335766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2654 47.30% 47.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2805 49.99% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 62 1.10% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 17 0.30% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 10 0.18% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 10 0.18% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads -system.physmem.totQLat 1554447250 # Total ticks spent queuing -system.physmem.totMemAccLat 4250153500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 718855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10811.97 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads +system.physmem.totQLat 1581653750 # Total ticks spent queuing +system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29561.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.60 # Average write queue length when enqueuing -system.physmem.readRowHits 110522 # Number of row buffer hits during reads -system.physmem.writeRowHits 64789 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 1520096.84 # Average gap between requests -system.physmem.pageHitRate 72.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249842880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136323000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 559080600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 312783120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47987220420 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177768013500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250947114240 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.830589 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295423376000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12236120000 # Time in different power states +system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing +system.physmem.readRowHits 110439 # Number of row buffer hits during reads +system.physmem.writeRowHits 67921 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes +system.physmem.avgGap 1516278.92 # Average gap between requests +system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.547573 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58777294250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246017520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134235750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562114800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 316645200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47395195335 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178287321750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250875381075 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.634868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296291389000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12236120000 # Time in different power states +system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.512070 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states +system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57909758500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132103761 # Number of BP lookups -system.cpu.branchPred.condPredicted 98193255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5910050 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68601566 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60590451 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 132103795 # Number of BP lookups +system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.322256 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891572 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8545 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -335,7 +323,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -365,7 +353,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,7 +383,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -426,16 +414,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732878259 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 733263439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12939743 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446720 # CPI: cycles per instruction -system.cpu.ipc 0.691219 # IPC: instructions per cycle +system.cpu.cpi 1.447480 # CPI: cycles per instruction +system.cpu.ipc 0.690856 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction @@ -471,29 +459,29 @@ system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694071941 # Number of cycles that the object actually ticked -system.cpu.idleCycles 38806318 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked +system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.313641 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083825 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.361704 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5033914500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.313641 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993729 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993729 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338115 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338115 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566020 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566020 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits @@ -502,10 +490,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103949 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103949 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106743 # number of overall hits -system.cpu.dcache.overall_hits::total 168106743 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits +system.cpu.dcache.overall_hits::total 168106740 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses @@ -516,16 +504,16 @@ system.cpu.dcache.demand_misses::cpu.data 1512501 # n system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses system.cpu.dcache.overall_misses::total 1512516 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13462011000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13462011000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21943272000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21943272000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35405283000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35405283000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35405283000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35405283000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) @@ -534,10 +522,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616450 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616450 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619259 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619259 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses @@ -548,22 +536,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16591.479219 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16591.479219 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31297.455500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31297.455500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23408.436094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23408.436094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23408.203946 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23408.203946 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1069267 # number of writebacks -system.cpu.dcache.writebacks::total 1069267 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks +system.cpu.dcache.writebacks::total 1068942 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits @@ -582,16 +570,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12369658000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12369658000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11145800500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11145800500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1093500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1093500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23515458500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23515458500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23516552000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23516552000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses @@ -602,26 +590,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15676.984359 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15676.984359 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31274.342851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31274.342851 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 91125 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 91125 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.969767 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.969767 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20530.709347 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20530.709347 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18175 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.153068 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199148908 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9934.100264 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1187.153068 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id @@ -629,45 +617,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 57 system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398357957 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398357957 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199148908 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199148908 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199148908 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199148908 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199148908 # number of overall hits -system.cpu.icache.overall_hits::total 199148908 # number of overall hits +system.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398358065 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199148962 # 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miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.387440 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22739.387440 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22739.387440 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22739.387440 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,89 +670,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 20047 system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435809500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 435809500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435809500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 435809500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435809500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 435809500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.387440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.387440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 112318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27616.037174 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1771878 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 143528 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.345173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 165163715500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23489.264935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.326790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.445449 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.716835 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009409 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.116530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.842775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19060134 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19060134 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1069267 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1069267 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 112761 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18705497 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18705497 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255711 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255711 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17236 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17236 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748638 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 748638 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17236 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1004349 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1021585 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17236 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1004349 # number of overall hits -system.cpu.l2cache.overall_hits::total 1021585 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100927 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100927 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40157 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 236084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3363607000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3363607000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 236084500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11421132500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11657217000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 236084500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11421132500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11657217000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) @@ -779,107 +767,107 @@ system.cpu.l2cache.demand_accesses::total 1165480 # n system.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050909 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050909 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140220 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123171 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123464 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140220 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123171 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123464 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78559.032766 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78559.032766 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79720.028460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79720.028460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82343.651169 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82343.651169 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79637.892213 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79637.892213 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140270 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140270 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140270 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123798 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140270 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123798 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80793.552993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80793.552993 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 97182 # number of writebacks -system.cpu.l2cache.writebacks::total 97182 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks +system.cpu.l2cache.writebacks::total 97528 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100927 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100927 # number of ReadExReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40144 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40144 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 143881 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 143881 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6919457500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6919457500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195753000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195753000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2904162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2904162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195753000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9823619500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10019372500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195753000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9823619500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10019372500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282996 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282996 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7047745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7047745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207624000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207624000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2957433000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2957433000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207624000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10005178500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10212802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207624000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10005178500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10212802500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050893 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050893 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123452 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123452 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68559.032766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68559.032766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69662.989324 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69662.989324 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72343.612993 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72343.612993 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2610 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution @@ -888,53 +876,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141740800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144187008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112318 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6219648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1277798 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006010 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077318 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112761 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270122 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7673 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1277798 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249938000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30093953 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718157484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 42954 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97182 # Transaction distribution -system.membus.trans_dist::CleanEvict 12526 # Transaction distribution -system.membus.trans_dist::ReadExReq 100927 # Transaction distribution -system.membus.trans_dist::ReadExResp 100927 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42954 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15428032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15428032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 43291 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution +system.membus.trans_dist::CleanEvict 12615 # Transaction distribution +system.membus.trans_dist::ReadExReq 100978 # Transaction distribution +system.membus.trans_dist::ReadExResp 100978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 253589 # Request fanout histogram +system.membus.snoop_fanout::samples 144269 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253589 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253589 # Request fanout histogram -system.membus.reqLayer0.occupancy 685523500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 144269 # Request fanout histogram +system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 763755750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d31d95a5e..f10b69af3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232865 # Number of seconds simulated -sim_ticks 232864525000 # Number of ticks simulated -final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233363 # Number of seconds simulated +sim_ticks 233363457000 # Number of ticks simulated +final_tick 233363457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 208842 # Simulator instruction rate (inst/s) -host_op_rate 226249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96255881 # Simulator tick rate (ticks/s) -host_mem_usage 295820 # Number of bytes of host memory used -host_seconds 2419.22 # Real time elapsed on the host +host_inst_rate 153279 # Simulator instruction rate (inst/s) +host_op_rate 166055 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70798116 # Simulator tick rate (ticks/s) +host_mem_usage 302508 # Number of bytes of host memory used +host_seconds 3296.18 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory -system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory -system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257200 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423921 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292354 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292354 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2249548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43571703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70688311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116509563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2249548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2249548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80349963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80349963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80349963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2249548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43571703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70688311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 196859526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423921 # Number of read requests accepted -system.physmem.writeReqs 292354 # Number of write requests accepted -system.physmem.readBursts 423921 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292354 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26979136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 151808 # Total number of bytes read from write queue -system.physmem.bytesWritten 18708352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27130944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18710656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2372 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 641792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10513600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16409344 # Number of bytes read from this memory +system.physmem.bytes_read::total 27564736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 641792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 641792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18651328 # Number of bytes written to this memory +system.physmem.bytes_written::total 18651328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256396 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430699 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291427 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291427 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2750182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45052469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70316682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118119333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2750182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2750182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79923945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79923945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79923945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2750182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45052469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70316682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 198043278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430699 # Number of read requests accepted +system.physmem.writeReqs 291427 # Number of write requests accepted +system.physmem.readBursts 430699 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291427 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27407296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 157440 # Total number of bytes read from write queue +system.physmem.bytesWritten 18649728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27564736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18651328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2460 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26585 # Per bank write bursts -system.physmem.perBankRdBursts::1 25966 # Per bank write bursts -system.physmem.perBankRdBursts::2 25309 # Per bank write bursts -system.physmem.perBankRdBursts::3 32108 # Per bank write bursts -system.physmem.perBankRdBursts::4 27451 # Per bank write bursts -system.physmem.perBankRdBursts::5 28247 # Per bank write bursts -system.physmem.perBankRdBursts::6 25115 # Per bank write bursts -system.physmem.perBankRdBursts::7 24228 # Per bank write bursts -system.physmem.perBankRdBursts::8 25496 # Per bank write bursts -system.physmem.perBankRdBursts::9 25694 # Per bank write bursts -system.physmem.perBankRdBursts::10 25307 # Per bank write bursts -system.physmem.perBankRdBursts::11 26044 # Per bank write bursts -system.physmem.perBankRdBursts::12 27396 # Per bank write bursts -system.physmem.perBankRdBursts::13 26024 # Per bank write bursts -system.physmem.perBankRdBursts::14 24983 # Per bank write bursts -system.physmem.perBankRdBursts::15 25596 # Per bank write bursts -system.physmem.perBankWrBursts::0 18605 # Per bank write bursts -system.physmem.perBankWrBursts::1 18353 # Per bank write bursts -system.physmem.perBankWrBursts::2 18036 # Per bank write bursts -system.physmem.perBankWrBursts::3 17927 # Per bank write bursts -system.physmem.perBankWrBursts::4 18566 # Per bank write bursts -system.physmem.perBankWrBursts::5 18339 # Per bank write bursts -system.physmem.perBankWrBursts::6 17904 # Per bank write bursts -system.physmem.perBankWrBursts::7 17705 # Per bank write bursts -system.physmem.perBankWrBursts::8 17878 # Per bank write bursts -system.physmem.perBankWrBursts::9 17947 # Per bank write bursts -system.physmem.perBankWrBursts::10 18182 # Per bank write bursts -system.physmem.perBankWrBursts::11 18731 # Per bank write bursts -system.physmem.perBankWrBursts::12 18803 # Per bank write bursts -system.physmem.perBankWrBursts::13 18363 # Per bank write bursts -system.physmem.perBankWrBursts::14 18474 # Per bank write bursts -system.physmem.perBankWrBursts::15 18505 # Per bank write bursts +system.physmem.perBankRdBursts::0 27205 # Per bank write bursts +system.physmem.perBankRdBursts::1 26463 # Per bank write bursts +system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::3 32969 # Per bank write bursts +system.physmem.perBankRdBursts::4 28037 # Per bank write bursts +system.physmem.perBankRdBursts::5 29890 # Per bank write bursts +system.physmem.perBankRdBursts::6 25340 # Per bank write bursts +system.physmem.perBankRdBursts::7 24398 # Per bank write bursts +system.physmem.perBankRdBursts::8 25649 # Per bank write bursts +system.physmem.perBankRdBursts::9 25581 # Per bank write bursts +system.physmem.perBankRdBursts::10 25884 # Per bank write bursts +system.physmem.perBankRdBursts::11 26303 # Per bank write bursts +system.physmem.perBankRdBursts::12 27555 # Per bank write bursts +system.physmem.perBankRdBursts::13 26148 # Per bank write bursts +system.physmem.perBankRdBursts::14 24908 # Per bank write bursts +system.physmem.perBankRdBursts::15 26307 # Per bank write bursts +system.physmem.perBankWrBursts::0 18644 # Per bank write bursts +system.physmem.perBankWrBursts::1 18139 # Per bank write bursts +system.physmem.perBankWrBursts::2 17950 # Per bank write bursts +system.physmem.perBankWrBursts::3 17944 # Per bank write bursts +system.physmem.perBankWrBursts::4 18581 # Per bank write bursts +system.physmem.perBankWrBursts::5 18235 # Per bank write bursts +system.physmem.perBankWrBursts::6 17841 # Per bank write bursts +system.physmem.perBankWrBursts::7 17708 # Per bank write bursts +system.physmem.perBankWrBursts::8 18005 # Per bank write bursts +system.physmem.perBankWrBursts::9 17734 # Per bank write bursts +system.physmem.perBankWrBursts::10 18244 # Per bank write bursts +system.physmem.perBankWrBursts::11 18783 # Per bank write bursts +system.physmem.perBankWrBursts::12 18680 # Per bank write bursts +system.physmem.perBankWrBursts::13 18156 # Per bank write bursts +system.physmem.perBankWrBursts::14 18369 # Per bank write bursts +system.physmem.perBankWrBursts::15 18389 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 232864472500 # Total gap between requests +system.physmem.totGap 233363404500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423921 # Read request sizes (log2) +system.physmem.readPktSize::6 430699 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292354 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 324214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3284 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291427 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 330391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3274 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,41 +149,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -198,118 +198,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 322606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.616907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.575706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 179.865264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 203481 63.07% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79249 24.57% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15283 4.74% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7278 2.26% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4895 1.52% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2519 0.78% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1928 0.60% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1485 0.46% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6488 2.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 322606 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17068 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.693051 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.945620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17066 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 328347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 140.266048 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.833830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.808988 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 208753 63.58% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 80037 24.38% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14980 4.56% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7256 2.21% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4857 1.48% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2521 0.77% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1858 0.57% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1524 0.46% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6561 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 328347 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.230642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.328941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 16968 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17068 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.126670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.068877 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.479655 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9203 53.92% 53.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 342 2.00% 55.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5412 31.71% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1340 7.85% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 381 2.23% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 185 1.08% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 84 0.49% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 48 0.28% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 28 0.16% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 13 0.08% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17068 # Writes before turning the bus around for reads -system.physmem.totQLat 8669198966 # Total ticks spent queuing -system.physmem.totMemAccLat 16573242716 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2107745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20565.10 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 16970 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.171597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.099419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.840930 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 9436 55.60% 55.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6694 39.45% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 588 3.46% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 150 0.88% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 55 0.32% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 20 0.12% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 4 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 8 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::94-95 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16970 # Writes before turning the bus around for reads +system.physmem.totQLat 8687632010 # Total ticks spent queuing +system.physmem.totMemAccLat 16717113260 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2141195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20286.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39315.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39036.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.54 # Data bus utilization in percentage +system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.66 # Average write queue length when enqueuing -system.physmem.readRowHits 306141 # Number of row buffer hits during reads -system.physmem.writeRowHits 85116 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.11 # Row buffer hit rate for writes -system.physmem.avgGap 325104.84 # Average gap between requests -system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1231478640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 671937750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1677023400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942418800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82038252060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 67754804250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 169525418820 # Total energy per rank (pJ) -system.physmem_0.averagePower 728.002962 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 112181922825 # Time in different power states -system.physmem_0.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem.avgWrQLen 21.52 # Average write queue length when enqueuing +system.physmem.readRowHits 308039 # Number of row buffer hits during reads +system.physmem.writeRowHits 83248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.57 # Row buffer hit rate for writes +system.physmem.avgGap 323161.62 # Average gap between requests +system.physmem.pageHitRate 54.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1261242360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 688177875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1715142000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 939872160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86511761685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64129665000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170487912840 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.572857 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 106127593352 # Time in different power states +system.physmem_0.memoryStateTime::REF 7792460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112906030175 # Time in different power states +system.physmem_0.memoryStateTime::ACT 119441919148 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1207422720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 658812000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1610934000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 951801840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78953270130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) -system.physmem_1.averagePower 725.972811 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states -system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem_1.actEnergy 1221045840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 666245250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1624857000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 948412800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81485025165 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 68539083000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169726720815 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.311005 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 113492657633 # Time in different power states +system.physmem_1.memoryStateTime::REF 7792460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states +system.physmem_1.memoryStateTime::ACT 112077139867 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174583649 # Number of BP lookups -system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174594135 # Number of BP lookups +system.cpu.branchPred.condPredicted 131061438 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7233022 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90315091 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79002409 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.474206 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12105110 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104499 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4687937 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4674274 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13663 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53871 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +338,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +368,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +398,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,233 +429,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 465729051 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 466726915 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14522705 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 141 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13015 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235271545 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36405 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465093244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.693494 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.182412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7649319 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727510991 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174594135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95781793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 451018276 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14520177 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5415 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13360 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235275678 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36827 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465946604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.690437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.183518 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95400849 20.51% 20.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132044062 28.39% 48.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57356261 12.33% 61.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180292072 38.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96241342 20.66% 20.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132050994 28.34% 49.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57360477 12.31% 61.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180293791 38.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465093244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.562051 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32522816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 120066297 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282921194 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22809829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6773108 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23856996 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495879 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710982293 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29095211 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6773108 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63338503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55962062 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40377047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273519607 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25122917 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682713266 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12851705 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9930975 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2510705 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1794472 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1920747 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827509638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000483792 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718633951 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 465946604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374082 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.558751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32536552 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 120918293 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282902203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22817634 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6771922 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23855471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495849 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710960604 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29091371 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6771922 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63349282 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56784032 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40401553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273510163 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25129652 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682692967 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12844145 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9945202 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2511648 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1805093 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1905777 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827472920 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000392013 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718609980 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173413964 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545834 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536299 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43818789 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142365669 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67523427 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12892964 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11349045 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664768510 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608926727 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749477 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120399705 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306541324 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1718 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465093244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.309257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173377246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545812 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536134 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43839802 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142358029 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67522859 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12902461 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11335768 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664750936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979334 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608926553 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5748894 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120382115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306467952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1702 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465946604 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.306859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102130 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148683316 31.97% 31.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100887288 21.69% 53.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145497620 31.28% 84.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63056493 13.56% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6967915 1.50% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 612 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 149520607 32.09% 32.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100880237 21.65% 53.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145552540 31.24% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63032249 13.53% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6960366 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 605 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465093244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465946604 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71909518 53.13% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44304480 32.74% 85.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19119642 14.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71896734 53.12% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44291867 32.73% 85.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19147796 14.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412592470 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352106 0.06% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133579374 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62402774 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412590919 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352109 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133574983 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62408539 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608926727 # Type of FU issued -system.cpu.iq.rate 1.307470 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135333670 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222250 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1824029756 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788176792 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594203276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 89 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608926553 # Type of FU issued +system.cpu.iq.rate 1.304674 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135336427 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222254 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1824884935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788141663 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594200588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 96 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744260342 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7285470 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744262920 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7284479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26482386 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24610 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29757 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10663207 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26474746 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24624 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29798 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10662639 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225824 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225013 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22508 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6773108 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22711376 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 916891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669240779 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6771922 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22843049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 918168 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669223084 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142365669 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67523427 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490808 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256518 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 523375 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29757 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591194 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3743418 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7334612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598426944 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129087025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10499783 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142358029 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67522859 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490792 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256633 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 523882 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29798 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3590923 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742651 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7333574 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598420503 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129081054 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10506050 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492919 # number of nop insts executed -system.cpu.iew.exec_refs 190006687 # number of memory reference insts executed -system.cpu.iew.exec_branches 131263664 # Number of branches executed -system.cpu.iew.exec_stores 60919662 # Number of stores executed -system.cpu.iew.exec_rate 1.284925 # Inst execution rate -system.cpu.iew.wb_sent 595449226 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594203292 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349565798 # num instructions producing a value -system.cpu.iew.wb_consumers 571378084 # num instructions consuming a value -system.cpu.iew.wb_rate 1.275856 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611794 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107129246 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492814 # number of nop insts executed +system.cpu.iew.exec_refs 190002009 # number of memory reference insts executed +system.cpu.iew.exec_branches 131263961 # Number of branches executed +system.cpu.iew.exec_stores 60920955 # Number of stores executed +system.cpu.iew.exec_rate 1.282164 # Inst execution rate +system.cpu.iew.wb_sent 595445456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594200604 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349565575 # num instructions producing a value +system.cpu.iew.wb_consumers 571385188 # num instructions consuming a value +system.cpu.iew.wb_rate 1.273123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611786 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107116116 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6746083 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448430808 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.223582 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.891618 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6744856 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 449285999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.221253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.890713 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219662042 48.98% 48.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116371870 25.95% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43476650 9.70% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23164070 5.17% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11528126 2.57% 92.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7755918 1.73% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8275201 1.85% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4244089 0.95% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13952842 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 220514428 49.08% 49.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116376748 25.90% 74.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43480691 9.68% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23177999 5.16% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11514242 2.56% 92.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755129 1.73% 94.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8259802 1.84% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4227193 0.94% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13979767 3.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448430808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 449285999 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -702,555 +701,560 @@ system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13952842 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1090292113 # The number of ROB reads -system.cpu.rob.rob_writes 1328334369 # The number of ROB writes -system.cpu.timesIdled 12786 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 635807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13979767 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1091107249 # The number of ROB reads +system.cpu.rob.rob_writes 1328306301 # The number of ROB writes +system.cpu.timesIdled 14326 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 780311 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.921807 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.921807 # CPI: Total CPI of All Threads -system.cpu.ipc 1.084826 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610135542 # number of integer regfile reads -system.cpu.int_regfile_writes 327337405 # number of integer regfile writes +system.cpu.cpi 0.923782 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923782 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082507 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082507 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610129735 # number of integer regfile reads +system.cpu.int_regfile_writes 327331512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads -system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes -system.cpu.misc_regfile_reads 217603179 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166233884 # number of cc regfile reads +system.cpu.cc_regfile_writes 376536291 # number of cc regfile writes +system.cpu.misc_regfile_reads 217601523 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817145 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817306 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.628303 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168866082 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817818 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.927959 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 501259000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.628303 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 355259202 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355259202 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114162091 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114162091 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51724043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51724043 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2789 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2789 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165890841 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165890841 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165893629 # number of overall hits -system.cpu.dcache.overall_hits::total 165893629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4837166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4837166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516778 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516778 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 165886134 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165886134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165888923 # number of overall hits +system.cpu.dcache.overall_hits::total 165888923 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4839586 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4839586 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2515006 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2515006 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7353944 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7353944 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7353956 # number of overall misses -system.cpu.dcache.overall_misses::total 7353956 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57478265500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57478265500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18947607428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18947607428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1052500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1052500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76425872928 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76425872928 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76425872928 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76425872928 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119005736 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119005736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7354592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7354592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7354602 # number of overall misses +system.cpu.dcache.overall_misses::total 7354602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58596122500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58596122500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18922626430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18922626430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 77518748930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 77518748930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 77518748930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 77518748930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119001677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119001677 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2800 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2800 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173244785 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173244785 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173247585 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173247585 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040646 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040646 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046402 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046402 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004286 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004286 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173240726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173240726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173243525 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173243525 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040668 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040668 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046369 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046369 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003573 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003573 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042448 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042448 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042448 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042448 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7528.517584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7528.517584 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10392.501347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks -system.cpu.dcache.writebacks::total 2817145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.042453 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042453 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7523.889180 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7523.889180 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10540.183457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10540.169125 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 907373 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221320 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.099824 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817306 # number of writebacks +system.cpu.dcache.writebacks::total 2817306 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2541564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995189 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4536267 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4536267 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4536267 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4536267 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519820 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519820 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29541351500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29541351500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603156994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603156994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 669500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 669500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34144508494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34144508494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34145177994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34145177994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 4536753 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4536753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4536753 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4536753 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298022 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2298022 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519817 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519817 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2817839 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2817839 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2817848 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2817848 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30115234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30115234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603448995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603448995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 602500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 602500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34718683495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34718683495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34719285995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34719285995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003571 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76528 # number of replacements -system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003215 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003215 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13104.850389 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13104.850389 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.903126 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.903126 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12321.031647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12321.031647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12321.206110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12321.206110 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 76636 # number of replacements +system.cpu.icache.tags.tagsinuse 466.486924 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235189788 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77148 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3048.553274 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115712400500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.486924 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.911107 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.911107 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits -system.cpu.icache.overall_hits::total 235186472 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 84972 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 84972 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 84972 # number of overall misses -system.cpu.icache.overall_misses::total 84972 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1359599197 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1359599197 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1359599197 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1359599197 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1359599197 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1359599197 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235271444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235271444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235271444 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235271444 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235271444 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235271444 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000361 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000361 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000361 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000361 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000361 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000361 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16000.555442 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16000.555442 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 161540 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 362 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6762 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76528 # number of writebacks -system.cpu.icache.writebacks::total 76528 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7901 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7901 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7901 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7901 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7901 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77071 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77071 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77071 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77071 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77071 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1127867788 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1127867788 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1127867788 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1127867788 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1127867788 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1127867788 # number of overall MSHR miss cycles +system.cpu.icache.tags.tag_accesses 470628332 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470628332 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235189788 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235189788 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235189788 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235189788 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235189788 # number of overall hits +system.cpu.icache.overall_hits::total 235189788 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 85789 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 85789 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 85789 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 85789 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 85789 # number of overall misses +system.cpu.icache.overall_misses::total 85789 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1556704687 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1556704687 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1556704687 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1556704687 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1556704687 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1556704687 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235275577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235275577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235275577 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235275577 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235275577 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235275577 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18145.737647 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18145.737647 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18145.737647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18145.737647 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 171831 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 200 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6857 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.059210 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76636 # number of writebacks +system.cpu.icache.writebacks::total 76636 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8610 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8610 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8610 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8610 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8610 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8610 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77179 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77179 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77179 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77179 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77179 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77179 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1268632793 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1268632793 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1268632793 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1268632793 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1268632793 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1268632793 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16437.538618 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16437.538618 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513734 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8515093 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 374 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 395630 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 411561 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.738683 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 169696310500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1349.056936 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.840961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082340 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.923301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 34 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 239 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 519224 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516915 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 68843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 68843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2136682 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2136682 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 68843 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2653597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2722440 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 68843 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2653597 # number of overall hits -system.cpu.l2cache.overall_hits::total 2722440 # number of overall hits +system.cpu.l2cache.prefetcher.pfSpanPage 743899 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 390403 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15000.108571 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2699085 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 406018 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.647698 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14926.062493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.046079 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.911015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004519 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.915534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 114 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15501 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30384071193 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3662 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3662 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10028 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10028 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160616 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160616 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10028 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 164278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174306 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10028 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 164278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356222 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 530528 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18747915458 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 462000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 462000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 336888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 336888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 689794500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 689794500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11439165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11439165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689794500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11776053000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12465847500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689794500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11776053000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31213762958 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007088 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007088 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.106248 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057596 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069961 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069961 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060210 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.178797 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183259 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15400 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15400 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788969 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893984 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23717 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99826 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99825 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2372984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2645368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 540001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 397627 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295646 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9828032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360627392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370455424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 950855 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18712896 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3845578 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078356 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.284056 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 522012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295806 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9841856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360648000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370489856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 788066 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18653632 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3683057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.033555 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.180083 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3560544 92.59% 92.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268745 6.99% 99.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 16289 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3559472 96.64% 96.64% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 123584 3.36% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3845578 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3683057 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788426505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115796940 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226763956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 420223 # Transaction distribution -system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution -system.membus.trans_dist::CleanEvict 98859 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33 # Transaction distribution -system.membus.trans_dist::ReadExReq 3697 # Transaction distribution -system.membus.trans_dist::ReadExResp 3697 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1239087 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45841536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45841536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 821136 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 414105 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 427040 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291427 # Transaction distribution +system.membus.trans_dist::CleanEvict 98976 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34 # Transaction distribution +system.membus.trans_dist::ReadExReq 3658 # Transaction distribution +system.membus.trans_dist::ReadExResp 3658 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 427041 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1251834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46216000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46216000 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 815167 # Request fanout histogram +system.membus.snoop_fanout::samples 430733 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 815167 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430733 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 815167 # Request fanout histogram -system.membus.reqLayer0.occupancy 2211611288 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2242842427 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430733 # Request fanout histogram +system.membus.reqLayer0.occupancy 2217216132 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2280002282 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index e8a891fe8..6a67fce1b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1100009 # Simulator instruction rate (inst/s) -host_op_rate 1191455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 606617028 # Simulator tick rate (ticks/s) -host_mem_usage 259840 # Number of bytes of host memory used -host_seconds 460.52 # Real time elapsed on the host +host_inst_rate 1206466 # Simulator instruction rate (inst/s) +host_op_rate 1306763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 665324846 # Simulator tick rate (ticks/s) +host_mem_usage 263448 # Number of bytes of host memory used +host_seconds 419.89 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 630707528 # Transaction distribution system.membus.trans_dist::ReadResp 632196069 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 2705349287 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 687926230 # Request fanout histogram -system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 687926230 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index a77764c75..9780dac13 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708539 # Number of seconds simulated -sim_ticks 708539449500 # Number of ticks simulated -final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.708700 # Number of seconds simulated +sim_ticks 708700329500 # Number of ticks simulated +final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 665557 # Simulator instruction rate (inst/s) -host_op_rate 720769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 933837970 # Simulator tick rate (ticks/s) -host_mem_usage 269828 # Number of bytes of host memory used -host_seconds 758.74 # Real time elapsed on the host +host_inst_rate 820539 # Simulator instruction rate (inst/s) +host_op_rate 888607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1151553403 # Simulator tick rate (ticks/s) +host_mem_usage 275232 # Number of bytes of host memory used +host_seconds 615.43 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory -system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory +system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory -system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory +system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1417078899 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1417400659 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504984064 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 172743505 # nu system.cpu.num_load_insts 115883283 # Number of load instructions system.cpu.num_store_insts 56860222 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121552863 # Number of branches fetched @@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1136276 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 1140371 # n system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses system.cpu.dcache.overall_misses::total 1140372 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) @@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks -system.cpu.dcache.writebacks::total 1065708 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks +system.cpu.dcache.writebacks::total 1065429 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses @@ -323,16 +323,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses @@ -343,26 +343,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -372,7 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits @@ -385,12 +385,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses @@ -403,12 +403,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,89 +423,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 110394 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 110813 # number of replacements +system.cpu.l2cache.tags.tagsinuse 28700.010798 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2150809 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 143581 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.979761 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 210357436000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.875855 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18498717 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18498717 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 744258 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 999933 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1009151 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits -system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses +system.cpu.l2cache.overall_hits::cpu.data 999933 # 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number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140439 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 142742 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses -system.cpu.l2cache.overall_misses::total 142364 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 140439 # number of overall misses +system.cpu.l2cache.overall_misses::total 142742 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8642481500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8642481500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1065429 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) @@ -520,101 +520,101 @@ system.cpu.l2cache.demand_accesses::total 1151893 # n system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123919 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123919 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks -system.cpu.l2cache.writebacks::total 96330 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96648 # number of writebacks +system.cpu.l2cache.writebacks::total 96648 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 142742 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution @@ -623,53 +623,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 110394 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6165120 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 110813 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 41576 # Transaction distribution -system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution -system.membus.trans_dist::CleanEvict 11920 # Transaction distribution -system.membus.trans_dist::ReadExReq 100788 # Transaction distribution -system.membus.trans_dist::ReadExResp 100788 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 108784 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 41909 # Transaction distribution +system.membus.trans_dist::WritebackDirty 96648 # Transaction distribution +system.membus.trans_dist::CleanEvict 12014 # Transaction distribution +system.membus.trans_dist::ReadExReq 100833 # Transaction distribution +system.membus.trans_dist::ReadExResp 100833 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 250615 # Request fanout histogram +system.membus.snoop_fanout::samples 142743 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 142743 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 250615 # Request fanout histogram -system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 142743 # Request fanout histogram +system.membus.reqLayer0.occupancy 644372828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 713710000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 4e13e1bff..bc9a5d8a0 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.481958 # Number of seconds simulated -sim_ticks 481957625500 # Number of ticks simulated -final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.482382 # Number of seconds simulated +sim_ticks 482382057000 # Number of ticks simulated +final_tick 482382057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109870 # Simulator instruction rate (inst/s) -host_op_rate 203315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64041688 # Simulator tick rate (ticks/s) -host_mem_usage 315224 # Number of bytes of host memory used -host_seconds 7525.69 # Real time elapsed on the host +host_inst_rate 90853 # Simulator instruction rate (inst/s) +host_op_rate 168124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53003549 # Simulator tick rate (ticks/s) +host_mem_usage 321140 # Number of bytes of host memory used +host_seconds 9100.94 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory -system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory -system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386855 # Number of read requests accepted -system.physmem.writeReqs 294920 # Number of write requests accepted -system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue -system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24650752 # Number of bytes read from this memory +system.physmem.bytes_read::total 24805888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory +system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 321604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 51102133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51423737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 321604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 321604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 39204244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39204244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 39204244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 321604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51102133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 90627981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387592 # Number of read requests accepted +system.physmem.writeReqs 295491 # Number of write requests accepted +system.physmem.readBursts 387592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24786816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue +system.physmem.bytesWritten 18910464 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24805888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24516 # Per bank write bursts -system.physmem.perBankRdBursts::1 26460 # Per bank write bursts -system.physmem.perBankRdBursts::2 24685 # Per bank write bursts -system.physmem.perBankRdBursts::3 24442 # Per bank write bursts -system.physmem.perBankRdBursts::4 23203 # Per bank write bursts -system.physmem.perBankRdBursts::5 23588 # Per bank write bursts -system.physmem.perBankRdBursts::6 24636 # Per bank write bursts -system.physmem.perBankRdBursts::7 24397 # Per bank write bursts -system.physmem.perBankRdBursts::8 23786 # Per bank write bursts -system.physmem.perBankRdBursts::9 23509 # Per bank write bursts -system.physmem.perBankRdBursts::10 24817 # Per bank write bursts -system.physmem.perBankRdBursts::11 23975 # Per bank write bursts -system.physmem.perBankRdBursts::12 23290 # Per bank write bursts -system.physmem.perBankRdBursts::13 22963 # Per bank write bursts -system.physmem.perBankRdBursts::14 23965 # Per bank write bursts -system.physmem.perBankRdBursts::15 24296 # Per bank write bursts -system.physmem.perBankWrBursts::0 18881 # Per bank write bursts -system.physmem.perBankWrBursts::1 19925 # Per bank write bursts -system.physmem.perBankWrBursts::2 19022 # Per bank write bursts -system.physmem.perBankWrBursts::3 18969 # Per bank write bursts -system.physmem.perBankWrBursts::4 18086 # Per bank write bursts -system.physmem.perBankWrBursts::5 18421 # Per bank write bursts -system.physmem.perBankWrBursts::6 19142 # Per bank write bursts -system.physmem.perBankWrBursts::7 19085 # Per bank write bursts -system.physmem.perBankWrBursts::8 18675 # Per bank write bursts -system.physmem.perBankWrBursts::9 17903 # Per bank write bursts -system.physmem.perBankWrBursts::10 18899 # Per bank write bursts -system.physmem.perBankWrBursts::11 17761 # Per bank write bursts -system.physmem.perBankWrBursts::12 17398 # Per bank write bursts -system.physmem.perBankWrBursts::13 16983 # Per bank write bursts -system.physmem.perBankWrBursts::14 17797 # Per bank write bursts -system.physmem.perBankWrBursts::15 17948 # Per bank write bursts +system.physmem.perBankRdBursts::0 24694 # Per bank write bursts +system.physmem.perBankRdBursts::1 26457 # Per bank write bursts +system.physmem.perBankRdBursts::2 24696 # Per bank write bursts +system.physmem.perBankRdBursts::3 24495 # Per bank write bursts +system.physmem.perBankRdBursts::4 23285 # Per bank write bursts +system.physmem.perBankRdBursts::5 23614 # Per bank write bursts +system.physmem.perBankRdBursts::6 24693 # Per bank write bursts +system.physmem.perBankRdBursts::7 24448 # Per bank write bursts +system.physmem.perBankRdBursts::8 23844 # Per bank write bursts +system.physmem.perBankRdBursts::9 23582 # Per bank write bursts +system.physmem.perBankRdBursts::10 24812 # Per bank write bursts +system.physmem.perBankRdBursts::11 24004 # Per bank write bursts +system.physmem.perBankRdBursts::12 23312 # Per bank write bursts +system.physmem.perBankRdBursts::13 22998 # Per bank write bursts +system.physmem.perBankRdBursts::14 24024 # Per bank write bursts +system.physmem.perBankRdBursts::15 24336 # Per bank write bursts +system.physmem.perBankWrBursts::0 19003 # Per bank write bursts +system.physmem.perBankWrBursts::1 19960 # Per bank write bursts +system.physmem.perBankWrBursts::2 19024 # Per bank write bursts +system.physmem.perBankWrBursts::3 18975 # Per bank write bursts +system.physmem.perBankWrBursts::4 18152 # Per bank write bursts +system.physmem.perBankWrBursts::5 18441 # Per bank write bursts +system.physmem.perBankWrBursts::6 19161 # Per bank write bursts +system.physmem.perBankWrBursts::7 19119 # Per bank write bursts +system.physmem.perBankWrBursts::8 18726 # Per bank write bursts +system.physmem.perBankWrBursts::9 17970 # Per bank write bursts +system.physmem.perBankWrBursts::10 18928 # Per bank write bursts +system.physmem.perBankWrBursts::11 17785 # Per bank write bursts +system.physmem.perBankWrBursts::12 17418 # Per bank write bursts +system.physmem.perBankWrBursts::13 16994 # Per bank write bursts +system.physmem.perBankWrBursts::14 17838 # Per bank write bursts +system.physmem.perBankWrBursts::15 17982 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 481957508500 # Total gap between requests +system.physmem.totGap 482381969500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386855 # Read request sizes (log2) +system.physmem.readPktSize::6 387592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294920 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5169 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5176 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,33 +145,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,247 +194,242 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.722669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.940489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.258352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52888 36.16% 36.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40462 27.66% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14063 9.61% 73.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7664 5.24% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5102 3.49% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3857 2.64% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2918 1.99% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2773 1.90% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16553 11.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17634 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.962913 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.199318 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.461189 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17628 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads -system.physmem.totQLat 4249579000 # Total ticks spent queuing -system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17634 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.755969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.728033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.977832 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10918 61.92% 61.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 278 1.58% 63.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6268 35.55% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 161 0.91% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17633 # Writes before turning the bus around for reads +system.physmem.totQLat 4311135000 # Total ticks spent queuing +system.physmem.totMemAccLat 11572897500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1936470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11131.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29881.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 51.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 39.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 39.20 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.71 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing -system.physmem.readRowHits 315674 # Number of row buffer hits during reads -system.physmem.writeRowHits 215465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes -system.physmem.avgGap 706915.78 # Average gap between requests -system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.294629 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states -system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.28 # Average write queue length when enqueuing +system.physmem.readRowHits 315765 # Number of row buffer hits during reads +system.physmem.writeRowHits 220723 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes +system.physmem.avgGap 706183.54 # Average gap between requests +system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 566682480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309201750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1531779600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 983877840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 69780771990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 228217880250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 332897011590 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.111043 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 379065618250 # Time in different power states +system.physmem_0.memoryStateTime::REF 16107780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87208649000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.434954 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states +system.physmem_1.actEnergy 539164080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 294186750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1489098000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 930690000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 67080778605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230586295500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 332427030615 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.136751 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 383030551000 # Time in different power states +system.physmem_1.memoryStateTime::REF 16107780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 83243489000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 297786504 # Number of BP lookups -system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 297919436 # Number of BP lookups +system.cpu.branchPred.condPredicted 297919436 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23611614 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229854393 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40311454 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4410387 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229854393 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119921311 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 109933082 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11586406 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 963915252 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 964764115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 229640733 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587519909 # Number of instructions fetch has processed +system.cpu.fetch.Branches 297919436 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160232765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 710474501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48125197 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1838 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31961 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 395431 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 7638 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216406816 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6303131 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 964614734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.081549 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.494827 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 473031835 49.04% 49.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36413294 3.77% 52.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36207947 3.75% 56.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33239258 3.45% 60.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28476947 2.95% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30017172 3.11% 66.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40187194 4.17% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37484755 3.89% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249556332 25.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 964614734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308800 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.645501 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165560291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 381637451 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312327895 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81026499 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24062598 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2744008679 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24062598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201558349 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 194036216 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13250 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351418098 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 193526223 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2626516746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 906315 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 120859920 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 22304361 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 41770089 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707207684 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6591914084 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4206827635 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2574467 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 921 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090246112 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1066 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 982 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 368286677 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608256588 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244134978 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253265740 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76368619 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419508786 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 132419 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999186857 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3656712 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889558685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510180986 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 131867 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964614734 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.072524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.106121 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 336173556 34.85% 34.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135262022 14.02% 48.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129832579 13.46% 62.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119015920 12.34% 74.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 98090682 10.17% 84.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67084509 6.95% 91.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45576707 4.72% 96.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22663670 2.35% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10915089 1.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964614734 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11249182 43.29% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11894821 45.77% 89.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2844033 10.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2910415 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333514799 66.70% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 358060 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798571 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued @@ -460,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471222917 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186382093 9.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued -system.cpu.iq.rate 2.074089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999186857 # Type of FU issued +system.cpu.iq.rate 2.072203 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25988036 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012999 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4991322155 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3305635589 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1923777377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1311041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4133688 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 240317 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021708405 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 556073 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179295064 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224173511 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 339017 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 636964 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94976783 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31958 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24062598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144797851 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6250562 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419641205 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1306710 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608256824 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244134978 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 45669 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1454928 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3966770 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 636964 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8731316 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20649413 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29380729 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945668790 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456756594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53518067 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed -system.cpu.iew.exec_branches 185171662 # Number of branches executed -system.cpu.iew.exec_stores 178831439 # Number of stores executed -system.cpu.iew.exec_rate 2.018648 # Inst execution rate -system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457092334 # num instructions producing a value -system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value -system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635598570 # number of memory reference insts executed +system.cpu.iew.exec_branches 185172751 # Number of branches executed +system.cpu.iew.exec_stores 178841976 # Number of stores executed +system.cpu.iew.exec_rate 2.016730 # Inst execution rate +system.cpu.iew.wb_sent 1934534562 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924017694 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1456930726 # num instructions producing a value +system.cpu.iew.wb_consumers 2203703226 # num instructions consuming a value +system.cpu.iew.wb_rate 1.994288 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661128 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889633438 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23642184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831915086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.839229 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.465352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 352165945 42.33% 42.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184695932 22.20% 64.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57945588 6.97% 71.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87210863 10.48% 81.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30437769 3.66% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26536432 3.19% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10472867 1.26% 90.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9005135 1.08% 91.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73444555 8.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831915086 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -581,489 +576,496 @@ system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3177371770 # The number of ROB reads -system.cpu.rob.rob_writes 4973814894 # The number of ROB writes -system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73444555 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3178186489 # The number of ROB reads +system.cpu.rob.rob_writes 4973800859 # The number of ROB writes +system.cpu.timesIdled 2058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 149381 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads -system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads -system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes -system.cpu.fp_regfile_reads 239177 # number of floating regfile reads -system.cpu.fp_regfile_writes 8 # number of floating regfile writes -system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads -system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads +system.cpu.cpi 1.166798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.166798 # CPI: Total CPI of All Threads +system.cpu.ipc 0.857046 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.857046 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928420991 # number of integer regfile reads +system.cpu.int_regfile_writes 1576721018 # number of integer regfile writes +system.cpu.fp_regfile_reads 241306 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.cc_regfile_reads 617864492 # number of cc regfile reads +system.cpu.cc_regfile_writes 419924545 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064270268 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2545945 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2546182 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.922606 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 421485651 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550278 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.270473 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1898151500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.922606 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998028 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998028 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits -system.cpu.dcache.overall_hits::total 421064470 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses -system.cpu.dcache.overall_misses::total 3357607 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 852234240 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 852234240 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 273116230 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 273116230 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366946 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366946 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 421483176 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 421483176 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 421483176 # number of overall hits +system.cpu.dcache.overall_hits::total 421483176 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2567540 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2567540 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791265 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791265 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3358805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3358805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3358805 # number of overall misses +system.cpu.dcache.overall_misses::total 3358805 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57574934000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57574934000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24743790498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24743790498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 82318724498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 82318724498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 82318724498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 82318724498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275683770 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275683770 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 424841981 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424841981 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424841981 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424841981 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009313 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009313 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks -system.cpu.dcache.writebacks::total 2337968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007906 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007906 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007906 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007906 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22424.162428 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22424.162428 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31271.180323 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31271.180323 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24508.336893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24508.336893 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1268 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 857 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.832031 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432820961 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432820961 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 216397172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216397172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216397172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216397172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216397172 # number of overall hits +system.cpu.icache.overall_hits::total 216397172 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9643 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36772.944001 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4014 # number of writebacks -system.cpu.icache.writebacks::total 4014 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7390 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7390 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7390 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7390 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7390 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243725000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243725000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243725000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243725000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243725000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243725000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 4041 # number of writebacks +system.cpu.icache.writebacks::total 4041 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2312 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2312 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2312 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2312 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2312 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2312 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7331 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7331 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7331 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7331 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7331 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 251236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 251236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251236999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 251236999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26967067000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks +system.cpu.l2cache.writebacks::total 295491 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2424 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2424 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178367 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178367 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 385169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 387593 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 385169 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 387593 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14535147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14535147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 179310000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 179310000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12743139000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12743139000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179310000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27278286500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27457596500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179310000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27278286500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27457596500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.426253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100661 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100661 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151373 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151373 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765958 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649345 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 619648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312832576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313452224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 356883 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18985088 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2914251 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066139 # Request fanout histogram +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003171 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263749 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263749 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100990 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100990 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151644 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151644 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70285.333314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70285.333314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73972.772277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73972.772277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71443.366766 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71443.366766 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109409 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551871 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7932 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2949 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1773523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4041 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766192 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 620608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312840768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313461376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357696 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19018624 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2915207 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004295 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.065414 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2901462 99.56% 99.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12784 0.44% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2902688 99.57% 99.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12516 0.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2915207 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896659390 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10998496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3826206608 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180179 # Transaction distribution -system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution -system.membus.trans_dist::CleanEvict 57436 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution -system.membus.trans_dist::ReadExReq 206676 # Transaction distribution -system.membus.trans_dist::ReadExResp 206676 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 740700 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353605 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180791 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution +system.membus.trans_dist::CleanEvict 57611 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 206801 # Transaction distribution +system.membus.trans_dist::ReadExResp 206801 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180791 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43717312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43717312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43717312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 740563 # Request fanout histogram +system.membus.snoop_fanout::samples 387598 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387598 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 740563 # Request fanout histogram -system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387598 # Request fanout histogram +system.membus.reqLayer0.occupancy 1995849000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2051150500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index ff2284b45..76b9b35da 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885773 # Nu sim_ticks 885772926000 # Number of ticks simulated final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 771975 # Simulator instruction rate (inst/s) -host_op_rate 1428542 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 826990545 # Simulator tick rate (ticks/s) -host_mem_usage 269652 # Number of bytes of host memory used -host_seconds 1071.08 # Real time elapsed on the host +host_inst_rate 861241 # Simulator instruction rate (inst/s) +host_op_rate 1593729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 922618164 # Simulator tick rate (ticks/s) +host_mem_usage 273768 # Number of bytes of host memory used +host_seconds 960.06 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 11823849838 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram -system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1601552189 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1601552189 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index b7bd8e61b..9b8e6bb2d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650501 # Number of seconds simulated -sim_ticks 1650501252500 # Number of ticks simulated -final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650924 # Number of seconds simulated +sim_ticks 1650923912500 # Number of ticks simulated +final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 516047 # Simulator instruction rate (inst/s) -host_op_rate 954946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1030101248 # Simulator tick rate (ticks/s) -host_mem_usage 278616 # Number of bytes of host memory used -host_seconds 1602.27 # Real time elapsed on the host +host_inst_rate 598809 # Simulator instruction rate (inst/s) +host_op_rate 1108098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1195612149 # Simulator tick rate (ticks/s) +host_mem_usage 285816 # Number of bytes of host memory used +host_seconds 1380.82 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory -system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory -system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory +system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory +system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory +system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3301002505 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3301847825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826847304 # Number of instructions committed @@ -66,7 +66,7 @@ system.cpu.num_mem_refs 533241508 # nu system.cpu.num_load_insts 384083313 # Number of load instructions system.cpu.num_store_insts 149158195 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149981740 # Number of branches fetched @@ -105,16 +105,16 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2517016 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id @@ -124,7 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits @@ -141,14 +141,14 @@ system.cpu.dcache.demand_misses::cpu.data 2521112 # n system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses system.cpu.dcache.overall_misses::total 2521112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) @@ -165,22 +165,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks -system.cpu.dcache.writebacks::total 2325221 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks +system.cpu.dcache.writebacks::total 2324919 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses @@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses @@ -205,22 +205,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id @@ -232,7 +232,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits @@ -245,12 +245,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses @@ -263,12 +263,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -283,89 +283,88 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124423000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 348438 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 349420 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits -system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses -system.cpu.l2cache.overall_misses::total 380855 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 584841 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 # 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number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses +system.cpu.l2cache.overall_misses::total 381691 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) @@ -380,101 +379,101 @@ system.cpu.l2cache.demand_accesses::total 2523926 # n system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks -system.cpu.l2cache.writebacks::total 293208 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks +system.cpu.l2cache.writebacks::total 293952 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution @@ -483,55 +482,61 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348438 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18765312 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 349420 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 174499 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution -system.membus.trans_dist::CleanEvict 53507 # Transaction distribution -system.membus.trans_dist::ReadExReq 206356 # Transaction distribution -system.membus.trans_dist::ReadExResp 206356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 175162 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution +system.membus.trans_dist::CleanEvict 53608 # Transaction distribution +system.membus.trans_dist::ReadExReq 206529 # Transaction distribution +system.membus.trans_dist::ReadExResp 206529 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 727569 # Request fanout histogram +system.membus.snoop_fanout::samples 381691 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727569 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381691 # Request fanout histogram +system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index b65c3962a..6b30c3cf1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233526 # Number of seconds simulated -sim_ticks 233525789500 # Number of ticks simulated -final_tick 233525789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233534 # Number of seconds simulated +sim_ticks 233533887500 # Number of ticks simulated +final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279317 # Simulator instruction rate (inst/s) -host_op_rate 279317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163615265 # Simulator tick rate (ticks/s) -host_mem_usage 255720 # Number of bytes of host memory used -host_seconds 1427.29 # Real time elapsed on the host +host_inst_rate 225573 # Simulator instruction rate (inst/s) +host_op_rate 225573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132138421 # Simulator tick rate (ticks/s) +host_mem_usage 260868 # Number of bytes of host memory used +host_seconds 1767.34 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1090209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1090209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233525688500 # Total gap between requests +system.physmem.totGap 233533785500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.852693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.480715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.694198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 535 34.72% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.32% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 186 12.07% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 104 6.75% 75.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 66 4.28% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 53 3.44% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 1.82% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.53% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 186 12.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation -system.physmem.totQLat 52273750 # Total ticks spent queuing -system.physmem.totMemAccLat 199892500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.totQLat 53440000 # Total ticks spent queuing +system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6639.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25389.62 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6330 # Number of row buffer hits during reads +system.physmem.readRowHits 6327 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29661588.78 # Average gap between requests -system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6804000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3712500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29662617.24 # Average gap between requests +system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5982776145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134867232750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 156147584715 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.653337 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 224361889750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1365674000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4845960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2644125 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5743132470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 135077446500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 156107858775 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.483223 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 224713608000 # Time in different power states -system.physmem_1.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.481917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1013955750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912937 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702744 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 45912940 # Number of BP lookups +system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186730 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689251 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249877 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13974 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95338457 # DTB read hits +system.cpu.dtb.read_hits 95338456 # DTB read hits system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95338573 # DTB read accesses +system.cpu.dtb.read_accesses 95338572 # DTB read accesses system.cpu.dtb.write_hits 73578378 # DTB write hits system.cpu.dtb.write_misses 849 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 73579227 # DTB write accesses -system.cpu.dtb.data_hits 168916835 # DTB hits +system.cpu.dtb.data_hits 168916834 # DTB hits system.cpu.dtb.data_misses 965 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917800 # DTB accesses -system.cpu.itb.fetch_hits 96959231 # ITB hits +system.cpu.dtb.data_accesses 168917799 # DTB accesses +system.cpu.itb.fetch_hits 96959232 # ITB hits system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960470 # ITB accesses +system.cpu.itb.fetch_accesses 96960471 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467051579 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 467067775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664651 # Number of instructions committed system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.171540 # CPI: cycles per instruction -system.cpu.ipc 0.853577 # IPC: instructions per cycle +system.cpu.cpi 1.171581 # CPI: cycles per instruction +system.cpu.ipc 0.853548 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction @@ -344,18 +344,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455740556 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11311023 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked +system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.966637 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817023 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.202401 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.966637 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -365,31 +365,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514800 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514800 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817023 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817023 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817023 # number of overall hits -system.cpu.dcache.overall_hits::total 167817023 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits +system.cpu.dcache.overall_hits::total 167817024 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5929 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5929 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6990 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6990 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6990 # number of overall misses -system.cpu.dcache.overall_misses::total 6990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77930500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77930500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 429190000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 429190000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 507120500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 507120500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses +system.cpu.dcache.overall_misses::total 6989 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73450.047125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73450.047125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72388.261090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72388.261090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72549.427754 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2733 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2733 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2825 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310193000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310193000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -454,69 +454,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3193 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.750364 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954060 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18749.576484 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.750364 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937378 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923633 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923633 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954060 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954060 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954060 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954060 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954060 # number of overall hits -system.cpu.icache.overall_hits::total 96954060 # number of overall hits +system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits +system.cpu.icache.overall_hits::total 96954061 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses system.cpu.icache.overall_misses::total 5171 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 318040500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 318040500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 318040500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 318040500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959231 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959231 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959231 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959231 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 96959232 # 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average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,47 +531,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5171 system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312869500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312869500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 316777500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 316777500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4425.384656 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4801 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.910487 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 7128.160045 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.689318 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 372.164909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.179805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 642.039942 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011358 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019594 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4442 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114871 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114871 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.137560 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3717.022485 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104100 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113435 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.217534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits @@ -600,18 +599,18 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 291713500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 301944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 593657500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 291713500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 301944000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 593657500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 295621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 307079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 602700500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 295621500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 307079000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 602700500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses) @@ -640,18 +639,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.843295 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75404.229646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75404.229646 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,18 +669,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252763500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 514927500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252763500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 514927500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses @@ -694,25 +693,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution @@ -744,9 +743,15 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution @@ -767,9 +772,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9219000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41801750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 81cd1b880..71e9e3432 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064189 # Number of seconds simulated -sim_ticks 64188759000 # Number of ticks simulated -final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064159 # Number of seconds simulated +sim_ticks 64159445000 # Number of ticks simulated +final_tick 64159445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260398 # Simulator instruction rate (inst/s) -host_op_rate 260398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44504184 # Simulator tick rate (ticks/s) -host_mem_usage 257256 # Number of bytes of host memory used -host_seconds 1442.31 # Real time elapsed on the host +host_inst_rate 223776 # Simulator instruction rate (inst/s) +host_op_rate 223776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38227708 # Simulator tick rate (ticks/s) +host_mem_usage 261380 # Number of bytes of host memory used +host_seconds 1678.35 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 220736 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 476160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 476096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220736 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3449 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7440 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3439855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3978267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7418121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3439855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3439855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3439855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3978267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7418121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7440 # Number of read requests accepted +system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3440429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3980084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7420513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3440429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3440429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3440429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3980084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7420513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7439 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7440 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476160 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 476096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476160 # Total read bytes from the system interface side +system.physmem.bytesReadSys 476096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::10 339 # Pe system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 540 # Per bank write bursts -system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::14 453 # Per bank write bursts system.physmem.perBankRdBursts::15 380 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64188663500 # Total gap between requests +system.physmem.totGap 64159334500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7440 # Read request sizes (log2) +system.physmem.readPktSize::6 7439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.287187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.380841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.777138 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 32.62% 32.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 304 22.39% 55.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 160 11.78% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 7.07% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.98% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 38 2.80% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.80% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.84% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 200 14.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1358 # Bytes accessed per row activation -system.physmem.totQLat 65294500 # Total ticks spent queuing -system.physmem.totMemAccLat 204794500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8776.14 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.640474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.024877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.175025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 440 32.62% 32.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 302 22.39% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 154 11.42% 66.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 83 6.15% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 3.93% 76.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 50 3.71% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.67% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 35 2.59% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation +system.physmem.totQLat 63577500 # Total ticks spent queuing +system.physmem.totMemAccLat 203058750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8546.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27526.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27296.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.42 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6069 # Number of row buffer hits during reads +system.physmem.readRowHits 6088 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8627508.53 # Average gap between requests -system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32221800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 8624725.70 # Average gap between requests +system.physmem.pageHitRate 81.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5821200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3176250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1996054785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36758466000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42987835170 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.776911 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61149211250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_0.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1995176700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36745221000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42972346350 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.779347 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61126318750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2142400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 890802750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 890255000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25217400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4377240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2388375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25560600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1854861795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36882319500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42961259445 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.362844 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61355238000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_1.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1859740425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36864024750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42946625790 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.378459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61324552000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2142400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 692021750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 47858697 # Number of BP lookups -system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 23334340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19575055 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 47856205 # Number of BP lookups +system.cpu.branchPred.condPredicted 27886274 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 572784 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 23348714 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19574502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.889474 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8688210 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1446 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2339152 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2308305 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 30847 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111425 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 83.835461 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8687459 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1418 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2338624 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2308001 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 30623 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 111239 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 98833092 # DTB read hits -system.cpu.dtb.read_misses 28443 # DTB read misses -system.cpu.dtb.read_acv 867 # DTB read access violations -system.cpu.dtb.read_accesses 98861535 # DTB read accesses -system.cpu.dtb.write_hits 75500788 # DTB write hits +system.cpu.dtb.read_hits 98829712 # DTB read hits +system.cpu.dtb.read_misses 28367 # DTB read misses +system.cpu.dtb.read_acv 845 # DTB read access violations +system.cpu.dtb.read_accesses 98858079 # DTB read accesses +system.cpu.dtb.write_hits 75499203 # DTB write hits system.cpu.dtb.write_misses 1454 # DTB write misses system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 75502242 # DTB write accesses -system.cpu.dtb.data_hits 174333880 # DTB hits -system.cpu.dtb.data_misses 29897 # DTB misses -system.cpu.dtb.data_acv 870 # DTB access violations -system.cpu.dtb.data_accesses 174363777 # DTB accesses -system.cpu.itb.fetch_hits 46960311 # ITB hits -system.cpu.itb.fetch_misses 430 # ITB misses -system.cpu.itb.fetch_acv 5 # ITB acv -system.cpu.itb.fetch_accesses 46960741 # ITB accesses +system.cpu.dtb.write_accesses 75500657 # DTB write accesses +system.cpu.dtb.data_hits 174328915 # DTB hits +system.cpu.dtb.data_misses 29821 # DTB misses +system.cpu.dtb.data_acv 848 # DTB access violations +system.cpu.dtb.data_accesses 174358736 # DTB accesses +system.cpu.itb.fetch_hits 46955913 # ITB hits +system.cpu.itb.fetch_misses 420 # ITB misses +system.cpu.itb.fetch_acv 7 # ITB acv +system.cpu.itb.fetch_accesses 46956333 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,141 +299,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 128377521 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 128318893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 47431154 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 424848239 # Number of instructions fetch has processed -system.cpu.fetch.Branches 47858697 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 30571570 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80009353 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1247564 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 47425719 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 424811206 # Number of instructions fetch has processed +system.cpu.fetch.Branches 47856205 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 30569962 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79950349 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1246202 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13513 # Number of stall cycles due to pending traps +system.cpu.fetch.MiscStallCycles 270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13187 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 46960311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 225671 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128078159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.317101 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 46955913 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 225768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128012699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.318508 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.349839 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53091522 41.45% 41.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4331488 3.38% 44.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6713646 5.24% 50.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5106781 3.99% 54.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10967794 8.56% 62.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7526071 5.88% 68.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5305239 4.14% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1848793 1.44% 74.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33186825 25.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53041219 41.43% 41.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4325218 3.38% 44.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6711253 5.24% 50.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5104898 3.99% 54.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10968142 8.57% 62.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7524114 5.88% 68.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5300788 4.14% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1845614 1.44% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33191453 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128078159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372797 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.309366 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42083889 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13603478 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67893810 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3877357 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 619625 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 8883159 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4198 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 421926458 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 13804 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 619625 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43653235 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3048927 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 516546 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70101215 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10138611 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419911173 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439346 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2543427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2848893 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3543199 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 273983157 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 552185759 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 393726185 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 158459573 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 128012699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372947 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.310590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42125446 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13481218 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 67948873 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3838220 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 618942 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 8882912 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4201 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 421902807 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 618942 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43678343 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3058028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 517106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70134710 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10005570 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 419884966 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 437260 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2526892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2765017 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3520699 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 273968908 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 552151473 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 393698766 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 158452706 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14450838 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14436589 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 37562 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15867681 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 99739292 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 76524203 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11895065 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9302116 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392194254 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 15635470 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 99735139 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 76519296 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11859955 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9294086 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392181792 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 389210938 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 196221 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16619749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7681566 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 389203558 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 195886 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16607287 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7664931 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128078159 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.038855 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.181056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 128012699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.040351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.180919 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17247166 13.47% 13.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19402738 15.15% 28.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008781 17.18% 45.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17964276 14.03% 59.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19060613 14.88% 74.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13269746 10.36% 85.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8793023 6.87% 91.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6106038 4.77% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4225778 3.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17224377 13.46% 13.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19358192 15.12% 28.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22001472 17.19% 45.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17955910 14.03% 59.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19066405 14.89% 74.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13282652 10.38% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8794829 6.87% 91.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6104058 4.77% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4224804 3.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128078159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128012699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 255592 1.41% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138975 0.77% 2.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 79489 0.44% 2.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3727 0.02% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3445589 19.00% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1648341 9.09% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8051616 44.40% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4508979 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 256922 1.42% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138470 0.76% 2.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 78848 0.44% 2.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3339 0.02% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3443164 19.01% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1648895 9.10% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8039924 44.38% 75.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4505956 24.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 146987981 37.77% 37.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128295 0.55% 38.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 146986421 37.77% 37.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128250 0.55% 38.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 36418632 9.36% 47.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7354909 1.89% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2800462 0.72% 50.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556521 4.25% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584140 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 36418938 9.36% 47.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7355017 1.89% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2800646 0.72% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556809 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1584153 0.41% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued @@ -455,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99505104 25.57% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 75841313 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99502900 25.57% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 75836843 19.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 389210938 # Type of FU issued -system.cpu.iq.rate 3.031769 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18132308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046587 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 592570653 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 242193331 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 227932630 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332257911 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166691582 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158290719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 234731368 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172578297 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19373689 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 389203558 # Type of FU issued +system.cpu.iq.rate 3.033096 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18115520 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046545 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 592493180 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 242176639 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 227925873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 332238041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 166682962 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158291544 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 234723560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172561937 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19352464 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4984806 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 93159 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 70985 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3003475 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4980653 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 92349 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 70589 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2998568 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382536 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 383293 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3853 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 619625 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1856570 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 132026 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 415917767 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108843 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 99739292 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 76524203 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 618942 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1854909 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 149633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 415904338 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108226 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 99735139 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 76519296 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 123512 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 70985 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 411741 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230567 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 642308 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 387626106 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98862428 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1584832 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 7462 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 141873 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 70589 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 411438 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230495 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 641933 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 387616397 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98858950 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1587161 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 23723223 # number of nop insts executed -system.cpu.iew.exec_refs 174364706 # number of memory reference insts executed -system.cpu.iew.exec_branches 45864043 # Number of branches executed -system.cpu.iew.exec_stores 75502278 # Number of stores executed -system.cpu.iew.exec_rate 3.019424 # Inst execution rate -system.cpu.iew.wb_sent 386487511 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 386223349 # cumulative count of insts written-back -system.cpu.iew.wb_producers 192322376 # num instructions producing a value -system.cpu.iew.wb_consumers 273878502 # num instructions consuming a value -system.cpu.iew.wb_rate 3.008497 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.702218 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17254297 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 23722256 # number of nop insts executed +system.cpu.iew.exec_refs 174359643 # number of memory reference insts executed +system.cpu.iew.exec_branches 45862472 # Number of branches executed +system.cpu.iew.exec_stores 75500693 # Number of stores executed +system.cpu.iew.exec_rate 3.020727 # Inst execution rate +system.cpu.iew.wb_sent 386480663 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 386217417 # cumulative count of insts written-back +system.cpu.iew.wb_producers 192328787 # num instructions producing a value +system.cpu.iew.wb_consumers 273868663 # num instructions consuming a value +system.cpu.iew.wb_rate 3.009825 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.702266 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17240745 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569011 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125612042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.173777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.248518 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 568625 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125549188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.175366 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.248155 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42074654 33.50% 33.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17552788 13.97% 47.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 8725383 6.95% 54.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9055727 7.21% 61.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6223211 4.95% 66.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4119483 3.28% 69.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4738198 3.77% 73.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2406397 1.92% 75.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30716201 24.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42020703 33.47% 33.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17522364 13.96% 47.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 8729636 6.95% 54.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9062074 7.22% 61.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6240745 4.97% 66.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4112376 3.28% 69.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4753795 3.79% 73.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2410879 1.92% 75.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30696616 24.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125612042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125549188 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664569 # Number of instructions committed system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,33 +576,33 @@ system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction -system.cpu.commit.bw_lim_events 30716201 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 510811730 # The number of ROB reads -system.cpu.rob.rob_writes 834310252 # The number of ROB writes -system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 299362 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30696616 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 510754909 # The number of ROB reads +system.cpu.rob.rob_writes 834280363 # The number of ROB writes +system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 306194 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.341816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.341816 # CPI: Total CPI of All Threads -system.cpu.ipc 2.925550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.925550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 385452871 # number of integer regfile reads -system.cpu.int_regfile_writes 165252221 # number of integer regfile writes -system.cpu.fp_regfile_reads 154536644 # number of floating regfile reads -system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes +system.cpu.cpi 0.341660 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.341660 # CPI: Total CPI of All Threads +system.cpu.ipc 2.926886 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.926886 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 385442521 # number of integer regfile reads +system.cpu.int_regfile_writes 165246956 # number of integer regfile writes +system.cpu.fp_regfile_reads 154535424 # number of floating regfile reads +system.cpu.fp_regfile_writes 102076666 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776 # number of replacements -system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4176 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36535.653496 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 779 # number of replacements +system.cpu.dcache.tags.tagsinuse 3291.925722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 152589979 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4179 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36513.514956 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3292.009184 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803713 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803713 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.925722 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -610,45 +610,45 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501036 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 305227185 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 305227185 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 79088959 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79088959 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501014 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501014 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 152572883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152572883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152572883 # number of overall hits -system.cpu.dcache.overall_hits::total 152572883 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1826 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1826 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19692 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19692 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21518 # number of overall misses -system.cpu.dcache.overall_misses::total 21518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128481000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128481000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1201737956 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1201737956 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1330218956 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1330218956 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1330218956 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1330218956 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79073673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79073673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 152589973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152589973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152589973 # number of overall hits +system.cpu.dcache.overall_hits::total 152589973 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19714 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19714 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21524 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21524 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21524 # number of overall misses +system.cpu.dcache.overall_misses::total 21524 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128203000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128203000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1194602455 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1194602455 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1322805455 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1322805455 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1322805455 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1322805455 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79090769 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79090769 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 152594401 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 152594401 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 152594401 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 152594401 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 152611497 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 152611497 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 152611497 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 152611497 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses @@ -657,258 +657,257 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000141 system.cpu.dcache.demand_miss_rate::total 0.000141 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000141 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70361.993428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70361.993428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61026.709120 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61026.709120 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61818.893763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61818.893763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 50592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 80 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 740 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70830.386740 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70830.386740 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60596.654915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60596.654915 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61457.231695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61457.231695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49869 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 741 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.367568 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 838 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 838 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16504 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16504 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17342 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17342 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17342 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17342 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 74762500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 74762500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 249321500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 249321500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 324084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 324084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 324084000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 324084000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.299595 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 658 # 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number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4179 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4179 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4179 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4179 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 251163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 251163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 327202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 327202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 327202500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 327202500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000013 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75670.546559 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75670.546559 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78206.242158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78206.242158 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2132 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4060 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11565.188670 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76885.237614 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76885.237614 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78734.482759 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78734.482759 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2131 # number of replacements +system.cpu.icache.tags.tagsinuse 1829.791655 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 46950265 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4058 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11569.804091 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.246133 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses -system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 46954666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 46954666 # number of overall hits -system.cpu.icache.overall_hits::total 46954666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5645 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5645 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5645 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5645 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5645 # number of overall misses -system.cpu.icache.overall_misses::total 5645 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 370489499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 370489499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 370489499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 370489499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 370489499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 370489499 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 93915884 # Number of tag accesses +system.cpu.icache.tags.data_accesses 93915884 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 46950265 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 46950265 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 46950265 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 46950265 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 46950265 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373323999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 46955913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 46955913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 46955913 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 46955913 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 46955913 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 46955913 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000120 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000120 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000120 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000120 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66098.441749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66098.441749 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 575 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.888889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849926 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.954774 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.903120 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849926 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.954774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.903120 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78525.575448 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78525.575448 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76940.852421 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76940.852421 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84840.487239 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84840.487239 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76940.852421 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79889.849624 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78522.583681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76940.852421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79889.849624 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78522.583681 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -917,116 +916,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3128 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3128 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3450 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3450 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3449 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3449 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 862 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 862 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3449 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7440 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3449 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7440 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 212530500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 212530500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228307000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228307000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63243500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63243500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228307000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275774000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 504081000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228307000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275774000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 504081000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849754 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.872470 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.872470 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903351 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67944.533248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67944.533248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66175.942029 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66175.942029 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73368.329466 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73368.329466 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 11144 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2908 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_misses::total 7439 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 214348000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 214348000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 230879000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 230879000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 64512500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 64512500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 278860500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 509739500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230879000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 278860500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 509739500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980564 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980564 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849926 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.871587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.871587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903120 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903120 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68525.575448 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68525.575448 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66940.852421 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66940.852421 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74840.487239 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74840.487239 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 11147 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2910 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2131 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 988 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19380 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4058 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 989 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9137 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 705664 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 8236 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8237 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8236 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8237 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8236 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8359000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8237 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8362500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6090499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6087499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6268500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4312 # Transaction distribution +system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4311 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4312 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14880 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 476160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4311 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14878 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 476096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7440 # Request fanout histogram +system.membus.snoop_fanout::samples 7439 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7440 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7439 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7440 # Request fanout histogram -system.membus.reqLayer0.occupancy 9246500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7439 # Request fanout histogram +system.membus.reqLayer0.occupancy 9245500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39238750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39234750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 9532c68be..33645e09f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567385 # Number of seconds simulated -sim_ticks 567385356500 # Number of ticks simulated -final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567393 # Number of seconds simulated +sim_ticks 567392530500 # Number of ticks simulated +final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154582 # Simulator instruction rate (inst/s) -host_op_rate 1154582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1643217424 # Simulator tick rate (ticks/s) -host_mem_usage 254440 # Number of bytes of host memory used -host_seconds 345.29 # Real time elapsed on the host +host_inst_rate 646502 # Simulator instruction rate (inst/s) +host_op_rate 646502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 920122456 # Simulator tick rate (ticks/s) +host_mem_usage 259072 # Number of bytes of host memory used +host_seconds 616.65 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory system.physmem.bytes_read::total 459136 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 567385356500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1134770713 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1134785061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134770713 # Number of busy cycles +system.cpu.num_busy_cycles 1134785061 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -124,16 +124,16 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id @@ -143,7 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -224,34 +224,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,48 +302,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits @@ -372,18 +370,18 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) @@ -412,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,18 +440,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses @@ -466,25 +464,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution @@ -518,7 +516,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 0b49d498f..a1a985a56 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.225030 # Number of seconds simulated -sim_ticks 225030243000 # Number of ticks simulated -final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225041 # Number of seconds simulated +sim_ticks 225040911000 # Number of ticks simulated +final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131394 # Simulator instruction rate (inst/s) -host_op_rate 157754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108291606 # Simulator tick rate (ticks/s) -host_mem_usage 275248 # Number of bytes of host memory used -host_seconds 2078.00 # Real time elapsed on the host +host_inst_rate 161529 # Simulator instruction rate (inst/s) +host_op_rate 193933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 133133968 # Simulator tick rate (ticks/s) +host_mem_usage 280148 # Number of bytes of host memory used +host_seconds 1690.33 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory system.physmem.bytes_read::total 485568 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 219136 # Nu system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7587 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 225029996000 # Total gap between requests +system.physmem.totGap 225040663000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation -system.physmem.totQLat 51456750 # Total ticks spent queuing -system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation +system.physmem.totQLat 55497500 # Total ticks spent queuing +system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,48 +217,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6068 # Number of row buffer hits during reads +system.physmem.readRowHits 6044 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29659944.11 # Average gap between requests -system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29661350.07 # Average gap between requests +system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.664832 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states +system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.691134 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.764823 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states +system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.800930 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32430290 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32430292 # Number of BP lookups system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 2264813 # Nu system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 450060486 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450081822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037855 # Number of instructions committed system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.648345 # CPI: cycles per instruction -system.cpu.ipc 0.606669 # IPC: instructions per cycle +system.cpu.cpi 1.648423 # CPI: cycles per instruction +system.cpu.ipc 0.606640 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id @@ -451,43 +451,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits -system.cpu.dcache.overall_hits::total 168632427 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits +system.cpu.dcache.overall_hits::total 168632429 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses -system.cpu.dcache.overall_misses::total 6936 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses +system.cpu.dcache.overall_misses::total 6935 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,12 +528,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -564,72 +564,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits -system.cpu.icache.overall_hits::total 69819783 # number of overall hits +system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits +system.cpu.icache.overall_hits::total 69819782 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126 system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits @@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 7630 # nu system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214976500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214976500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 256075000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 256075000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 105174500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 105174500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 256075000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 320151000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 576226000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 256075000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 320151000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 576226000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) @@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.170931 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75324.632095 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75324.632095 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74744.600117 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74744.600117 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77907.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77907.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75521.100917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75521.100917 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7587 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186436500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186436500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 221700500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 221700500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 89390500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 89390500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 221700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275827000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 497527500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 221700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275827000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 497527500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses @@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65324.632095 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65324.632095 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64748.977804 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64748.977804 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution @@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 60188498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution @@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 01e70293e..3bab29953 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.111754 # Number of seconds simulated -sim_ticks 111753553500 # Number of ticks simulated -final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.120480 # Number of seconds simulated +sim_ticks 120480458500 # Number of ticks simulated +final_tick 120480458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142273 # Simulator instruction rate (inst/s) -host_op_rate 170814 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58231903 # Simulator tick rate (ticks/s) -host_mem_usage 288696 # Number of bytes of host memory used -host_seconds 1919.11 # Real time elapsed on the host -sim_insts 273037220 # Number of instructions simulated -sim_ops 327811602 # Number of ops (including micro ops) simulated +host_inst_rate 129515 # Simulator instruction rate (inst/s) +host_op_rate 155497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57149813 # Simulator tick rate (ticks/s) +host_mem_usage 293332 # Number of bytes of host memory used +host_seconds 2108.15 # Real time elapsed on the host +sim_insts 273037218 # Number of instructions simulated +sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory -system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 84617 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 5552790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 41395659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1510753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48459202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5552790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5552790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5552790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 41395659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1510753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 48459202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 84617 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1888064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14651392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167808 # Number of bytes read from this memory +system.physmem.bytes_read::total 16707264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1888064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1888064 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2622 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261051 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15671122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 121608037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1392823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138671982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15671122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15671122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15671122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 121608037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1392823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138671982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261052 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 84617 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261052 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5415488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16707328 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5415488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16707328 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956 # Per bank write bursts -system.physmem.perBankRdBursts::1 811 # Per bank write bursts -system.physmem.perBankRdBursts::2 834 # Per bank write bursts -system.physmem.perBankRdBursts::3 2907 # Per bank write bursts -system.physmem.perBankRdBursts::4 10637 # Per bank write bursts -system.physmem.perBankRdBursts::5 59817 # Per bank write bursts -system.physmem.perBankRdBursts::6 152 # Per bank write bursts -system.physmem.perBankRdBursts::7 259 # Per bank write bursts -system.physmem.perBankRdBursts::8 225 # Per bank write bursts -system.physmem.perBankRdBursts::9 303 # Per bank write bursts -system.physmem.perBankRdBursts::10 3870 # Per bank write bursts -system.physmem.perBankRdBursts::11 811 # Per bank write bursts -system.physmem.perBankRdBursts::12 1141 # Per bank write bursts -system.physmem.perBankRdBursts::13 693 # Per bank write bursts -system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 563 # Per bank write bursts +system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::1 69992 # Per bank write bursts +system.physmem.perBankRdBursts::2 1296 # Per bank write bursts +system.physmem.perBankRdBursts::3 10757 # Per bank write bursts +system.physmem.perBankRdBursts::4 42908 # Per bank write bursts +system.physmem.perBankRdBursts::5 121820 # Per bank write bursts +system.physmem.perBankRdBursts::6 160 # Per bank write bursts +system.physmem.perBankRdBursts::7 266 # Per bank write bursts +system.physmem.perBankRdBursts::8 224 # Per bank write bursts +system.physmem.perBankRdBursts::9 562 # Per bank write bursts +system.physmem.perBankRdBursts::10 7776 # Per bank write bursts +system.physmem.perBankRdBursts::11 812 # Per bank write bursts +system.physmem.perBankRdBursts::12 1213 # Per bank write bursts +system.physmem.perBankRdBursts::13 743 # Per bank write bursts +system.physmem.perBankRdBursts::14 656 # Per bank write bursts +system.physmem.perBankRdBursts::15 609 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 111753395000 # Total gap between requests +system.physmem.totGap 120480449000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 84617 # Read request sizes (log2) +system.physmem.readPktSize::6 261052 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,19 +95,19 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 64967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12075 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -191,86 +191,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 254.217463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.921670 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 155.515771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 2572 12.08% 12.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7102 33.36% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8141 38.24% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1445 6.79% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1060 4.98% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 699 3.28% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 0.15% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 27 0.13% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 212 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21291 # Bytes accessed per row activation -system.physmem.totQLat 818886094 # Total ticks spent queuing -system.physmem.totMemAccLat 2405454844 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 423085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9677.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.160415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.717328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 205.520754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18369 27.40% 27.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21159 31.56% 58.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11457 17.09% 76.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6629 9.89% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4618 6.89% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2220 3.31% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1372 2.05% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 491 0.73% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 730 1.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67045 # Bytes accessed per row activation +system.physmem.totQLat 2500931533 # Total ticks spent queuing +system.physmem.totMemAccLat 7395656533 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305260000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9580.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28427.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28330.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 138.67 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.46 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 138.67 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.38 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.08 # Data bus utilization in percentage +system.physmem.busUtilRead 1.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 63316 # Number of row buffer hits during reads +system.physmem.readRowHits 193998 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.31 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1320696.73 # Average gap between requests -system.physmem.pageHitRate 74.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 137093040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74802750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 595467600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 461518.97 # Average gap between requests +system.physmem.pageHitRate 74.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 469687680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 256278000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1937777400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61580578995 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 13031079750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 82717875255 # Total energy per rank (pJ) -system.physmem_0.averagePower 740.214288 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 21327892271 # Time in different power states -system.physmem_0.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_0.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73664414550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7668236250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 91865342760 # Total energy per rank (pJ) +system.physmem_0.averagePower 762.514125 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12350213739 # Time in different power states +system.physmem_0.memoryStateTime::REF 4022980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 86689152979 # Time in different power states +system.physmem_0.memoryStateTime::ACT 104104852261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 23821560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 12997875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 64092600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 37134720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 20262000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 98069400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10878672015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ) -system.physmem_1.averagePower 678.173227 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states -system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_1.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 16939770435 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 57426696000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 82390881435 # Total energy per rank (pJ) +system.physmem_1.averagePower 683.872818 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 95444315624 # Time in different power states +system.physmem_1.memoryStateTime::REF 4022980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21009739880 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971731 # Number of BP lookups -system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35971487 # Number of BP lookups +system.cpu.branchPred.condPredicted 19266966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984300 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17894295 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923321 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 77.808715 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6951891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2517210 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43855 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128902 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,131 +391,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 223507108 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 240960918 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1989645 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 12852393 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309387545 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35971487 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348567 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 224289895 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1990323 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1871 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 2666 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82203342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 33398 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 222582301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.671920 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.267628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3026 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82204082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34266 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 238142439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.562665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.293284 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62373241 28.02% 28.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40203334 18.06% 46.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28080746 12.62% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91924980 41.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77933727 32.73% 32.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40203358 16.88% 49.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28082672 11.79% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91922682 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 222582301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160942 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.384215 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26238985 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73050782 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98117127 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24314460 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 860947 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134221 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348541423 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3410145 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 860947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42548430 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 23450678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 285531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105165670 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50271045 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344601348 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1453656 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7084396 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85832 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7483674 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 23725025 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3279176 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394880845 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218133140 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335914250 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192916662 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22650794 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11588 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11554 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57533645 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89989968 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84391268 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1975718 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1902358 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343283622 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22608 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339469619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 966789 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15494628 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37288530 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 488 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 222582301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.525142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.109331 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 238142439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.149283 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.283974 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 26809492 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 87975457 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 98235303 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 24260898 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 861289 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6686645 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134215 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348536073 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3411178 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 861289 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43087679 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34729777 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 287359 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 105264108 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53912227 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344595535 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1451317 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7117459 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 85486 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7456793 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27429966 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3277218 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394867605 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2218081796 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335910446 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192911530 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22637557 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11573 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57394706 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89984018 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84392471 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1976841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1898355 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343274386 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22623 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339465004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 967637 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15485409 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 37250778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 238142439 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.425470 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.136916 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 42440680 19.07% 19.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76122495 34.20% 53.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59389973 26.68% 79.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34692267 15.59% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9226095 4.15% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 678749 0.30% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 32042 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 57979720 24.35% 24.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76155774 31.98% 56.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59457503 24.97% 81.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34550396 14.51% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9286722 3.90% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 677796 0.28% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34528 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 222582301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 238142439 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9228112 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7358 0.01% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 237798 0.20% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 147681 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70485 0.06% 8.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 67886 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 638269 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297789 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 542439 0.46% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51542568 43.28% 52.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56315471 47.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9217758 7.75% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7319 0.01% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 238781 0.20% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 138932 0.12% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 70694 0.06% 8.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68373 0.06% 8.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 637081 0.54% 8.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 296736 0.25% 8.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 541785 0.46% 9.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51510154 43.32% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56187310 47.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108184507 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148145 0.63% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108183295 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148337 0.63% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued @@ -534,103 +534,103 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792731 2.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6792696 2.00% 34.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8635726 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210403 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592905 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20864008 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7178651 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141492 2.10% 48.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175295 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90027492 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518264 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8634939 2.54% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3210556 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20863290 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7179112 2.11% 46.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141893 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 90024001 26.52% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 83518602 24.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339469619 # Type of FU issued -system.cpu.iq.rate 1.518831 # Inst issue rate -system.cpu.iq.fu_busy_cnt 119095856 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350829 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738018306 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235153924 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219171367 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283565878 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123658767 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116921576 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293614389 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164951086 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5389138 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339465004 # Type of FU issued +system.cpu.iq.rate 1.408797 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118914923 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.350301 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 753593457 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235149136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219170609 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283361550 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123645361 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116917491 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 293630516 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 164749411 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5409371 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4257693 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7295 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2015651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4251743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7382 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2016854 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126905 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613909 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 126951 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 613385 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 860947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1344821 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 736472 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343307622 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 861289 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1346418 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1223561 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343298428 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89989968 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84391268 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11575 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7371 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 729404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437891 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454375 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337441545 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89439870 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2028074 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89984018 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84392471 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7654 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1216581 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 438027 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454511 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337435973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89435470 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2029031 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1392 # number of nop insts executed -system.cpu.iew.exec_refs 172567373 # number of memory reference insts executed -system.cpu.iew.exec_branches 31555849 # Number of branches executed -system.cpu.iew.exec_stores 83127503 # Number of stores executed -system.cpu.iew.exec_rate 1.509758 # Inst execution rate -system.cpu.iew.wb_sent 336239137 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336092943 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151867680 # num instructions producing a value -system.cpu.iew.wb_consumers 263704827 # num instructions consuming a value -system.cpu.iew.wb_rate 1.503724 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575900 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14172678 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1419 # number of nop insts executed +system.cpu.iew.exec_refs 172563167 # number of memory reference insts executed +system.cpu.iew.exec_branches 31555788 # Number of branches executed +system.cpu.iew.exec_stores 83127697 # Number of stores executed +system.cpu.iew.exec_rate 1.400376 # Inst execution rate +system.cpu.iew.wb_sent 336234414 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336088100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151781597 # num instructions producing a value +system.cpu.iew.wb_consumers 263546089 # num instructions consuming a value +system.cpu.iew.wb_rate 1.394783 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575921 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14163176 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 220392023 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.487405 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.078236 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850428 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 235953046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.389311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.042233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 89247998 40.50% 40.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67546822 30.65% 71.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20918501 9.49% 80.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13253983 6.01% 86.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8642695 3.92% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4496391 2.04% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3033426 1.38% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2604506 1.18% 95.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10647701 4.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 104793604 44.41% 44.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 67594704 28.65% 73.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20883417 8.85% 81.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13239055 5.61% 87.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8655759 3.67% 91.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4517031 1.91% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3019754 1.28% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2590982 1.10% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10658740 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 220392023 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037832 # Number of instructions committed -system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 235953046 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037830 # Number of instructions committed +system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168107892 # Number of memory references committed system.cpu.commit.loads 85732275 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563526 # Number of branches committed +system.cpu.commit.branches 30563525 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. +system.cpu.commit.int_insts 258331703 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction @@ -663,157 +663,157 @@ system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Cl system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10647701 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 551726691 # The number of ROB reads -system.cpu.rob.rob_writes 686162246 # The number of ROB writes -system.cpu.timesIdled 18335 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 924807 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273037220 # Number of Instructions Simulated -system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.818596 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.818596 # CPI: Total CPI of All Threads -system.cpu.ipc 1.221604 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.221604 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325161919 # number of integer regfile reads -system.cpu.int_regfile_writes 134094717 # number of integer regfile writes -system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads -system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads -system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056766062 # number of misc regfile reads +system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction +system.cpu.commit.bw_lim_events 10658740 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 567267171 # The number of ROB reads +system.cpu.rob.rob_writes 686142351 # The number of ROB writes +system.cpu.timesIdled 39413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2818479 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037218 # Number of Instructions Simulated +system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.882520 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882520 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133118 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133118 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325162337 # number of integer regfile reads +system.cpu.int_regfile_writes 134093699 # number of integer regfile writes +system.cpu.fp_regfile_reads 186638060 # number of floating regfile reads +system.cpu.fp_regfile_writes 131662989 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279404689 # number of cc regfile reads +system.cpu.cc_regfile_writes 80058303 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056730531 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542955 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542807 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.846983 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 162052499 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543319 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 105.002594 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 87321000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.846983 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999701 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999701 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 333478959 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333478959 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 81039652 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81039652 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921351 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921351 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69633 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69633 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161985266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161985266 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162054877 # number of overall hits -system.cpu.dcache.overall_hits::total 162054877 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2782957 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2782957 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1132669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1132669 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161961003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161961003 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 162030636 # number of overall hits +system.cpu.dcache.overall_hits::total 162030636 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784011 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784011 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131348 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131348 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915644 # number of overall misses -system.cpu.dcache.overall_misses::total 3915644 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31092984500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31092984500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9127104911 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9127104911 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40220089411 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40220089411 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40220089411 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40220089411 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83848193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83848193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3915359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3915359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3915377 # number of overall misses +system.cpu.dcache.overall_misses::total 3915377 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45256653500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45256653500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9138834402 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9138834402 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54395487902 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54395487902 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54395487902 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54395487902 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83823663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83823663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69629 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69629 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165900892 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165900892 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165970521 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165970521 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033190 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033190 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013804 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013804 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000259 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000259 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165876362 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165876362 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165946013 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165946013 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8058.051303 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8058.051303 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10271.688208 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8077.827867 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8077.827867 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 46000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 46000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13892.848115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13892.784246 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1086145 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136219 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks -system.cpu.dcache.writebacks::total 1542955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 7.973521 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542807 # number of writebacks +system.cpu.dcache.writebacks::total 1542807 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461430 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1461430 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910604 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910604 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2372156 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2372156 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2372156 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2372156 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322721 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220749 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220749 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2372034 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2372034 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2372034 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2372034 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1543470 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1543470 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1543481 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1543481 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15298451500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15298451500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1831859691 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1831859691 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 695500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 695500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17130311191 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17130311191 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17131006691 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17131006691 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015775 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015775 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1543325 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1543325 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1543336 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1543336 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25407816000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25407816000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1834277181 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1834277181 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 705000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 705000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27242093181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27242093181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses @@ -822,392 +822,396 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 726201 # number of replacements -system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8309.522257 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8309.522257 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 725593 # number of replacements +system.cpu.icache.tags.tagsinuse 511.815316 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81471161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726105 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.203002 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 334835500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.815316 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999639 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999639 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits -system.cpu.icache.overall_hits::total 81470529 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 732796 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 732796 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 732796 # number of overall misses -system.cpu.icache.overall_misses::total 732796 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 6565806949 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 6565806949 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 6565806949 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 6565806949 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 6565806949 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 6565806949 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82203325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82203325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82203325 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82203325 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82203325 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82203325 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8959.938303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8959.938303 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8959.938303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165134244 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165134244 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81471161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81471161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81471161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81471161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81471161 # number of overall hits +system.cpu.icache.overall_hits::total 81471161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 732901 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 732901 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 732901 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 732901 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 732901 # number of overall misses +system.cpu.icache.overall_misses::total 732901 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8031652441 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8031652441 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8031652441 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8031652441 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8031652441 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8031652441 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82204062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82204062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82204062 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82204062 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82204062 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82204062 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008916 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008916 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008916 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008916 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008916 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008916 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10958.713989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10958.713989 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 128534 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4274 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 726201 # number of writebacks -system.cpu.icache.writebacks::total 726201 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726725 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726725 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726725 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726725 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726725 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726725 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6109081458 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6109081458 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6109081458 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6109081458 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6109081458 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6109081458 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008841 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008841 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.073467 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 725593 # number of writebacks +system.cpu.icache.writebacks::total 725593 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6780 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 6780 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 6780 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 6780 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 6780 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 6780 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726121 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726121 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726121 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726121 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726121 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726121 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7527879949 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7527879949 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7527879949 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7527879949 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 402848 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 402975 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 113 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 27937 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5253.562311 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1811987 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6314 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 286.979252 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # 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number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 187753381 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 251000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 251000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2084473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2084473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14900259000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14900259000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2084473500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14953574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17038047500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2084473500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14953574000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17225800881 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.928571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.928571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013343 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054095 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054095 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.036112 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172520 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172520 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113878 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058865 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3448.748330 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322722 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6809489 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92982208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134350 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5056 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137742 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4537857 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268434 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51535 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51534 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2048700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177753 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6807232 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197512064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290416512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55606 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2324982 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131629 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2019600 83.99% 83.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 307525 12.79% 96.78% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 77352 3.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018948 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306033 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 83887 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13 # Transaction distribution -system.membus.trans_dist::ReadExReq 730 # Transaction distribution -system.membus.trans_dist::ReadExResp 730 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 2324982 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537328500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089458442 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2315007958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 261068 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253748 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260294 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 757 # Transaction distribution +system.membus.trans_dist::ReadExResp 757 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522119 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16707264 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 84630 # Request fanout histogram +system.membus.snoop_fanout::samples 261068 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 84630 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261068 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 84630 # Request fanout histogram -system.membus.reqLayer0.occupancy 108151910 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 445724357 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 261068 # Request fanout histogram +system.membus.reqLayer0.occupancy 329929457 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1377865586 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index e42324626..ec456bd8f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 732440 # Simulator instruction rate (inst/s) -host_op_rate 879375 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 541118678 # Simulator tick rate (ticks/s) -host_mem_usage 263976 # Number of bytes of host memory used -host_seconds 372.78 # Real time elapsed on the host +host_inst_rate 781022 # Simulator instruction rate (inst/s) +host_op_rate 937704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 577011080 # Simulator tick rate (ticks/s) +host_mem_usage 268872 # Number of bytes of host memory used +host_seconds 349.59 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 434895828 # Transaction distribution system.membus.trans_dist::ReadResp 434906723 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 2275398075 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 517024352 # Request fanout histogram -system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 517024352 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 517024352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index fd046e3e7..81799693e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517291 # Number of seconds simulated -sim_ticks 517291025500 # Number of ticks simulated -final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517298 # Number of seconds simulated +sim_ticks 517297855500 # Number of ticks simulated +final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 451771 # Simulator instruction rate (inst/s) -host_op_rate 542368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 856851233 # Simulator tick rate (ticks/s) -host_mem_usage 273716 # Number of bytes of host memory used -host_seconds 603.71 # Real time elapsed on the host +host_inst_rate 565388 # Simulator instruction rate (inst/s) +host_op_rate 678769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1072356714 # Simulator tick rate (ticks/s) +host_mem_usage 278352 # Number of bytes of host memory used +host_seconds 482.39 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory system.physmem.bytes_read::total 437248 # Number of bytes read from this memory @@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 166912 # Nu system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1034582051 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1034595711 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -214,16 +214,16 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.320204 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751543 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id @@ -233,7 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -258,14 +258,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89418000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 269696500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 269696500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -290,14 +290,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60253.909741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 87767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 177406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 186000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265173500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 265173500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 265359500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -342,26 +342,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1765.939670 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862275 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862275 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id @@ -371,7 +371,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits @@ -384,12 +384,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 341054000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 341054000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 341054000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -402,12 +402,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21858.232391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21858.232391 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,48 +422,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5901.352793 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.031616 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.180095 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits @@ -492,18 +490,18 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 255885500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 413785500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 255885500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 413785500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) @@ -532,18 +530,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -562,18 +560,18 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses @@ -586,25 +584,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution @@ -638,7 +636,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 6833 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index f21f0115d..cfec5db38 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.508216 # Number of seconds simulated -sim_ticks 508215534000 # Number of ticks simulated -final_tick 508215534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.508441 # Number of seconds simulated +sim_ticks 508441445000 # Number of ticks simulated +final_tick 508441445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 266071 # Simulator instruction rate (inst/s) -host_op_rate 266071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145588775 # Simulator tick rate (ticks/s) -host_mem_usage 258712 # Number of bytes of host memory used -host_seconds 3490.76 # Real time elapsed on the host +host_inst_rate 272638 # Simulator instruction rate (inst/s) +host_op_rate 272638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149248503 # Simulator tick rate (ticks/s) +host_mem_usage 263860 # Number of bytes of host memory used +host_seconds 3406.68 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520192 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185920 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 185856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory +system.physmem.bytes_read::total 18706752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 185856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 185856 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289378 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292293 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 365829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36441609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36807438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 365829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 365829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8397445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8397445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8397445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 365829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36441609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 45204883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292283 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 365541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36426802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36792343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 365541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 365541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8393714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8393714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8393714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 365541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36426802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 45186057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292293 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292283 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292293 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18687040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706112 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18685888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18706752 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18032 # Per bank write bursts -system.physmem.perBankRdBursts::1 18362 # Per bank write bursts -system.physmem.perBankRdBursts::2 18398 # Per bank write bursts -system.physmem.perBankRdBursts::3 18335 # Per bank write bursts -system.physmem.perBankRdBursts::4 18250 # Per bank write bursts -system.physmem.perBankRdBursts::5 18255 # Per bank write bursts -system.physmem.perBankRdBursts::6 18321 # Per bank write bursts -system.physmem.perBankRdBursts::7 18295 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18236 # Per bank write bursts -system.physmem.perBankRdBursts::10 18232 # Per bank write bursts -system.physmem.perBankRdBursts::11 18379 # Per bank write bursts -system.physmem.perBankRdBursts::12 18271 # Per bank write bursts -system.physmem.perBankRdBursts::13 18134 # Per bank write bursts -system.physmem.perBankRdBursts::14 18060 # Per bank write bursts -system.physmem.perBankRdBursts::15 18193 # Per bank write bursts +system.physmem.perBankRdBursts::0 18028 # Per bank write bursts +system.physmem.perBankRdBursts::1 18361 # Per bank write bursts +system.physmem.perBankRdBursts::2 18399 # Per bank write bursts +system.physmem.perBankRdBursts::3 18347 # Per bank write bursts +system.physmem.perBankRdBursts::4 18249 # Per bank write bursts +system.physmem.perBankRdBursts::5 18247 # Per bank write bursts +system.physmem.perBankRdBursts::6 18319 # Per bank write bursts +system.physmem.perBankRdBursts::7 18291 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts +system.physmem.perBankRdBursts::9 18239 # Per bank write bursts +system.physmem.perBankRdBursts::10 18229 # Per bank write bursts +system.physmem.perBankRdBursts::11 18377 # Per bank write bursts +system.physmem.perBankRdBursts::12 18268 # Per bank write bursts +system.physmem.perBankRdBursts::13 18136 # Per bank write bursts +system.physmem.perBankRdBursts::14 18057 # Per bank write bursts +system.physmem.perBankRdBursts::15 18190 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts +system.physmem.perBankWrBursts::9 4188 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 508215452500 # Total gap between requests +system.physmem.totGap 508441362500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292283 # Read request sizes (log2) +system.physmem.readPktSize::6 292293 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 464 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,25 +145,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -194,97 +194,97 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 221.521925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.541969 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.372247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37864 36.55% 36.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43808 42.28% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9097 8.78% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 745 0.72% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1395 1.35% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1153 1.11% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 627 0.61% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 610 0.59% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8304 8.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103603 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.361324 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.573478 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 739.455375 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 103424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 221.899134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.895688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.440022 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37597 36.35% 36.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43798 42.35% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9078 8.78% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 804 0.78% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1585 1.53% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1026 0.99% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 543 0.53% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 660 0.64% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8333 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103424 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.164816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.696519 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 767.230213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.462336 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.441628 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.843264 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 936 23.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads -system.physmem.totQLat 2518388500 # Total ticks spent queuing -system.physmem.totMemAccLat 7993107250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8625.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.448063 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.427763 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.835172 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3146 77.62% 77.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 906 22.35% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads +system.physmem.totQLat 2452616250 # Total ticks spent queuing +system.physmem.totMemAccLat 7926997500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8400.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27375.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27150.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 8.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.40 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 203026 # Number of row buffer hits during reads -system.physmem.writeRowHits 52001 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes -system.physmem.avgGap 1415776.01 # Average gap between requests -system.physmem.pageHitRate 71.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 390708360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 213184125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140250800 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing +system.physmem.readRowHits 203097 # Number of row buffer hits during reads +system.physmem.writeRowHits 52099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 1416365.89 # Average gap between requests +system.physmem.pageHitRate 71.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 390353040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 212990250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140196200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103572972045 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214071794250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 352799059260 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.201008 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 355459552750 # Time in different power states -system.physmem_0.memoryStateTime::REF 16970200000 # Time in different power states +system.physmem_0.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 103170345705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 214560479250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 352899262365 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.089734 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 356274409500 # Time in different power states +system.physmem_0.memoryStateTime::REF 16977740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 135779058500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 135182501000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 392424480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 214120500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136545800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103467236760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 214164544500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 352784075640 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.171524 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 355611467750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16970200000 # Time in different power states +system.physmem_1.actEnergy 391426560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 213576000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136460000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 103438175310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 214325517750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 352929159300 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.148589 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 355878371250 # Time in different power states +system.physmem_1.memoryStateTime::REF 16977740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135627775750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 135579179250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851653 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 123851654 # Number of BP lookups system.cpu.branchPred.condPredicted 79872946 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 686743 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066131 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190141 # Number of BTB hits +system.cpu.branchPred.BTBLookups 102066133 # Number of BTB lookups +system.cpu.branchPred.BTBHits 68190143 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 66.809764 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697400 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 18697398 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 11224 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 14052177 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 14048616 # Number of indirect target hits. @@ -299,18 +299,18 @@ system.cpu.dtb.read_hits 237539296 # DT system.cpu.dtb.read_misses 195211 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305020 # DTB write hits +system.cpu.dtb.write_hits 98305021 # DTB write hits system.cpu.dtb.write_misses 7170 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312190 # DTB write accesses -system.cpu.dtb.data_hits 335844316 # DTB hits +system.cpu.dtb.write_accesses 98312191 # DTB write accesses +system.cpu.dtb.data_hits 335844317 # DTB hits system.cpu.dtb.data_misses 202381 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046697 # DTB accesses -system.cpu.itb.fetch_hits 286584409 # ITB hits +system.cpu.dtb.data_accesses 336046698 # DTB accesses +system.cpu.itb.fetch_hits 286584411 # ITB hits system.cpu.itb.fetch_misses 119 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584528 # ITB accesses +system.cpu.itb.fetch_accesses 286584530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,16 +324,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1016431068 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1016882890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319592 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 319599 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.094361 # CPI: cycles per instruction -system.cpu.ipc 0.913775 # IPC: instructions per cycle +system.cpu.cpi 1.094848 # CPI: cycles per instruction +system.cpu.ipc 0.913369 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction @@ -369,36 +369,36 @@ system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962815750 # Number of cycles that the object actually ticked -system.cpu.idleCycles 53615318 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 962815783 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54067107 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.348104 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318733 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.323693 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320318732 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320478 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 905242500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.348104 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999108 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999108 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 410.320477 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 911974500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.323693 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999102 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999102 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 955 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1491 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115729 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115729 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154684 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 643115727 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 643115727 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 222154683 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 222154683 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98164049 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 98164049 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318733 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318733 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318733 # number of overall hits -system.cpu.dcache.overall_hits::total 320318733 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 320318732 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320318732 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320318732 # number of overall hits +system.cpu.dcache.overall_hits::total 320318732 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137151 # number of WriteReq misses @@ -407,22 +407,22 @@ system.cpu.dcache.demand_misses::cpu.data 848804 # n system.cpu.dcache.demand_misses::total 848804 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 848804 # number of overall misses system.cpu.dcache.overall_misses::total 848804 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24412597000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24412597000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105115500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105115500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34517712500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34517712500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34517712500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34517712500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866337 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866337 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24607511500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24607511500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10163393500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10163393500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34770905000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34770905000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34770905000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34770905000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 222866336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 222866336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167537 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167537 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 321167536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 321167536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 321167536 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 321167536 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -431,22 +431,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34304.073755 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34304.073755 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73678.759178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73678.759178 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40666.293396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40666.293396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40666.293396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40666.293396 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34577.963558 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34577.963558 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74103.677698 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74103.677698 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40964.586642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40964.586642 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88481 # number of writebacks -system.cpu.dcache.writebacks::total 88481 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks +system.cpu.dcache.writebacks::total 88440 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68140 # number of WriteReq MSHR hits @@ -463,14 +463,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780655 system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23700262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23700262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5068010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5068010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28768272500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28768272500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28768272500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28768272500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23895183000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23895183000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5097981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5097981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28993164500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28993164500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993164500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28993164500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -479,24 +479,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33303.537302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33303.537302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73437.712828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73437.712828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36851.454868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36851.454868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36851.454868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36851.454868 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10580 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.197843 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572082 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12326 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23249.398183 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33577.439000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33577.439000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73872.013157 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73872.013157 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 10578 # number of replacements +system.cpu.icache.tags.tagsinuse 1690.178313 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 286572086 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12324 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23253.171535 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1690.197843 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825292 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825292 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1690.178313 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.825282 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.825282 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id @@ -504,181 +504,181 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181144 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181144 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572082 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572082 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572082 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286572082 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286572082 # number of overall hits -system.cpu.icache.overall_hits::total 286572082 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12327 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12327 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12327 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12327 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12327 # number of overall misses -system.cpu.icache.overall_misses::total 12327 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 353123500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 353123500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 353123500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 353123500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 353123500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 353123500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286584409 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286584409 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286584409 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286584409 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286584409 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286584409 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 573181146 # Number of tag accesses +system.cpu.icache.tags.data_accesses 573181146 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 286572086 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 286572086 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 286572086 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 286572086 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 286572086 # number of overall hits +system.cpu.icache.overall_hits::total 286572086 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12325 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12325 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12325 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12325 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12325 # number of overall misses +system.cpu.icache.overall_misses::total 12325 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354631500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354631500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354631500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354631500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354631500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354631500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 286584411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 286584411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 286584411 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 286584411 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 286584411 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 286584411 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28646.345421 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28773.346856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28773.346856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28773.346856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28773.346856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28773.346856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28773.346856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12325 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792982 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792980 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235743 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368602 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235700 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368602 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74568.159652 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74568.159652 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77422.203098 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77422.203098 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79437.632439 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79437.632439 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78307.329264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78307.329264 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,120 +691,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2906 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2906 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222733 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222733 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2906 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289378 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292284 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2906 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289378 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292284 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4273173000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4273173000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 194338000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 194338000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15271890000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15271890000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 194338000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19545063000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19739401000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 194338000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19545063000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19739401000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2905 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2905 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2905 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292294 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2905 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292294 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4303145000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4303145000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15466816000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15466816000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195871500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19769961000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19965832500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195871500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19769961000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19965832500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370686 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368588 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370686 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368588 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64118.433491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64118.433491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66874.741913 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66874.741913 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68565.906264 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68565.906264 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66874.741913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67541.634126 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67535.003627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66874.741913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67541.634126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67535.003627 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580121 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787139 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368602 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368602 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64568.159652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64568.159652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67425.645439 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67425.645439 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69437.632439 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69437.632439 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1580117 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787137 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2087 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2087 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2095 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10580 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881355 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 723968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881417 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12325 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35227 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55624704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57090688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259960 # Total snoops (count) +system.cpu.toL2Bus.pkt_count::total 2373096 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259981 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001982 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044476 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1052961 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001990 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044561 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050855 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2087 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050866 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2095 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052942 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889121500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052961 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889076500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18489000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18486000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170982999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225638 # Transaction distribution +system.membus.snoop_filter.tot_requests 550179 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257886 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225648 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191190 # Transaction distribution +system.membus.trans_dist::CleanEvict 191203 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225638 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842439 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22973824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22973824 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842472 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22974464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 550156 # Request fanout histogram +system.membus.snoop_fanout::samples 292293 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 550156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292293 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 550156 # Request fanout histogram -system.membus.reqLayer0.occupancy 925402000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292293 # Request fanout histogram +system.membus.reqLayer0.occupancy 925378500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556718500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556878500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 577d97331..c74410070 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.174766 # Number of seconds simulated -sim_ticks 174766258500 # Number of ticks simulated -final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.175004 # Number of seconds simulated +sim_ticks 175004412500 # Number of ticks simulated +final_tick 175004412500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215097 # Simulator instruction rate (inst/s) -host_op_rate 215097 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44625570 # Simulator tick rate (ticks/s) -host_mem_usage 260248 # Number of bytes of host memory used -host_seconds 3916.28 # Real time elapsed on the host +host_inst_rate 244500 # Simulator instruction rate (inst/s) +host_op_rate 244500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50794673 # Simulator tick rate (ticks/s) +host_mem_usage 265392 # Number of bytes of host memory used +host_seconds 3445.33 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory -system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 174016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 174016 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18525120 # Number of bytes read from this memory +system.physmem.bytes_read::total 18699072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2719 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292173 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 995707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 105996479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106992186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 995707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 995707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24419176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24419176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24419176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 995707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 105996479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 131411362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292166 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 993986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 105855160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106849146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 993986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 993986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24385945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24385945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24385945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 993986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 105855160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 131235091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292173 # Number of read requests accepted system.physmem.writeReqs 66682 # Number of write requests accepted -system.physmem.readBursts 292166 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292173 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18677824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265792 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18698624 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18679488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18699072 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18006 # Per bank write bursts -system.physmem.perBankRdBursts::1 18334 # Per bank write bursts -system.physmem.perBankRdBursts::2 18382 # Per bank write bursts -system.physmem.perBankRdBursts::3 18340 # Per bank write bursts -system.physmem.perBankRdBursts::4 18235 # Per bank write bursts -system.physmem.perBankRdBursts::5 18233 # Per bank write bursts -system.physmem.perBankRdBursts::6 18311 # Per bank write bursts -system.physmem.perBankRdBursts::7 18302 # Per bank write bursts -system.physmem.perBankRdBursts::8 18233 # Per bank write bursts -system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::0 18012 # Per bank write bursts +system.physmem.perBankRdBursts::1 18337 # Per bank write bursts +system.physmem.perBankRdBursts::2 18383 # Per bank write bursts +system.physmem.perBankRdBursts::3 18348 # Per bank write bursts +system.physmem.perBankRdBursts::4 18239 # Per bank write bursts +system.physmem.perBankRdBursts::5 18237 # Per bank write bursts +system.physmem.perBankRdBursts::6 18320 # Per bank write bursts +system.physmem.perBankRdBursts::7 18308 # Per bank write bursts +system.physmem.perBankRdBursts::8 18229 # Per bank write bursts +system.physmem.perBankRdBursts::9 18225 # Per bank write bursts system.physmem.perBankRdBursts::10 18220 # Per bank write bursts -system.physmem.perBankRdBursts::11 18388 # Per bank write bursts -system.physmem.perBankRdBursts::12 18256 # Per bank write bursts -system.physmem.perBankRdBursts::13 18125 # Per bank write bursts -system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18192 # Per bank write bursts +system.physmem.perBankRdBursts::11 18382 # Per bank write bursts +system.physmem.perBankRdBursts::12 18250 # Per bank write bursts +system.physmem.perBankRdBursts::13 18123 # Per bank write bursts +system.physmem.perBankRdBursts::14 18058 # Per bank write bursts +system.physmem.perBankRdBursts::15 18196 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,8 +74,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4261 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts -system.physmem.perBankWrBursts::10 4148 # Per bank write bursts +system.physmem.perBankWrBursts::9 4191 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 174766169000 # Total gap between requests +system.physmem.totGap 175004322000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292166 # Read request sizes (log2) +system.physmem.readPktSize::6 292173 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,12 +98,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -146,24 +146,24 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4144 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -194,125 +194,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.414911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.615169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 282.362382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 31544 32.64% 32.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41851 43.31% 75.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11279 11.67% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 407 0.42% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 349 0.36% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 422 0.44% 88.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 656 0.68% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1511 1.56% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8609 8.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96628 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.731557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.520071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 729.773377 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 96708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.268147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.455294 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 282.430006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31632 32.71% 32.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41779 43.20% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11320 11.71% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 443 0.46% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 357 0.37% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 304 0.31% 88.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 669 0.69% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1569 1.62% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8635 8.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96708 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.658609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.711074 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 765.890247 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.78% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.445349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.425120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.833815 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3151 77.74% 77.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 77.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 896 22.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads -system.physmem.totQLat 3659606000 # Total ticks spent queuing -system.physmem.totMemAccLat 9131624750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12539.73 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.444499 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.424176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.836057 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3157 77.87% 77.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 892 22.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads +system.physmem.totQLat 3688779750 # Total ticks spent queuing +system.physmem.totMemAccLat 9161286000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12638.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31289.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 24.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 24.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31388.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 24.38 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 24.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.03 # Data bus utilization in percentage +system.physmem.busUtil 1.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.19 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 209802 # Number of row buffer hits during reads -system.physmem.writeRowHits 52054 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes -system.physmem.avgGap 487020.04 # Average gap between requests -system.physmem.pageHitRate 73.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 364626360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 198952875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139346000 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 209722 # Number of row buffer hits during reads +system.physmem.writeRowHits 52099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 487674.19 # Average gap between requests +system.physmem.pageHitRate 73.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 365095080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 199208625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140180600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63677219400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 49000374750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 126011580585 # Total energy per rank (pJ) -system.physmem_0.averagePower 721.044153 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81102514500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5835700000 # Time in different power states +system.physmem_0.refreshEnergy 11430394560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63710720865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 49115814750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 126177846480 # Total energy per rank (pJ) +system.physmem_0.averagePower 720.999703 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81290875500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5843760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87824440500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87869398250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 365752800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 199567500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136265000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215479440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 63630052470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49041749250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 126003495660 # Total energy per rank (pJ) -system.physmem_1.averagePower 720.997890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81165303250 # Time in different power states -system.physmem_1.memoryStateTime::REF 5835700000 # Time in different power states +system.physmem_1.actEnergy 366002280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 199703625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136311800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215563680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 11430394560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64026816075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48838535250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 126213327270 # Total energy per rank (pJ) +system.physmem_1.averagePower 721.202467 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 80826473000 # Time in different power states +system.physmem_1.memoryStateTime::REF 5843760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 88334018000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 129267026 # Number of BP lookups -system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93510959 # Number of BTB lookups -system.cpu.branchPred.BTBHits 70602364 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 129267773 # Number of BP lookups +system.cpu.branchPred.condPredicted 83048997 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 145228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93512308 # Number of BTB lookups +system.cpu.branchPred.BTBHits 70602709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 75.501700 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19428078 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1137 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14846480 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14819636 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 26844 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 75.500980 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19428222 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1139 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14846516 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14819690 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 26826 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4927 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 243602185 # DTB read hits -system.cpu.dtb.read_misses 267667 # DTB read misses +system.cpu.dtb.read_hits 243602594 # DTB read hits +system.cpu.dtb.read_misses 267810 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 243869852 # DTB read accesses -system.cpu.dtb.write_hits 101634527 # DTB write hits -system.cpu.dtb.write_misses 39608 # DTB write misses +system.cpu.dtb.read_accesses 243870404 # DTB read accesses +system.cpu.dtb.write_hits 101634629 # DTB write hits +system.cpu.dtb.write_misses 39603 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 101674135 # DTB write accesses -system.cpu.dtb.data_hits 345236712 # DTB hits -system.cpu.dtb.data_misses 307275 # DTB misses +system.cpu.dtb.write_accesses 101674232 # DTB write accesses +system.cpu.dtb.data_hits 345237223 # DTB hits +system.cpu.dtb.data_misses 307413 # DTB misses system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 345543987 # DTB accesses -system.cpu.itb.fetch_hits 116217608 # ITB hits -system.cpu.itb.fetch_misses 1594 # ITB misses +system.cpu.dtb.data_accesses 345544636 # DTB accesses +system.cpu.itb.fetch_hits 116218491 # ITB hits +system.cpu.itb.fetch_misses 1583 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 116219202 # ITB accesses +system.cpu.itb.fetch_accesses 116220074 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,138 +327,138 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 349532518 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 350008826 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 116536228 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973715519 # Number of instructions fetch has processed -system.cpu.fetch.Branches 129267026 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 104850078 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 232359516 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 756618 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13025 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 116537595 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 973721565 # Number of instructions fetch has processed +system.cpu.fetch.Branches 129267773 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 104850621 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 232833162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 756818 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12983 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 116217608 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 170932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 349287938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.787716 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.090069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 116218491 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 171000 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 349762998 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.783947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.089679 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 152570668 43.68% 43.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 21852908 6.26% 49.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15618674 4.47% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24569577 7.03% 61.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 38589117 11.05% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15690770 4.49% 76.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 12536709 3.59% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3990160 1.14% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63869355 18.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 153044218 43.76% 43.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 21853200 6.25% 50.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15619262 4.47% 54.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24569789 7.02% 61.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 38589030 11.03% 72.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15690779 4.49% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12536762 3.58% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3989777 1.14% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 63870181 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 349287938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369828 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.785765 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85729217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 85771889 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158922951 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18492364 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371517 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11932000 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7014 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 968678626 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25475 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371517 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93246352 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12124008 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14162 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 169252951 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 74278948 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 966798475 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 812 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25198716 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40147884 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7202949 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 666569389 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1151537527 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114498375 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 37039151 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 349762998 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369327 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.781991 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85730052 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86245168 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158924333 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18491829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 371616 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11931982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7013 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 968682189 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25467 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 371616 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93247100 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12146615 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14284 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 169253997 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 74729386 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 966801753 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1559 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25162616 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40511587 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7290496 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 666571567 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1151541399 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114502328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 37039070 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27602231 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 87958062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 245057270 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 102624029 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35348443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4751860 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 877942600 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 76 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 871652294 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 10599 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35560646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10943510 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 349287938 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.495512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.135180 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27604409 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1367 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 87953522 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 245057905 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 102624371 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35358842 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4732178 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 877945283 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 77 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 871653931 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 10631 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35563330 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10945081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 349762998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.492127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.135671 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75519507 21.62% 21.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 61352705 17.57% 39.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 57497159 16.46% 55.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51075272 14.62% 70.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45041028 12.90% 83.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20641156 5.91% 89.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18147367 5.20% 94.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10284591 2.94% 97.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9729153 2.79% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75990310 21.73% 21.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 61353138 17.54% 39.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 57501132 16.44% 55.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51071612 14.60% 70.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45054201 12.88% 83.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20633149 5.90% 89.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18143842 5.19% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10286820 2.94% 97.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9728794 2.78% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 349287938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 349762998 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3589516 19.40% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11788826 63.72% 83.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3123532 16.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3589530 19.39% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11797020 63.73% 83.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3124042 16.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 505111201 57.95% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 505112247 57.95% 57.95% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7850 0.00% 57.95% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13300877 1.53% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826560 0.44% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339807 0.38% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13300875 1.53% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826555 0.44% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued @@ -481,82 +482,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 244259904 28.02% 88.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 101804815 11.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 244260355 28.02% 88.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 101804963 11.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 871652294 # Type of FU issued -system.cpu.iq.rate 2.493766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18501874 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2041816444 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 876761594 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 835992532 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69288555 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36778587 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34169821 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855051836 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35101056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65597329 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 871653931 # Type of FU issued +system.cpu.iq.rate 2.490377 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18510592 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021236 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2042303381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 876767032 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 835994185 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 69288702 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36778589 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34169846 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 855062076 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35101171 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 65597395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7546673 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37094 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4322829 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7547308 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5161 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37165 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4323171 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2714 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4439 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4324 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371517 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4003286 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 617757 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 966013425 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 245057270 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 102624029 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 76 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 538427 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 92920 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37094 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128203 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 15937 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 144140 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 871030251 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 243869972 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 622043 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 371616 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4020858 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 620837 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 966016228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16689 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 245057905 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 102624371 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 77 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 538553 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 95932 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37165 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 128220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 15953 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 144173 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 871032011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 243870521 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 621920 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88070749 # number of nop insts executed -system.cpu.iew.exec_refs 345544428 # number of memory reference insts executed -system.cpu.iew.exec_branches 127159642 # Number of branches executed -system.cpu.iew.exec_stores 101674456 # Number of stores executed -system.cpu.iew.exec_rate 2.491986 # Inst execution rate -system.cpu.iew.wb_sent 870623887 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 870162353 # cumulative count of insts written-back -system.cpu.iew.wb_producers 525000957 # num instructions producing a value -system.cpu.iew.wb_consumers 821946847 # num instructions consuming a value -system.cpu.iew.wb_rate 2.489503 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.638729 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 31811556 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 88070868 # number of nop insts executed +system.cpu.iew.exec_refs 345545074 # number of memory reference insts executed +system.cpu.iew.exec_branches 127159833 # Number of branches executed +system.cpu.iew.exec_stores 101674553 # Number of stores executed +system.cpu.iew.exec_rate 2.488600 # Inst execution rate +system.cpu.iew.wb_sent 870625746 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 870164031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 525002727 # num instructions producing a value +system.cpu.iew.wb_consumers 821961915 # num instructions consuming a value +system.cpu.iew.wb_rate 2.486120 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.638719 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 31814193 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 138434 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 345159794 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.690312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.060061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 138436 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 345634386 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.686618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.059575 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 109423104 31.70% 31.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 81928646 23.74% 55.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 29947333 8.68% 64.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19779535 5.73% 69.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17819278 5.16% 75.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7961935 2.31% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3040960 0.88% 78.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3978860 1.15% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71280143 20.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109896722 31.80% 31.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 81929003 23.70% 55.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29947850 8.66% 64.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19779542 5.72% 69.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17820096 5.16% 75.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7961930 2.30% 77.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3040428 0.88% 78.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3978823 1.15% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71279992 20.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 345159794 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 345634386 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -602,127 +603,127 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 71280143 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1231657697 # The number of ROB reads -system.cpu.rob.rob_writes 1924928764 # The number of ROB writes -system.cpu.timesIdled 3152 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 244580 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 71279992 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1232135077 # The number of ROB reads +system.cpu.rob.rob_writes 1924934508 # The number of ROB writes +system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.414933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.414933 # CPI: Total CPI of All Threads -system.cpu.ipc 2.410025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.410025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1104176449 # number of integer regfile reads -system.cpu.int_regfile_writes 635594518 # number of integer regfile writes -system.cpu.fp_regfile_reads 36406853 # number of floating regfile reads -system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes +system.cpu.cpi 0.415499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.415499 # CPI: Total CPI of All Threads +system.cpu.ipc 2.406745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.406745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1104178752 # number of integer regfile reads +system.cpu.int_regfile_writes 635595888 # number of integer regfile writes +system.cpu.fp_regfile_reads 36406844 # number of floating regfile reads +system.cpu.fp_regfile_writes 24680552 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776668 # number of replacements -system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780764 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 350.748599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 371412500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4091.068449 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998796 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 776667 # number of replacements +system.cpu.dcache.tags.tagsinuse 4091.035125 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 273851714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780763 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 350.748837 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 374790500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4091.035125 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998788 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998788 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1013 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408623 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 553380005 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 553380005 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 176443372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176443372 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97408329 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97408329 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 273851866 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 273851866 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 273851866 # number of overall hits -system.cpu.dcache.overall_hits::total 273851866 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1554707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1554707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 892577 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 892577 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2447284 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2447284 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2447284 # number of overall misses -system.cpu.dcache.overall_misses::total 2447284 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83708553000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83708553000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61914869831 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61914869831 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145623422831 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145623422831 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145623422831 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145623422831 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177997950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177997950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 273851701 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 273851701 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 273851701 # number of overall hits +system.cpu.dcache.overall_hits::total 273851701 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1555036 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1555036 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 892871 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 892871 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2447907 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2447907 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2447907 # number of overall misses +system.cpu.dcache.overall_misses::total 2447907 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84877374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84877374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62367572330 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62367572330 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 147244946330 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 147244946330 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 147244946330 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 147244946330 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177998408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177998408 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 276299150 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 276299150 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 276299150 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 276299150 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008734 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009080 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009080 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59504.096309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59504.096309 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22333 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 68716 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.360231 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.400771 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88604 # number of writebacks -system.cpu.dcache.writebacks::total 88604 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842561 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 842561 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823959 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 823959 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1666520 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1666520 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1666520 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1666520 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712146 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712146 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68618 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68618 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780764 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780764 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780764 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780764 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24226479500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24226479500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5661245497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5661245497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29887724997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29887724997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29887724997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_accesses::cpu.data 276299608 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 276299608 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 276299608 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 276299608 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008736 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008736 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008860 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008860 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008860 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008860 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54582.256617 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54582.256617 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69850.596928 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69850.596928 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60151.364545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60151.364545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60151.364545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60151.364545 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24555 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 63758 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 349 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 520 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.358166 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 122.611538 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88567 # number of writebacks +system.cpu.dcache.writebacks::total 88567 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842892 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842892 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824252 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 824252 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1667144 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1667144 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1667144 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1667144 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712144 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712144 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68619 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68619 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780763 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780763 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780763 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780763 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24487996000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24487996000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5721430497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5721430497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30209426497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30209426497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30209426497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30209426497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses @@ -731,24 +732,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4617 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18381.739639 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34386.298277 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34386.298277 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83379.683426 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83379.683426 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38692.185077 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38692.185077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38692.185077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38692.185077 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 4616 # number of replacements +system.cpu.icache.tags.tagsinuse 1647.876124 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 116210243 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6321 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18384.787692 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.904441 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.876124 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804627 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804627 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id @@ -756,187 +757,187 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 1 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses -system.cpu.icache.tags.data_accesses 232441538 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -949,120 +950,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66625 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66625 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2720 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2720 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2720 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289447 # 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Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338196 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2355458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56339648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259794 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 718465 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712144 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338193 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2355452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55637120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56337088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259809 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1046881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001913 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1046894 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001918 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043754 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1044878 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2003 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1044886 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2008 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1046881 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877407000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1046894 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877367000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9481500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1171144500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225541 # Transaction distribution +system.membus.snoop_filter.tot_requests 549975 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257802 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225548 # Transaction distribution system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution -system.membus.trans_dist::CleanEvict 191110 # Transaction distribution +system.membus.trans_dist::CleanEvict 191120 # Transaction distribution system.membus.trans_dist::ReadExReq 66625 # Transaction distribution system.membus.trans_dist::ReadExResp 66625 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225541 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842124 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22966272 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225548 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842148 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22966720 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 549958 # Request fanout histogram +system.membus.snoop_fanout::samples 292173 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549958 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292173 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549958 # Request fanout histogram -system.membus.reqLayer0.occupancy 877671500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292173 # Request fanout histogram +system.membus.reqLayer0.occupancy 877549500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551270000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551106000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index b6b81e33b..efcf10ec9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2033284 # Simulator instruction rate (inst/s) -host_op_rate 2033284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1016862727 # Simulator tick rate (ticks/s) -host_mem_usage 248468 # Number of bytes of host memory used -host_seconds 456.69 # Real time elapsed on the host +host_inst_rate 1533629 # Simulator instruction rate (inst/s) +host_op_rate 1533629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 766980884 # Simulator tick rate (ticks/s) +host_mem_usage 251816 # Number of bytes of host memory used +host_seconds 605.48 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 6109961839 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram -system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1264600947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1264600947 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index f13a4ce2b..7031d8335 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.288319 # Number of seconds simulated -sim_ticks 1288319411500 # Number of ticks simulated -final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.288611 # Number of seconds simulated +sim_ticks 1288611150500 # Number of ticks simulated +final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112167 # Simulator instruction rate (inst/s) -host_op_rate 1112167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1543016447 # Simulator tick rate (ticks/s) -host_mem_usage 257436 # Number of bytes of host memory used -host_seconds 834.94 # Real time elapsed on the host +host_inst_rate 1122029 # Simulator instruction rate (inst/s) +host_op_rate 1122029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1557051854 # Simulator tick rate (ticks/s) +host_mem_usage 262324 # Number of bytes of host memory used +host_seconds 827.60 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory -system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18512320 # Number of bytes read from this memory +system.physmem.bytes_read::total 18649344 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289255 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291396 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 106335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14366103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14472437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3311870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3311870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3311870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14366103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17784307 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2576638823 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2577222301 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -92,7 +92,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2576638823 # Number of busy cycles +system.cpu.num_busy_cycles 2577222301 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -131,16 +131,16 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4094.168779 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1112572500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.168779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id @@ -150,7 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits @@ -167,14 +167,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20380048000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20380048000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4229584000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4229584000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24609632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24609632000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24609632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24609632000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) @@ -191,22 +191,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28643.214329 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28643.214329 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61285.884024 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61285.884024 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31529.467232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31529.467232 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks -system.cpu.dcache.writebacks::total 88866 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88841 # number of writebacks +system.cpu.dcache.writebacks::total 88841 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses @@ -215,14 +215,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528 system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19668534000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19668534000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4160570000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4160570000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23829104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23829104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23829104000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23829104000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -231,24 +231,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27643.214329 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27643.214329 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60285.884024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60285.884024 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.409268 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.409268 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719926 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id @@ -257,7 +257,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits @@ -270,12 +270,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 187267500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 187267500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 187267500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 187267500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 187267500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 187267500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -288,12 +288,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30361.138132 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30361.138132 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30361.138132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30361.138132 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,90 +308,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 181099500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 181099500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 181099500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 181099500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 181099500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 181099500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258847 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29361.138132 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29361.138132 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 258865 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32717.214949 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1276112 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291633 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.375746 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 4209362000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27.944200 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.856544 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32641.414205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000853 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001460 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.996137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998450 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31170 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12833601 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12833601 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88841 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88841 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488907 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488907 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491273 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 495300 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits -system.cpu.l2cache.overall_hits::total 495307 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491273 # number of overall hits +system.cpu.l2cache.overall_hits::total 495300 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222607 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222607 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289255 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291396 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses -system.cpu.l2cache.overall_misses::total 291389 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 289255 # number of overall misses +system.cpu.l2cache.overall_misses::total 291396 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4032205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4032205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 129556500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 129556500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13467735000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13467735000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 129556500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17499940000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17629496500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 129556500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17499940000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17629496500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88841 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88841 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) @@ -410,26 +410,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312864 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312864 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370405 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370405 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.051661 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.051661 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.132123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.132123 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,63 +444,63 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222607 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222607 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289255 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291396 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 289255 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291396 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3365725000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3365725000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 108146500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 108146500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11241665000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11241665000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108146500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14607390000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14715536500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108146500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14607390000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14715536500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312864 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312864 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370405 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370405 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.051661 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.051661 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1726 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1726 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155524 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 879773 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution @@ -509,53 +509,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258847 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56329920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258865 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1045561 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001651 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.040596 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1043835 99.83% 99.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1726 0.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1045561 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877332000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224741 # Transaction distribution +system.membus.snoop_filter.tot_requests 548536 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257140 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 224748 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190447 # Transaction distribution +system.membus.trans_dist::CleanEvict 190457 # Transaction distribution system.membus.trans_dist::ReadExReq 66648 # Transaction distribution system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224748 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22917056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22917056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 548519 # Request fanout histogram +system.membus.snoop_fanout::samples 291396 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291396 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548519 # Request fanout histogram -system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291396 # Request fanout histogram +system.membus.reqLayer0.occupancy 815280500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1456980000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 031a11fd6..228ad0113 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,96 +1,96 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.512589 # Number of seconds simulated -sim_ticks 512588680500 # Number of ticks simulated -final_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.512877 # Number of seconds simulated +sim_ticks 512876814500 # Number of ticks simulated +final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180394 # Simulator instruction rate (inst/s) -host_op_rate 222088 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144333179 # Simulator tick rate (ticks/s) -host_mem_usage 275860 # Number of bytes of host memory used -host_seconds 3551.43 # Real time elapsed on the host +host_inst_rate 169706 # Simulator instruction rate (inst/s) +host_op_rate 208931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 135858559 # Simulator tick rate (ticks/s) +host_mem_usage 281524 # Number of bytes of host memory used +host_seconds 3775.08 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory -system.physmem.bytes_read::total 18638208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory +system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291222 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291229 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18288 # Per bank write bursts -system.physmem.perBankRdBursts::1 18133 # Per bank write bursts -system.physmem.perBankRdBursts::2 18220 # Per bank write bursts -system.physmem.perBankRdBursts::3 18178 # Per bank write bursts -system.physmem.perBankRdBursts::4 18281 # Per bank write bursts -system.physmem.perBankRdBursts::5 18410 # Per bank write bursts -system.physmem.perBankRdBursts::6 18174 # Per bank write bursts -system.physmem.perBankRdBursts::7 17993 # Per bank write bursts -system.physmem.perBankRdBursts::8 18029 # Per bank write bursts -system.physmem.perBankRdBursts::9 18057 # Per bank write bursts -system.physmem.perBankRdBursts::10 18103 # Per bank write bursts -system.physmem.perBankRdBursts::11 18205 # Per bank write bursts -system.physmem.perBankRdBursts::12 18223 # Per bank write bursts -system.physmem.perBankRdBursts::13 18272 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18257 # Per bank write bursts +system.physmem.perBankRdBursts::0 18285 # Per bank write bursts +system.physmem.perBankRdBursts::1 18130 # Per bank write bursts +system.physmem.perBankRdBursts::2 18219 # Per bank write bursts +system.physmem.perBankRdBursts::3 18177 # Per bank write bursts +system.physmem.perBankRdBursts::4 18285 # Per bank write bursts +system.physmem.perBankRdBursts::5 18413 # Per bank write bursts +system.physmem.perBankRdBursts::6 18173 # Per bank write bursts +system.physmem.perBankRdBursts::7 17985 # Per bank write bursts +system.physmem.perBankRdBursts::8 18026 # Per bank write bursts +system.physmem.perBankRdBursts::9 18055 # Per bank write bursts +system.physmem.perBankRdBursts::10 18102 # Per bank write bursts +system.physmem.perBankRdBursts::11 18206 # Per bank write bursts +system.physmem.perBankRdBursts::12 18220 # Per bank write bursts +system.physmem.perBankRdBursts::13 18274 # Per bank write bursts +system.physmem.perBankRdBursts::14 18073 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts -system.physmem.perBankWrBursts::1 4099 # Per bank write bursts -system.physmem.perBankWrBursts::2 4135 # Per bank write bursts +system.physmem.perBankWrBursts::1 4098 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4223 # Per bank write bursts -system.physmem.perBankWrBursts::5 4222 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4092 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 512588586500 # Total gap between requests +system.physmem.totGap 512876719500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291222 # Read request sizes (log2) +system.physmem.readPktSize::6 291229 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,7 +98,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,87 +194,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads -system.physmem.totQLat 2758807250 # Total ticks spent queuing -system.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads +system.physmem.totQLat 2756382250 # Total ticks spent queuing +system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing -system.physmem.readRowHits 195021 # Number of row buffer hits during reads -system.physmem.writeRowHits 51610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes -system.physmem.avgGap 1434536.51 # Average gap between requests -system.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.106023 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states -system.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states +system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing +system.physmem.readRowHits 194946 # Number of row buffer hits during reads +system.physmem.writeRowHits 51576 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes +system.physmem.avgGap 1435314.77 # Average gap between requests +system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.111511 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states +system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.023062 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states -system.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states +system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.035798 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states +system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 147261658 # Number of BP lookups system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect @@ -289,7 +288,7 @@ system.cpu.branchPred.indirectHits 15988941 # Nu system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -319,7 +318,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -349,7 +348,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,7 +378,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,16 +409,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1025177361 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1025753629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.600202 # CPI: cycles per instruction -system.cpu.ipc 0.624921 # IPC: instructions per cycle +system.cpu.cpi 1.601101 # CPI: cycles per instruction +system.cpu.ipc 0.624570 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction @@ -455,28 +454,28 @@ system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked +system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778100 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits @@ -501,14 +500,14 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -533,22 +532,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34532.709986 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34532.709986 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73613.962472 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73613.962472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40857.697813 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40857.697813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40850.928564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40850.928564 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88716 # number of writebacks -system.cpu.dcache.writebacks::total 88716 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks +system.cpu.dcache.writebacks::total 88688 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits @@ -567,16 +566,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057 system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23907337500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23907337500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28991619500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28991619500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993407500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28993407500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -587,70 +586,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33543.094558 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33543.094558 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73342.979141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73342.979141 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37070.980120 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37070.980120 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37066.678301 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37066.678301 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24885 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.979735 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 257789647 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9678.241741 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.979735 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835928 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 515659204 # Number of tag accesses -system.cpu.icache.tags.data_accesses 515659204 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 257789647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 257789647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 257789647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 257789647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 257789647 # number of overall hits -system.cpu.icache.overall_hits::total 257789647 # number of overall hits +system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses +system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits +system.cpu.icache.overall_hits::total 257789646 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses system.cpu.icache.overall_misses::total 26637 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 515552500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 515552500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 515552500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 515552500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 515552500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 515552500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 257816284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 257816284 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19354.750910 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19354.750910 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19354.750910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19354.750910 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,90 +664,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 26637 system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 488916500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 488916500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 488916500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 488916500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 488916500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 488916500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18354.788452 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18354.788452 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258816 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32567.443571 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1247529 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291562 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.278778 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2619.708679 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.014636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29858.720256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.079947 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002717 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.911216 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 258837 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29128 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13229556 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13229556 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88716 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88716 # number of WritebackDirty hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490282 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490282 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493513 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 517580 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517573 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493513 # number of overall hits -system.cpu.l2cache.overall_hits::total 517580 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits +system.cpu.l2cache.overall_hits::total 517573 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222592 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222592 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288683 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291253 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288683 # number of overall misses -system.cpu.l2cache.overall_misses::total 291253 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4946370000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4946370000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194980000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 194980000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17689881000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17689881000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 194980000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22636251000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22831231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 194980000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22636251000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22831231000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88716 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses +system.cpu.l2cache.overall_misses::total 291260 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) @@ -767,26 +766,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312246 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312246 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369067 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360090 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369067 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360090 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74841.809021 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74841.809021 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.704280 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.704280 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79472.222721 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79472.222721 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78389.685256 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78389.685256 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,61 +808,61 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution @@ -872,53 +871,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258816 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258837 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225131 # Transaction distribution +system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225138 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190690 # Transaction distribution +system.membus.trans_dist::CleanEvict 190702 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 548010 # Request fanout histogram +system.membus.snoop_fanout::samples 291229 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548010 # Request fanout histogram -system.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291229 # Request fanout histogram +system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index c91bb3ccb..2975218ad 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.326731 # Number of seconds simulated -sim_ticks 326731324000 # Number of ticks simulated -final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.327896 # Number of seconds simulated +sim_ticks 327895638000 # Number of ticks simulated +final_tick 327895638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165193 # Simulator instruction rate (inst/s) -host_op_rate 203374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84248396 # Simulator tick rate (ticks/s) -host_mem_usage 272920 # Number of bytes of host memory used -host_seconds 3878.19 # Real time elapsed on the host +host_inst_rate 125299 # Simulator instruction rate (inst/s) +host_op_rate 154259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64130088 # Simulator tick rate (ticks/s) +host_mem_usage 277300 # Number of bytes of host memory used +host_seconds 5112.98 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory -system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 953240 # Number of read requests accepted -system.physmem.writeReqs 66334 # Number of write requests accepted -system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 266368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48003200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12980224 # Number of bytes read from this memory +system.physmem.bytes_read::total 61249792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 266368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 266368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244096 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202816 # Number of read requests responded to by this memory +system.physmem.num_reads::total 957028 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66314 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66314 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 812356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146397800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 39586449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186796605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12943435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12943435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12943435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146397800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 39586449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 199740040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 957029 # Number of read requests accepted +system.physmem.writeReqs 66314 # Number of write requests accepted +system.physmem.readBursts 957029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66314 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61231232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue +system.physmem.bytesWritten 4237440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61249856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 72 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19685 # Per bank write bursts -system.physmem.perBankRdBursts::1 19287 # Per bank write bursts -system.physmem.perBankRdBursts::2 657567 # Per bank write bursts -system.physmem.perBankRdBursts::3 20052 # Per bank write bursts -system.physmem.perBankRdBursts::4 19480 # Per bank write bursts -system.physmem.perBankRdBursts::5 20770 # Per bank write bursts -system.physmem.perBankRdBursts::6 19386 # Per bank write bursts -system.physmem.perBankRdBursts::7 19760 # Per bank write bursts -system.physmem.perBankRdBursts::8 19321 # Per bank write bursts -system.physmem.perBankRdBursts::9 19768 # Per bank write bursts -system.physmem.perBankRdBursts::10 19303 # Per bank write bursts -system.physmem.perBankRdBursts::11 19444 # Per bank write bursts -system.physmem.perBankRdBursts::12 19433 # Per bank write bursts -system.physmem.perBankRdBursts::13 20871 # Per bank write bursts -system.physmem.perBankRdBursts::14 19269 # Per bank write bursts -system.physmem.perBankRdBursts::15 19527 # Per bank write bursts -system.physmem.perBankWrBursts::0 4288 # Per bank write bursts -system.physmem.perBankWrBursts::1 4110 # Per bank write bursts -system.physmem.perBankWrBursts::2 4140 # Per bank write bursts -system.physmem.perBankWrBursts::3 4154 # Per bank write bursts -system.physmem.perBankWrBursts::4 4242 # Per bank write bursts -system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankRdBursts::0 19913 # Per bank write bursts +system.physmem.perBankRdBursts::1 19609 # Per bank write bursts +system.physmem.perBankRdBursts::2 657177 # Per bank write bursts +system.physmem.perBankRdBursts::3 20974 # Per bank write bursts +system.physmem.perBankRdBursts::4 19738 # Per bank write bursts +system.physmem.perBankRdBursts::5 20841 # Per bank write bursts +system.physmem.perBankRdBursts::6 19544 # Per bank write bursts +system.physmem.perBankRdBursts::7 20056 # Per bank write bursts +system.physmem.perBankRdBursts::8 19527 # Per bank write bursts +system.physmem.perBankRdBursts::9 20071 # Per bank write bursts +system.physmem.perBankRdBursts::10 19467 # Per bank write bursts +system.physmem.perBankRdBursts::11 19786 # Per bank write bursts +system.physmem.perBankRdBursts::12 19618 # Per bank write bursts +system.physmem.perBankRdBursts::13 21115 # Per bank write bursts +system.physmem.perBankRdBursts::14 19501 # Per bank write bursts +system.physmem.perBankRdBursts::15 19801 # Per bank write bursts +system.physmem.perBankWrBursts::0 4241 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts +system.physmem.perBankWrBursts::2 4141 # Per bank write bursts +system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.perBankWrBursts::4 4245 # Per bank write bursts +system.physmem.perBankWrBursts::5 4233 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4146 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 326731313500 # Total gap between requests +system.physmem.totGap 327895627500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 953240 # Read request sizes (log2) +system.physmem.readPktSize::6 957029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66334 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66314 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 765529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 621 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,48 +149,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -198,120 +198,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads -system.physmem.totQLat 12733277648 # Total ticks spent queuing -system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 194181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.148207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.280987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 364.158297 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 64676 33.31% 33.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60636 31.23% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15729 8.10% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3217 1.66% 74.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3574 1.84% 76.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2317 1.19% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2364 1.22% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21831 11.24% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19837 10.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 194181 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 177.226065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.842577 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1813.556545 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3969 99.47% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 4 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 2 0.05% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-32767 2 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::86016-90111 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.593985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.513577 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.886226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3332 83.51% 83.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 5 0.13% 83.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 452 11.33% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 50 1.25% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 19 0.48% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.43% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.25% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.48% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.30% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.38% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.40% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.38% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 9 0.23% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.13% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.08% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.08% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3990 # Writes before turning the bus around for reads +system.physmem.totQLat 12587538724 # Total ticks spent queuing +system.physmem.totMemAccLat 30526376224 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4783690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13156.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31906.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 186.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 186.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 12.94 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.56 # Data bus utilization in percentage system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing -system.physmem.readRowHits 805882 # Number of row buffer hits during reads -system.physmem.writeRowHits 26140 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes -system.physmem.avgGap 320458.66 # Average gap between requests -system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) -system.physmem_0.averagePower 771.975754 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states -system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 805843 # Number of row buffer hits during reads +system.physmem.writeRowHits 22921 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.60 # Row buffer hit rate for writes +system.physmem.avgGap 320416.15 # Average gap between requests +system.physmem.pageHitRate 81.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 934317720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 509796375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6223237800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216334800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 220944760020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2925699000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 253170624435 # Total energy per rank (pJ) +system.physmem_0.averagePower 772.109253 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3595093339 # Time in different power states +system.physmem_0.memoryStateTime::REF 10949120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states +system.physmem_0.memoryStateTime::ACT 313351421161 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) -system.physmem_1.averagePower 704.579541 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states -system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states +system.physmem_1.actEnergy 533690640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 291200250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1239209400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88116969465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 119441319000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 231251573475 # Total energy per rank (pJ) +system.physmem_1.averagePower 705.261391 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 198129163855 # Time in different power states +system.physmem_1.memoryStateTime::REF 10949120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states +system.physmem_1.memoryStateTime::ACT 118816573145 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174663372 # Number of BP lookups -system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174659739 # Number of BP lookups +system.cpu.branchPred.condPredicted 119113225 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015668 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96720974 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67755362 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.052398 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18785155 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 16716286 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16701799 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14487 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279501 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +347,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -371,7 +377,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,7 +407,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -432,85 +438,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 653462649 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 655791277 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 34353189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824276690 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174659739 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103242316 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 616975428 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3170 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247740649 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12515 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 655368010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.551156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.253828 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 193301276 29.50% 29.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148337850 22.63% 52.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72946568 11.13% 63.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240782316 36.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4317999600 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 655368010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.266334 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.256919 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75112130 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 236493276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277761287 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61980307 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021010 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20809608 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13112 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924575224 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11804312 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021010 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118055519 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 135785787 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 212608 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 294557237 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102735849 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906541412 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6891100 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27959034 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218150 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49337765 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 468731 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980926815 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318009248 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001835221 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457086 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244402361 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106148585 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6844 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6835 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138814111 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271882035 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160585921 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6159068 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12159693 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899827224 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12580 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860029296 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216848 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114846 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244387313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 655368010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.312285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.094624 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 192710599 29.40% 29.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182406257 27.83% 57.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 175554116 26.79% 84.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 92275656 14.08% 98.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12419071 1.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -518,9 +524,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 655368010 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66605310 24.62% 24.62% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available @@ -549,13 +555,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 134121363 49.58% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69112589 25.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413090005 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187656 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -577,88 +583,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550150 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478194 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 266665504 31.01% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 157232585 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued -system.cpu.iq.rate 1.316105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860029296 # Type of FU issued +system.cpu.iq.rate 1.311438 # Inst issue rate +system.cpu.iq.fu_busy_cnt 270494293 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314518 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2597595667 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980331886 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820082893 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 57542076 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878673 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1098503163 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32020426 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13986768 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 19641097 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18820 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31605425 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 17201 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021010 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10590461 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6281 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899849934 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271882035 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160585921 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6840 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 959 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3423 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18820 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3290187 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585316 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850173752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263373804 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855544 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10252 # number of nop insts executed -system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed -system.cpu.iew.exec_branches 143379422 # Number of branches executed -system.cpu.iew.exec_stores 152688943 # Number of stores executed -system.cpu.iew.exec_rate 1.301023 # Inst execution rate -system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back -system.cpu.iew.wb_producers 487338276 # num instructions producing a value -system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value -system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10130 # number of nop insts executed +system.cpu.iew.exec_refs 416063188 # number of memory reference insts executed +system.cpu.iew.exec_branches 143381327 # Number of branches executed +system.cpu.iew.exec_stores 152689384 # Number of stores executed +system.cpu.iew.exec_rate 1.296409 # Inst execution rate +system.cpu.iew.wb_sent 846297655 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844961566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 487343298 # num instructions producing a value +system.cpu.iew.wb_consumers 808106626 # num instructions consuming a value +system.cpu.iew.wb_rate 1.288461 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.603068 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103169122 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002654 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 640787345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.230876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.070419 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 350447626 54.69% 54.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137241088 21.42% 76.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51341072 8.01% 84.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28220230 4.40% 88.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14380949 2.24% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774505 2.31% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871971 1.23% 94.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561231 1.02% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29948673 4.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 640787345 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,82 +710,82 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1500478116 # The number of ROB reads -system.cpu.rob.rob_writes 1798380886 # The number of ROB writes -system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29948673 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1502729113 # The number of ROB reads +system.cpu.rob.rob_writes 1798382436 # The number of ROB writes +system.cpu.timesIdled 10485 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 423267 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868460109 # number of integer regfile reads -system.cpu.int_regfile_writes 500697086 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads -system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes -system.cpu.misc_regfile_reads 606830951 # number of misc regfile reads +system.cpu.cpi 1.023635 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.023635 # CPI: Total CPI of All Threads +system.cpu.ipc 0.976910 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.976910 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868461212 # number of integer regfile reads +system.cpu.int_regfile_writes 500699124 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616064 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959493 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322386264 # number of cc regfile reads +system.cpu.cc_regfile_writes 369207629 # number of cc regfile writes +system.cpu.misc_regfile_reads 606832888 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756452 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756458 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.912011 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371050492 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756970 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.586336 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 274880000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.912011 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999828 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999828 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751746846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751746846 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243126867 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243126867 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907624 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907624 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits -system.cpu.dcache.overall_hits::total 371035352 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371034491 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371034491 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371037648 # number of overall hits +system.cpu.dcache.overall_hits::total 371037648 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043853 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043853 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses -system.cpu.dcache.overall_misses::total 3447085 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3445163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3445163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3445810 # number of overall misses +system.cpu.dcache.overall_misses::total 3445810 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69278020000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69278020000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9882341350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9882341350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 168500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 168500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 79160361350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 79160361350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 79160361350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 79160361350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245528177 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245528177 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -788,70 +794,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 374479654 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374479654 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374483458 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374483458 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9467.177227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9467.177227 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 245757404 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.117895 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 264413500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.874726 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997802 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits -system.cpu.icache.overall_hits::total 245759426 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8157.462943 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8157.462943 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 75964 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2856 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks -system.cpu.icache.writebacks::total 1979880 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # 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Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15777 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1577 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3842 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9849 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025513 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962952 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 48582269000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294714000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48287555000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 65119070285 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002102 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.159217 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1296784 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4257152 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202053 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 81496.600949 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15114.942529 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15114.942529 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97808.002937 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97808.002937 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70793.658419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70793.658419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64318.301482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64318.301482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9473332 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736180 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 642769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4016330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 230920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 258553 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036124 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270746 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14210509 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606270912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 555960 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4255168 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5293139 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121491 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.326697 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4650072 87.85% 87.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 643066 12.15% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5293139 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9472646000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2970310996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135552978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 951856 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution -system.membus.trans_dist::CleanEvict 227102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 185 # Transaction distribution -system.membus.trans_dist::ReadExReq 1383 # Transaction distribution -system.membus.trans_dist::ReadExResp 1383 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 1254437 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 940010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 955666 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66314 # Transaction distribution +system.membus.trans_dist::CleanEvict 230920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 1362 # Transaction distribution +system.membus.trans_dist::ReadExResp 1362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 955667 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211465 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2211465 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65493888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65493888 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1246861 # Request fanout histogram +system.membus.snoop_fanout::samples 957203 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 957203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1246861 # Request fanout histogram -system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 957203 # Request fanout histogram +system.membus.reqLayer0.occupancy 1755655982 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5035261795 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 889d833d4..e76db2752 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 860032 # Simulator instruction rate (inst/s) -host_op_rate 1058813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 531234389 # Simulator tick rate (ticks/s) -host_mem_usage 264584 # Number of bytes of host memory used -host_seconds 744.92 # Real time elapsed on the host +host_inst_rate 969638 # Simulator instruction rate (inst/s) +host_op_rate 1193752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 598936996 # Simulator tick rate (ticks/s) +host_mem_usage 268708 # Number of bytes of host memory used +host_seconds 660.72 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 893703778 # Transaction distribution system.membus.trans_dist::ReadResp 893709517 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 4241547525 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1022670353 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 3a062984a..c71a30606 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.045756 # Number of seconds simulated -sim_ticks 1045756396500 # Number of ticks simulated -final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.046047 # Number of seconds simulated +sim_ticks 1046047111500 # Number of ticks simulated +final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 546786 # Simulator instruction rate (inst/s) -host_op_rate 671760 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 894330624 # Simulator tick rate (ticks/s) -host_mem_usage 273552 # Number of bytes of host memory used -host_seconds 1169.32 # Real time elapsed on the host +host_inst_rate 666714 # Simulator instruction rate (inst/s) +host_op_rate 819099 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1090788712 # Simulator tick rate (ticks/s) +host_mem_usage 278188 # Number of bytes of host memory used +host_seconds 958.98 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory -system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory +system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2091512793 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2092094223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks -system.cpu.dcache.writebacks::total 88995 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks +system.cpu.dcache.writebacks::total 88967 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits @@ -329,16 +329,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -349,26 +349,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id @@ -376,7 +376,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits @@ -389,12 +389,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -407,12 +407,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -427,90 +427,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution @@ -624,53 +624,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257772 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257791 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224275 # Transaction distribution +system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 224282 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190094 # Transaction distribution +system.membus.trans_dist::CleanEvict 190103 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 546561 # Request fanout histogram +system.membus.snoop_fanout::samples 290376 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 546561 # Request fanout histogram -system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 290376 # Request fanout histogram +system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 6234d30e2..58628a22b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060001 # Number of seconds simulated -sim_ticks 60000593000 # Number of ticks simulated -final_tick 60000593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060094 # Number of seconds simulated +sim_ticks 60093931000 # Number of ticks simulated +final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 262235 # Simulator instruction rate (inst/s) -host_op_rate 262235 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177912819 # Simulator tick rate (ticks/s) -host_mem_usage 257844 # Number of bytes of host memory used -host_seconds 337.25 # Real time elapsed on the host +host_inst_rate 276952 # Simulator instruction rate (inst/s) +host_op_rate 276952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188189933 # Simulator tick rate (ticks/s) +host_mem_usage 264524 # Number of bytes of host memory used +host_seconds 319.33 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 433344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10150272 # Number of bytes read from this memory -system.physmem.bytes_read::total 10583616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 433344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 433344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7325952 # Number of bytes written to this memory -system.physmem.bytes_written::total 7325952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158598 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165369 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114468 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114468 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7222329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169169528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 176391857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7222329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7222329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122097993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122097993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122097993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7222329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169169528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 298489850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165369 # Number of read requests accepted -system.physmem.writeReqs 114468 # Number of write requests accepted -system.physmem.readBursts 165369 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114468 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10583232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7324288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10583616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7325952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory +system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory +system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165736 # Number of read requests accepted +system.physmem.writeReqs 115250 # Number of write requests accepted +system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10322 # Per bank write bursts -system.physmem.perBankRdBursts::1 10363 # Per bank write bursts -system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10055 # Per bank write bursts -system.physmem.perBankRdBursts::4 10347 # Per bank write bursts -system.physmem.perBankRdBursts::5 10343 # Per bank write bursts -system.physmem.perBankRdBursts::6 9774 # Per bank write bursts -system.physmem.perBankRdBursts::7 10209 # Per bank write bursts -system.physmem.perBankRdBursts::8 10543 # Per bank write bursts -system.physmem.perBankRdBursts::9 10609 # Per bank write bursts -system.physmem.perBankRdBursts::10 10499 # Per bank write bursts -system.physmem.perBankRdBursts::11 10227 # Per bank write bursts -system.physmem.perBankRdBursts::12 10274 # Per bank write bursts -system.physmem.perBankRdBursts::13 10565 # Per bank write bursts -system.physmem.perBankRdBursts::14 10463 # Per bank write bursts -system.physmem.perBankRdBursts::15 10564 # Per bank write bursts -system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7274 # Per bank write bursts -system.physmem.perBankWrBursts::2 7296 # Per bank write bursts -system.physmem.perBankWrBursts::3 7001 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7187 # Per bank write bursts -system.physmem.perBankWrBursts::6 6833 # Per bank write bursts -system.physmem.perBankWrBursts::7 7100 # Per bank write bursts -system.physmem.perBankWrBursts::8 7227 # Per bank write bursts -system.physmem.perBankWrBursts::9 7003 # Per bank write bursts -system.physmem.perBankWrBursts::10 7117 # Per bank write bursts -system.physmem.perBankWrBursts::11 7031 # Per bank write bursts -system.physmem.perBankWrBursts::12 6992 # Per bank write bursts -system.physmem.perBankWrBursts::13 7301 # Per bank write bursts -system.physmem.perBankWrBursts::14 7308 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankRdBursts::0 10345 # Per bank write bursts +system.physmem.perBankRdBursts::1 10388 # Per bank write bursts +system.physmem.perBankRdBursts::2 10224 # Per bank write bursts +system.physmem.perBankRdBursts::3 10067 # Per bank write bursts +system.physmem.perBankRdBursts::4 10353 # Per bank write bursts +system.physmem.perBankRdBursts::5 10360 # Per bank write bursts +system.physmem.perBankRdBursts::6 9794 # Per bank write bursts +system.physmem.perBankRdBursts::7 10229 # Per bank write bursts +system.physmem.perBankRdBursts::8 10568 # Per bank write bursts +system.physmem.perBankRdBursts::9 10626 # Per bank write bursts +system.physmem.perBankRdBursts::10 10567 # Per bank write bursts +system.physmem.perBankRdBursts::11 10241 # Per bank write bursts +system.physmem.perBankRdBursts::12 10307 # Per bank write bursts +system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::14 10494 # Per bank write bursts +system.physmem.perBankRdBursts::15 10573 # Per bank write bursts +system.physmem.perBankWrBursts::0 7166 # Per bank write bursts +system.physmem.perBankWrBursts::1 7280 # Per bank write bursts +system.physmem.perBankWrBursts::2 7303 # Per bank write bursts +system.physmem.perBankWrBursts::3 7011 # Per bank write bursts +system.physmem.perBankWrBursts::4 7144 # Per bank write bursts +system.physmem.perBankWrBursts::5 7304 # Per bank write bursts +system.physmem.perBankWrBursts::6 6890 # Per bank write bursts +system.physmem.perBankWrBursts::7 7170 # Per bank write bursts +system.physmem.perBankWrBursts::8 7244 # Per bank write bursts +system.physmem.perBankWrBursts::9 7072 # Per bank write bursts +system.physmem.perBankWrBursts::10 7215 # Per bank write bursts +system.physmem.perBankWrBursts::11 7126 # Per bank write bursts +system.physmem.perBankWrBursts::12 7072 # Per bank write bursts +system.physmem.perBankWrBursts::13 7397 # Per bank write bursts +system.physmem.perBankWrBursts::14 7353 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60000569500 # Total gap between requests +system.physmem.totGap 60093907500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165369 # Read request sizes (log2) +system.physmem.readPktSize::6 165736 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114468 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115250 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,126 +194,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.137094 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.166991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.705237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19617 35.84% 35.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11794 21.55% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5683 10.38% 67.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3657 6.68% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2805 5.12% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2027 3.70% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1612 2.95% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1505 2.75% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6036 11.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54736 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.474162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.252876 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7042 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.246735 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.230854 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.753728 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6287 89.25% 89.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 12 0.17% 89.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 574 8.15% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 138 1.96% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.26% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 7 0.10% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7044 # Writes before turning the bus around for reads -system.physmem.totQLat 1985984500 # Total ticks spent queuing -system.physmem.totMemAccLat 5086540750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12009.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads +system.physmem.totQLat 1892978500 # Total ticks spent queuing +system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30759.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 176.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 176.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.33 # Data bus utilization in percentage +system.physmem.busUtil 2.34 # Data bus utilization in percentage system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 143816 # Number of row buffer hits during reads -system.physmem.writeRowHits 81240 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.97 # Row buffer hit rate for writes -system.physmem.avgGap 214412.57 # Average gap between requests -system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 198964080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108561750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636386400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 369061920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12421358775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25100061000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42752848725 # Total energy per rank (pJ) -system.physmem_0.averagePower 712.626862 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41606215000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2003300000 # Time in different power states +system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing +system.physmem.readRowHits 144145 # Number of row buffer hits during reads +system.physmem.writeRowHits 89685 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes +system.physmem.avgGap 213867.98 # Average gap between requests +system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ) +system.physmem_0.averagePower 711.117850 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16383815000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214545240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117063375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 652945800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 372211200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13100937570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24503939250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42880097235 # Total energy per rank (pJ) -system.physmem_1.averagePower 714.747907 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40611255500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2003300000 # Time in different power states +system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ) +system.physmem_1.averagePower 713.246634 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17379160000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14695118 # Number of BP lookups -system.cpu.branchPred.condPredicted 9500860 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 385258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10182600 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6367092 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14696108 # Number of BP lookups +system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.529138 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712185 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84621 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37568 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5776 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20578668 # DTB read hits -system.cpu.dtb.read_misses 95435 # DTB read misses +system.cpu.dtb.read_hits 20579333 # DTB read hits +system.cpu.dtb.read_misses 95423 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674103 # DTB read accesses -system.cpu.dtb.write_hits 14665915 # DTB write hits -system.cpu.dtb.write_misses 8842 # DTB write misses +system.cpu.dtb.read_accesses 20674756 # DTB read accesses +system.cpu.dtb.write_hits 14666035 # DTB write hits +system.cpu.dtb.write_misses 8840 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674757 # DTB write accesses -system.cpu.dtb.data_hits 35244583 # DTB hits -system.cpu.dtb.data_misses 104277 # DTB misses +system.cpu.dtb.write_accesses 14674875 # DTB write accesses +system.cpu.dtb.data_hits 35245368 # DTB hits +system.cpu.dtb.data_misses 104263 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35348860 # DTB accesses -system.cpu.itb.fetch_hits 25646396 # ITB hits -system.cpu.itb.fetch_misses 5177 # ITB misses +system.cpu.dtb.data_accesses 35349631 # DTB accesses +system.cpu.itb.fetch_hits 25649355 # ITB hits +system.cpu.itb.fetch_misses 5175 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25651573 # ITB accesses +system.cpu.itb.fetch_accesses 25654530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -327,16 +325,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120001186 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120187862 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1084586 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.356895 # CPI: cycles per instruction -system.cpu.ipc 0.736977 # IPC: instructions per cycle +system.cpu.cpi 1.359006 # CPI: cycles per instruction +system.cpu.ipc 0.735832 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -372,58 +370,58 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91986001 # Number of cycles that the object actually ticked -system.cpu.idleCycles 28015185 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200807 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.707874 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34647558 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204903 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.092488 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 690770500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.707874 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy +system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked +system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200806 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3387 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70183301 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70183301 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314289 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314289 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333269 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333269 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34647558 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34647558 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34647558 # number of overall hits -system.cpu.dcache.overall_hits::total 34647558 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280108 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280108 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341641 # number of overall misses -system.cpu.dcache.overall_misses::total 341641 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2738549500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2738549500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21709876500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21709876500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24448426000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24448426000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24448426000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24448426000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20375822 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20375822 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits +system.cpu.dcache.overall_hits::total 34648172 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses +system.cpu.dcache.overall_misses::total 341638 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989199 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses @@ -432,46 +430,46 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44505.379227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44505.379227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77505.378283 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77505.378283 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71561.744638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71561.744638 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168446 # number of writebacks -system.cpu.dcache.writebacks::total 168446 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136541 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136541 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136738 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136738 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136738 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136738 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61336 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61336 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168116 # number of writebacks +system.cpu.dcache.writebacks::total 168116 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 194 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136542 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136542 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 136736 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 136736 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 136736 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 136736 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61335 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61335 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204903 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204903 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204903 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204903 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2673829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2673829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10980283500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10980283500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13654113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13654113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13654113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13654113000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204902 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204902 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204902 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204902 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2722762000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2722762000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994246500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994246500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13717008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13717008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13717008500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13717008500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -480,332 +478,338 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43593.150841 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43593.150841 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76481.945712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76481.945712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66636.959927 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66636.959927 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66636.959927 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66636.959927 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 153927 # number of replacements -system.cpu.icache.tags.tagsinuse 1931.746995 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25490420 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 155975 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.426318 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42594058500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1931.746995 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943236 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943236 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44391.652401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44391.652401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76579.203438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76579.203438 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 153916 # number of replacements +system.cpu.icache.tags.tagsinuse 1931.382130 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25493390 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155964 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.456887 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42683279500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1931.382130 # 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number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25646396 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25646396 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15996.393676 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15996.393676 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15996.393676 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15996.393676 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15996.393676 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15996.393676 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25493390 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25493390 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25493390 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25493390 # number of overall hits +system.cpu.icache.overall_hits::total 25493390 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25649355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25649355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25649355 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25649355 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25649355 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25649355 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006081 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006081 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006081 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006081 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006081 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006081 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16150.553009 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16150.553009 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16150.553009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16150.553009 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153927 # number of writebacks -system.cpu.icache.writebacks::total 153927 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155976 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155976 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155976 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155976 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155976 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155976 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2339078500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2339078500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2339078500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2339078500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2339078500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2339078500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14996.400087 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14996.400087 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14996.400087 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14996.400087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14996.400087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14996.400087 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 133391 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30427.789253 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 406173 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 165503 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.454173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26336.336681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2098.353555 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1993.099017 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803721 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.060825 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928582 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1064 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979980 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 6033974 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 6033974 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168446 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168446 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153927 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153927 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12684 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12684 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149204 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 149204 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33621 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33621 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 149204 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46305 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 195509 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 149204 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46305 # number of overall hits -system.cpu.l2cache.overall_hits::total 195509 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130883 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130883 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6772 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6772 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27715 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27715 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6772 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158598 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165370 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6772 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158598 # number of overall misses -system.cpu.l2cache.overall_misses::total 165370 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10631688000 # 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number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2362957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2362957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2362957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2362957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2362957000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2362957000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15150.559420 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15150.559420 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 135276 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31728.322423 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 547427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168044 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.257641 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13928082000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 716.089195 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1994.899360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29017.333867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.021853 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71021.699825 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715613 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354734 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043914 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459274 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459274 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4027 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51284 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61336 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19833728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23894336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43728064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133391 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7325952 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 494270 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008147 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.089894 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135276 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 490243 99.19% 99.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4027 0.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 494270 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 680179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233962999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307359989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34486 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114468 # Transaction distribution -system.membus.trans_dist::CleanEvict 15010 # Transaction distribution -system.membus.trans_dist::ReadExReq 130883 # Transaction distribution -system.membus.trans_dist::ReadExResp 130883 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34486 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460216 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460216 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17909568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17909568 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34828 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution +system.membus.trans_dist::CleanEvict 15883 # Transaction distribution +system.membus.trans_dist::ReadExReq 130908 # Transaction distribution +system.membus.trans_dist::ReadExResp 130908 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 294847 # Request fanout histogram +system.membus.snoop_fanout::samples 165736 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294847 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294847 # Request fanout histogram -system.membus.reqLayer0.occupancy 819183500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 165736 # Request fanout histogram +system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 873079500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 4fef80875..4f7e5b26f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022275 # Number of seconds simulated -sim_ticks 22275010500 # Number of ticks simulated -final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022294 # Number of seconds simulated +sim_ticks 22293541500 # Number of ticks simulated +final_tick 22293541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202670 # Simulator instruction rate (inst/s) -host_op_rate 202670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56720302 # Simulator tick rate (ticks/s) -host_mem_usage 259380 # Number of bytes of host memory used -host_seconds 392.72 # Real time elapsed on the host +host_inst_rate 223643 # Simulator instruction rate (inst/s) +host_op_rate 223643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62642230 # Simulator tick rate (ticks/s) +host_mem_usage 265292 # Number of bytes of host memory used +host_seconds 355.89 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory -system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7322816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7322816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114419 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114419 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18405558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455811951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 474217509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18405558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18405558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 328745793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 328745793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 328745793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18405558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455811951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 802963303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165050 # Number of read requests accepted -system.physmem.writeReqs 114419 # Number of write requests accepted -system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114419 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7320960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7322816 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 413888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10171008 # Number of bytes read from this memory +system.physmem.bytes_read::total 10584896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 413888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 413888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158922 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115200 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18565377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 456231147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 474796523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18565377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18565377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 330714615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 330714615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 330714615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18565377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 456231147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 805511139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165389 # Number of read requests accepted +system.physmem.writeReqs 115200 # Number of write requests accepted +system.physmem.readBursts 165389 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115200 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10584320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7371392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10584896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7372800 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10290 # Per bank write bursts -system.physmem.perBankRdBursts::1 10331 # Per bank write bursts -system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10021 # Per bank write bursts -system.physmem.perBankRdBursts::4 10343 # Per bank write bursts -system.physmem.perBankRdBursts::5 10313 # Per bank write bursts -system.physmem.perBankRdBursts::6 9783 # Per bank write bursts -system.physmem.perBankRdBursts::7 10190 # Per bank write bursts -system.physmem.perBankRdBursts::8 10528 # Per bank write bursts -system.physmem.perBankRdBursts::9 10599 # Per bank write bursts -system.physmem.perBankRdBursts::10 10456 # Per bank write bursts -system.physmem.perBankRdBursts::11 10208 # Per bank write bursts -system.physmem.perBankRdBursts::12 10247 # Per bank write bursts -system.physmem.perBankRdBursts::13 10535 # Per bank write bursts -system.physmem.perBankRdBursts::14 10446 # Per bank write bursts -system.physmem.perBankRdBursts::15 10548 # Per bank write bursts -system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7268 # Per bank write bursts -system.physmem.perBankWrBursts::2 7294 # Per bank write bursts -system.physmem.perBankWrBursts::3 7001 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts -system.physmem.perBankWrBursts::6 6836 # Per bank write bursts -system.physmem.perBankWrBursts::7 7101 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts -system.physmem.perBankWrBursts::9 7003 # Per bank write bursts -system.physmem.perBankWrBursts::10 7101 # Per bank write bursts -system.physmem.perBankWrBursts::11 7022 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7296 # Per bank write bursts -system.physmem.perBankWrBursts::14 7307 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankRdBursts::0 10310 # Per bank write bursts +system.physmem.perBankRdBursts::1 10350 # Per bank write bursts +system.physmem.perBankRdBursts::2 10221 # Per bank write bursts +system.physmem.perBankRdBursts::3 10037 # Per bank write bursts +system.physmem.perBankRdBursts::4 10349 # Per bank write bursts +system.physmem.perBankRdBursts::5 10325 # Per bank write bursts +system.physmem.perBankRdBursts::6 9802 # Per bank write bursts +system.physmem.perBankRdBursts::7 10210 # Per bank write bursts +system.physmem.perBankRdBursts::8 10556 # Per bank write bursts +system.physmem.perBankRdBursts::9 10619 # Per bank write bursts +system.physmem.perBankRdBursts::10 10516 # Per bank write bursts +system.physmem.perBankRdBursts::11 10224 # Per bank write bursts +system.physmem.perBankRdBursts::12 10277 # Per bank write bursts +system.physmem.perBankRdBursts::13 10556 # Per bank write bursts +system.physmem.perBankRdBursts::14 10475 # Per bank write bursts +system.physmem.perBankRdBursts::15 10553 # Per bank write bursts +system.physmem.perBankWrBursts::0 7167 # Per bank write bursts +system.physmem.perBankWrBursts::1 7278 # Per bank write bursts +system.physmem.perBankWrBursts::2 7300 # Per bank write bursts +system.physmem.perBankWrBursts::3 7008 # Per bank write bursts +system.physmem.perBankWrBursts::4 7143 # Per bank write bursts +system.physmem.perBankWrBursts::5 7301 # Per bank write bursts +system.physmem.perBankWrBursts::6 6892 # Per bank write bursts +system.physmem.perBankWrBursts::7 7161 # Per bank write bursts +system.physmem.perBankWrBursts::8 7241 # Per bank write bursts +system.physmem.perBankWrBursts::9 7068 # Per bank write bursts +system.physmem.perBankWrBursts::10 7202 # Per bank write bursts +system.physmem.perBankWrBursts::11 7125 # Per bank write bursts +system.physmem.perBankWrBursts::12 7069 # Per bank write bursts +system.physmem.perBankWrBursts::13 7390 # Per bank write bursts +system.physmem.perBankWrBursts::14 7350 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22274979500 # Total gap between requests +system.physmem.totGap 22293510500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165050 # Read request sizes (log2) +system.physmem.readPktSize::6 165389 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114419 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115200 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,33 +145,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,127 +194,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.896604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 200.837447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.790414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18483 35.34% 35.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10568 20.20% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5879 11.24% 66.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2936 5.61% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2943 5.63% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1490 2.85% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2026 3.87% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 952 1.82% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7027 13.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52304 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.609728 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 338.236069 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6988 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.364807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.334911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.053834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6086 87.07% 87.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.50% 87.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 455 6.51% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 219 3.13% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 100 1.43% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 53 0.76% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 22 0.31% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.10% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads -system.physmem.totQLat 5740232250 # Total ticks spent queuing -system.physmem.totMemAccLat 8834807250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34780.01 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 44806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 400.727760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 239.628821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 367.162466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13215 29.49% 29.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8315 18.56% 48.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5340 11.92% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2750 6.14% 66.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2605 5.81% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1593 3.56% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1654 3.69% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1106 2.47% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8228 18.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 44806 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.298957 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.933264 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 317.077516 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7097 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7098 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.226824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.209944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.780993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6477 91.25% 91.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 22 0.31% 91.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 336 4.73% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 168 2.37% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 66 0.93% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.38% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7098 # Writes before turning the bus around for reads +system.physmem.totQLat 5599085250 # Total ticks spent queuing +system.physmem.totMemAccLat 8699960250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33855.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53530.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 474.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 328.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 474.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 328.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52605.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 474.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 330.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 474.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 330.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes +system.physmem.busUtil 6.29 # Data bus utilization in percentage +system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.58 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing -system.physmem.readRowHits 145488 # Number of row buffer hits during reads -system.physmem.writeRowHits 81629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.34 # Row buffer hit rate for writes -system.physmem.avgGap 79704.65 # Average gap between requests -system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190428840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103904625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 635177400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368951760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6564184695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7603330500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16920459420 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.821975 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12566232250 # Time in different power states -system.physmem_0.memoryStateTime::REF 743600000 # Time in different power states +system.physmem.avgWrQLen 24.72 # Average write queue length when enqueuing +system.physmem.readRowHits 145830 # Number of row buffer hits during reads +system.physmem.writeRowHits 89913 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes +system.physmem.avgGap 79452.55 # Average gap between requests +system.physmem.pageHitRate 84.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 163424520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 89170125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636441000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 370882800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6110627715 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8015176500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16841729940 # Total energy per rank (pJ) +system.physmem_0.averagePower 755.495604 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 13256940500 # Time in different power states +system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8959159250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8290987000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204618960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111647250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371861280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6822625545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7376602500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16993402335 # Total energy per rank (pJ) -system.physmem_1.averagePower 763.098971 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12188749750 # Time in different power states -system.physmem_1.memoryStateTime::REF 743600000 # Time in different power states +system.physmem_1.actEnergy 175218120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 95605125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 653343600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 375366960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6480752940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7690505250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 16926799275 # Total energy per rank (pJ) +system.physmem_1.averagePower 759.311692 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12714890500 # Time in different power states +system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8833037000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16474744 # Number of BP lookups -system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8918177 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7235165 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16464676 # Number of BP lookups +system.cpu.branchPred.condPredicted 10658312 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 322373 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8884191 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7232535 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.128296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1973322 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3328 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39379 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31470 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7909 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2657 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 81.409044 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1975403 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3321 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39323 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31540 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7783 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2655 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22508484 # DTB read hits -system.cpu.dtb.read_misses 226837 # DTB read misses +system.cpu.dtb.read_hits 22505585 # DTB read hits +system.cpu.dtb.read_misses 226699 # DTB read misses system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22735321 # DTB read accesses -system.cpu.dtb.write_hits 15806842 # DTB write hits -system.cpu.dtb.write_misses 44564 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15851406 # DTB write accesses -system.cpu.dtb.data_hits 38315326 # DTB hits -system.cpu.dtb.data_misses 271401 # DTB misses -system.cpu.dtb.data_acv 20 # DTB access violations -system.cpu.dtb.data_accesses 38586727 # DTB accesses -system.cpu.itb.fetch_hits 13727245 # ITB hits -system.cpu.itb.fetch_misses 29559 # ITB misses +system.cpu.dtb.read_accesses 22732284 # DTB read accesses +system.cpu.dtb.write_hits 15808846 # DTB write hits +system.cpu.dtb.write_misses 44546 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 15853392 # DTB write accesses +system.cpu.dtb.data_hits 38314431 # DTB hits +system.cpu.dtb.data_misses 271245 # DTB misses +system.cpu.dtb.data_acv 22 # DTB access violations +system.cpu.dtb.data_accesses 38585676 # DTB accesses +system.cpu.itb.fetch_hits 13724143 # ITB hits +system.cpu.itb.fetch_misses 29345 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13756804 # ITB accesses +system.cpu.itb.fetch_accesses 13753488 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,142 +326,142 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44550025 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44587088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15536362 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105039044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16474744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9239957 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27563903 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 886514 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 244 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 331564 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 78 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13727245 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187963 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15537600 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105003279 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16464676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9239478 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27573681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 883330 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 330450 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13724143 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187041 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43880130 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.393772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.128235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43888428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.392505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.127693 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24375049 55.55% 55.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1515026 3.45% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1375639 3.13% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1503768 3.43% 65.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4189647 9.55% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1825739 4.16% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 668569 1.52% 80.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050805 2.39% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7375888 16.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24387762 55.57% 55.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1515251 3.45% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1377134 3.14% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1500310 3.42% 65.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4190997 9.55% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1825571 4.16% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 669926 1.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050385 2.39% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7371092 16.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43880130 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369803 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.357777 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14899233 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9760394 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18283223 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 591754 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 345526 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3700749 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99293 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103056970 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 314917 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 345526 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15243567 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4452634 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97322 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18515033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5226048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102057831 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7235 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94720 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 348136 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4717245 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61355857 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123078605 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122759511 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319093 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43888428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369270 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.355015 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14897050 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9776190 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18280655 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 589828 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 344705 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3701787 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98635 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103032848 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312916 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 344705 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15240775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4552016 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97125 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18511621 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5142186 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102032260 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5895 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 92509 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 354670 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4626637 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61342957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123044735 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122725402 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8808976 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5695 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5747 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2360993 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23135657 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16359365 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1252776 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502701 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90727911 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5569 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88607473 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70141 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11141723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4452155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 986 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43880130 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.019307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245631 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8796076 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5684 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5736 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2358572 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23134576 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16358313 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246652 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 504576 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90719727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88603709 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 68043 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11133526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4439018 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 973 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43888428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018840 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.245634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17424086 39.71% 39.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5721163 13.04% 52.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5107482 11.64% 64.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4378378 9.98% 74.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4320360 9.85% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2636536 6.01% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1944467 4.43% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1375974 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 971684 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17434377 39.72% 39.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5720394 13.03% 52.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5103914 11.63% 64.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4383916 9.99% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4317842 9.84% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2637316 6.01% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1940633 4.42% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1378295 3.14% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 971741 2.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43880130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43888428 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243434 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1167545 46.27% 55.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112329 44.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 241284 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1166228 46.24% 55.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1114848 44.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49382948 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43980 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49379489 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44005 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121151 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121171 0.14% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120663 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120707 0.14% 56.05% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39093 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39092 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -485,82 +483,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22902831 25.85% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15996653 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22899221 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15999870 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88607473 # Type of FU issued -system.cpu.iq.rate 1.988943 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2523308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223077288 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101475255 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86832445 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420100 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299852 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90825011 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305770 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1671661 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88603709 # Type of FU issued +system.cpu.iq.rate 1.987206 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2522360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223074890 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101458980 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86835527 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611359 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299878 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90820238 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305831 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1672227 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2859019 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5476 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1745988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2857938 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5878 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20874 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1744936 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3024 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 205293 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3021 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 200758 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 345526 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1271875 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2754338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100226384 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125320 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23135657 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16359365 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5569 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3722 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2752972 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 115768 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 151556 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 267324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87911556 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22736014 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 695917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 344705 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1315985 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2729229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100214269 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 118431 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23134576 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16358313 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5556 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3898 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2727794 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20874 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 113179 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 152389 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 265568 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87909421 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22732927 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 694288 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9492904 # number of nop insts executed -system.cpu.iew.exec_refs 38587764 # number of memory reference insts executed -system.cpu.iew.exec_branches 15119893 # Number of branches executed -system.cpu.iew.exec_stores 15851750 # Number of stores executed -system.cpu.iew.exec_rate 1.973322 # Inst execution rate -system.cpu.iew.wb_sent 87534383 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87132297 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33840523 # num instructions producing a value -system.cpu.iew.wb_consumers 44256350 # num instructions consuming a value -system.cpu.iew.wb_rate 1.955830 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764648 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8655398 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9488986 # number of nop insts executed +system.cpu.iew.exec_refs 38586655 # number of memory reference insts executed +system.cpu.iew.exec_branches 15119960 # Number of branches executed +system.cpu.iew.exec_stores 15853728 # Number of stores executed +system.cpu.iew.exec_rate 1.971634 # Inst execution rate +system.cpu.iew.wb_sent 87537444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87135405 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33842966 # num instructions producing a value +system.cpu.iew.wb_consumers 44247648 # num instructions consuming a value +system.cpu.iew.wb_rate 1.954274 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764853 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8653815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 226701 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42610108 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.073233 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.886041 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 225413 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42617548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.072871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.885939 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21149437 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6275459 14.73% 64.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2900348 6.81% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1740796 4.09% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1682035 3.95% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1127009 2.64% 81.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1202859 2.82% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795530 1.87% 86.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5736635 13.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21149374 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6281932 14.74% 64.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2908445 6.82% 71.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1738602 4.08% 75.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1681485 3.95% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1121192 2.63% 81.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1200701 2.82% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 796598 1.87% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5739219 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42610108 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42617548 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -606,465 +604,471 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5736635 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132552201 # The number of ROB reads -system.cpu.rob.rob_writes 195265380 # The number of ROB writes -system.cpu.timesIdled 45343 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 669895 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5739219 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132555474 # The number of ROB reads +system.cpu.rob.rob_writes 195263120 # The number of ROB writes +system.cpu.timesIdled 45271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 698660 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559732 # CPI: Total CPI of All Threads -system.cpu.ipc 1.786570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.786570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116366061 # number of integer regfile reads -system.cpu.int_regfile_writes 57668563 # number of integer regfile writes -system.cpu.fp_regfile_reads 255567 # number of floating regfile reads -system.cpu.fp_regfile_writes 240367 # number of floating regfile writes -system.cpu.misc_regfile_reads 38271 # number of misc regfile reads +system.cpu.cpi 0.560197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.560197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.785085 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.785085 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116363135 # number of integer regfile reads +system.cpu.int_regfile_writes 57669565 # number of integer regfile writes +system.cpu.fp_regfile_reads 255561 # number of floating regfile reads +system.cpu.fp_regfile_writes 240404 # number of floating regfile writes +system.cpu.misc_regfile_reads 38263 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201418 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205514 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.365026 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.642288 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993809 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 201400 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.443451 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33984025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205496 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.375603 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 232048500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.443451 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993761 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2776 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1341 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561123 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33984765 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33984765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33984765 # number of overall hits -system.cpu.dcache.overall_hits::total 33984765 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269234 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052254 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052254 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321488 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321488 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321488 # number of overall misses -system.cpu.dcache.overall_misses::total 1321488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17321162000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17321162000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89091667377 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89091667377 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106412829377 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106412829377 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106412829377 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106412829377 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20692876 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20692876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70817108 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70817108 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20422994 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20422994 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13560978 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13560978 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33983972 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33983972 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33983972 # number of overall hits +system.cpu.dcache.overall_hits::total 33983972 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269382 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269382 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052399 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052399 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321781 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321781 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321781 # number of overall misses +system.cpu.dcache.overall_misses::total 1321781 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18043068500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18043068500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88421559159 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88421559159 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106464627659 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106464627659 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106464627659 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106464627659 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20692376 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20692376 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35306253 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35306253 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35306253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35306253 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013011 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013011 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072006 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072006 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037429 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037429 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037429 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64334.972552 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64334.972552 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84667.454224 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84667.454224 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80525.006188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80525.006188 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6873080 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 89218 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35305753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35305753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35305753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35305753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072016 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037438 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037438 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037438 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037438 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80546.344409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80546.344409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6874865 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 86609 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.036921 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168806 # number of writebacks -system.cpu.dcache.writebacks::total 168806 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207108 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908866 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908866 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115974 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115974 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62126 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62126 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143388 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143388 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205514 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205514 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205514 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205514 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3205966000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3205966000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14246299714 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14246299714 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17452265714 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17452265714 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17452265714 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17452265714 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.378182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 139.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168502 # number of writebacks +system.cpu.dcache.writebacks::total 168502 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207279 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207279 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 909006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 909006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1116285 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1116285 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1116285 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1116285 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62103 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62103 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205496 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205496 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205496 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205496 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3336459000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3336459000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14128429272 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14128429272 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17464888272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17464888272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17464888272 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17464888272 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003001 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005821 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005821 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51604.255867 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51604.255867 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99354.895207 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99354.895207 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90292 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92340 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.524063 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18757985500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1916.963164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936017 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936017 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005820 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005820 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 90436 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.490065 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13619166 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 92484 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.259699 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18779712500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.490065 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935786 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935786 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 384 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1460 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 389 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27546828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27546828 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 13622372 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13622372 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13622372 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13622372 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13622372 # number of overall hits -system.cpu.icache.overall_hits::total 13622372 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 104872 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 104872 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 104872 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 104872 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 104872 # number of overall misses -system.cpu.icache.overall_misses::total 104872 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1921920999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1921920999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1921920999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1921920999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1921920999 # 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Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 168502 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168502 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 90436 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 90436 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12584 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12584 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86017 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 86017 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33990 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 33990 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86017 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46574 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132591 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86017 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46574 # number of overall hits +system.cpu.l2cache.overall_hits::total 132591 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 130811 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130811 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6468 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 6468 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28111 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 28111 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6468 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158922 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165390 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6468 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158922 # number of overall misses +system.cpu.l2cache.overall_misses::total 165390 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13777150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13777150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 548837500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 548837500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2881866500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2881866500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 548837500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16659016500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17207854000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 548837500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16659016500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17207854000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168502 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168502 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 90436 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 90436 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143395 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143395 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912242 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069936 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069936 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452666 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452666 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069936 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773358 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555035 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069936 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773358 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555035 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105321.035693 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105321.035693 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84854.282622 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84854.282622 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102517.395326 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102517.395326 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84854.282622 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104825.112319 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104044.101820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84854.282622 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104825.112319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104044.101820 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 114419 # number of writebacks -system.cpu.l2cache.writebacks::total 114419 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130780 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130780 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6407 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6407 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6407 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158644 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165051 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6407 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158644 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165051 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12586888000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12586888000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 460830500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 460830500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2469459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2469459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460830500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15056347000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15517177500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460830500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15056347000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15517177500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 115201 # number of writebacks +system.cpu.l2cache.writebacks::total 115201 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130811 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130811 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6468 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6468 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165390 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6468 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165390 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12469040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12469040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 484167500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 484167500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2600756500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2600756500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 484167500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15069796500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15553964000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 484167500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15069796500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15553964000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912052 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912052 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069384 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448530 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448530 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.554132 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.554132 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96244.746903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96244.746903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71926.096457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71926.096457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88625.430663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88625.430663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589565 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291710 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069936 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452666 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452666 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555035 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 589817 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291836 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4239 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62123 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 274973 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887419 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11688448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35644928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133082 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7322816 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 430937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009387 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.096428 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 154585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52571 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275405 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887797 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11706880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23935872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35642752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134874 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7372864 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 432855 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009793 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098475 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 426892 99.06% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4045 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428616 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4239 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 430937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553880500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432855 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553846500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138521976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 138734483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308248491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34270 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution -system.membus.trans_dist::CleanEvict 14728 # Transaction distribution -system.membus.trans_dist::ReadExReq 130780 # Transaction distribution -system.membus.trans_dist::ReadExResp 130780 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34270 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 459247 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17886016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17886016 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 130746 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34578 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115200 # Transaction distribution +system.membus.trans_dist::CleanEvict 15546 # Transaction distribution +system.membus.trans_dist::ReadExReq 130811 # Transaction distribution +system.membus.trans_dist::ReadExResp 130811 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34578 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 461524 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17957696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 294197 # Request fanout histogram +system.membus.snoop_fanout::samples 165389 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165389 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294197 # Request fanout histogram -system.membus.reqLayer0.occupancy 776999500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 165389 # Request fanout histogram +system.membus.reqLayer0.occupancy 780841500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 852713250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 854544750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 50bae5738..7abf225fd 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058768 # Number of seconds simulated -sim_ticks 58768125500 # Number of ticks simulated -final_tick 58768125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058750 # Number of seconds simulated +sim_ticks 58750410500 # Number of ticks simulated +final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140139 # Simulator instruction rate (inst/s) -host_op_rate 179217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116134728 # Simulator tick rate (ticks/s) -host_mem_usage 275656 # Number of bytes of host memory used -host_seconds 506.03 # Real time elapsed on the host +host_inst_rate 179920 # Simulator instruction rate (inst/s) +host_op_rate 230092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149057017 # Simulator tick rate (ticks/s) +host_mem_usage 281832 # Number of bytes of host memory used +host_seconds 394.15 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 285632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory -system.physmem.bytes_read::total 8210304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 285632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 285632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5517568 # Number of bytes written to this memory -system.physmem.bytes_written::total 5517568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128286 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86212 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86212 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4860322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 134846431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139706753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4860322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4860322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 93887085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 93887085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 93887085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4860322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 134846431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 233593838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128286 # Number of read requests accepted -system.physmem.writeReqs 86212 # Number of write requests accepted -system.physmem.readBursts 128286 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 86212 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8209920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5515840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8210304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5517568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory +system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory +system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128515 # Number of read requests accepted +system.physmem.writeReqs 86552 # Number of write requests accepted +system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8065 # Per bank write bursts -system.physmem.perBankRdBursts::1 8314 # Per bank write bursts -system.physmem.perBankRdBursts::2 8239 # Per bank write bursts -system.physmem.perBankRdBursts::3 8142 # Per bank write bursts -system.physmem.perBankRdBursts::4 8284 # Per bank write bursts -system.physmem.perBankRdBursts::5 8404 # Per bank write bursts -system.physmem.perBankRdBursts::6 8054 # Per bank write bursts -system.physmem.perBankRdBursts::7 7915 # Per bank write bursts -system.physmem.perBankRdBursts::8 8035 # Per bank write bursts -system.physmem.perBankRdBursts::9 7585 # Per bank write bursts -system.physmem.perBankRdBursts::10 7763 # Per bank write bursts -system.physmem.perBankRdBursts::11 7814 # Per bank write bursts -system.physmem.perBankRdBursts::12 7871 # Per bank write bursts -system.physmem.perBankRdBursts::13 7866 # Per bank write bursts -system.physmem.perBankRdBursts::14 7967 # Per bank write bursts -system.physmem.perBankRdBursts::15 7962 # Per bank write bursts -system.physmem.perBankWrBursts::0 5395 # Per bank write bursts -system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5468 # Per bank write bursts -system.physmem.perBankWrBursts::3 5336 # Per bank write bursts -system.physmem.perBankWrBursts::4 5363 # Per bank write bursts -system.physmem.perBankWrBursts::5 5561 # Per bank write bursts -system.physmem.perBankWrBursts::6 5259 # Per bank write bursts -system.physmem.perBankWrBursts::7 5180 # Per bank write bursts -system.physmem.perBankWrBursts::8 5154 # Per bank write bursts -system.physmem.perBankWrBursts::9 5103 # Per bank write bursts -system.physmem.perBankWrBursts::10 5293 # Per bank write bursts -system.physmem.perBankWrBursts::11 5270 # Per bank write bursts -system.physmem.perBankWrBursts::12 5531 # Per bank write bursts +system.physmem.perBankRdBursts::0 8086 # Per bank write bursts +system.physmem.perBankRdBursts::1 8335 # Per bank write bursts +system.physmem.perBankRdBursts::2 8257 # Per bank write bursts +system.physmem.perBankRdBursts::3 8155 # Per bank write bursts +system.physmem.perBankRdBursts::4 8301 # Per bank write bursts +system.physmem.perBankRdBursts::5 8413 # Per bank write bursts +system.physmem.perBankRdBursts::6 8070 # Per bank write bursts +system.physmem.perBankRdBursts::7 7917 # Per bank write bursts +system.physmem.perBankRdBursts::8 8053 # Per bank write bursts +system.physmem.perBankRdBursts::9 7612 # Per bank write bursts +system.physmem.perBankRdBursts::10 7771 # Per bank write bursts +system.physmem.perBankRdBursts::11 7825 # Per bank write bursts +system.physmem.perBankRdBursts::12 7888 # Per bank write bursts +system.physmem.perBankRdBursts::13 7870 # Per bank write bursts +system.physmem.perBankRdBursts::14 7981 # Per bank write bursts +system.physmem.perBankRdBursts::15 7974 # Per bank write bursts +system.physmem.perBankWrBursts::0 5399 # Per bank write bursts +system.physmem.perBankWrBursts::1 5549 # Per bank write bursts +system.physmem.perBankWrBursts::2 5476 # Per bank write bursts +system.physmem.perBankWrBursts::3 5348 # Per bank write bursts +system.physmem.perBankWrBursts::4 5387 # Per bank write bursts +system.physmem.perBankWrBursts::5 5588 # Per bank write bursts +system.physmem.perBankWrBursts::6 5325 # Per bank write bursts +system.physmem.perBankWrBursts::7 5260 # Per bank write bursts +system.physmem.perBankWrBursts::8 5187 # Per bank write bursts +system.physmem.perBankWrBursts::9 5136 # Per bank write bursts +system.physmem.perBankWrBursts::10 5306 # Per bank write bursts +system.physmem.perBankWrBursts::11 5279 # Per bank write bursts +system.physmem.perBankWrBursts::12 5541 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts -system.physmem.perBankWrBursts::14 5703 # Per bank write bursts -system.physmem.perBankWrBursts::15 5431 # Per bank write bursts +system.physmem.perBankWrBursts::14 5706 # Per bank write bursts +system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58768094000 # Total gap between requests +system.physmem.totGap 58750379000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128286 # Read request sizes (log2) +system.physmem.readPktSize::6 128515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 86212 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86552 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,106 +194,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.665026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.783131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.990632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12260 31.60% 31.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8290 21.36% 52.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4146 10.68% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2807 7.23% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2540 6.55% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 4.38% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1262 3.25% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1176 3.03% 88.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4621 11.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.212911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.385643 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5295 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.269398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.253066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.759205 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4663 88.03% 88.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.13% 88.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 496 9.36% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.30% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8 0.15% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads -system.physmem.totQLat 1679255750 # Total ticks spent queuing -system.physmem.totMemAccLat 4084505750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 641400000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13090.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads +system.physmem.totQLat 1552277750 # Total ticks spent queuing +system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31840.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 139.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 139.71 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 93.89 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.82 # Data bus utilization in percentage +system.physmem.busUtil 1.83 # Data bus utilization in percentage system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing -system.physmem.readRowHits 111800 # Number of row buffer hits during reads -system.physmem.writeRowHits 63851 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.06 # Row buffer hit rate for writes -system.physmem.avgGap 273979.68 # Average gap between requests -system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153014400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83490000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 509886000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279190800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11659704255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25030042500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41553430275 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.134890 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41510709500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1962220000 # Time in different power states +system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing +system.physmem.readRowHits 112029 # Number of row buffer hits during reads +system.physmem.writeRowHits 70027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes +system.physmem.avgGap 273172.45 # Average gap between requests +system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ) +system.physmem_0.averagePower 705.717335 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15290173000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140215320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76506375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 490152000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 279145440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11133864720 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25491305250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41449291425 # Total energy per rank (pJ) -system.physmem_1.averagePower 705.362708 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 42280803500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1962220000 # Time in different power states +system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ) +system.physmem_1.averagePower 704.382975 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14520166000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827521 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922528 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342114 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9663077 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571727 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14827613 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.008637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719937 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 176106 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158425 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 17681 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 24889 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -323,7 +321,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +351,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +381,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,16 +412,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117536251 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117500821 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179302 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.657421 # CPI: cycles per instruction -system.cpu.ipc 0.603347 # IPC: instructions per cycle +system.cpu.cpi 1.656921 # CPI: cycles per instruction +system.cpu.ipc 0.603529 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -459,474 +457,480 @@ system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 97988256 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19547995 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 156444 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.129500 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637241 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160540 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.586402 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 821026500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.129500 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993196 # Average percentage of cache occupancy +system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked +system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 156451 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2952 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86035236 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86035236 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22879875 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22879875 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642158 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83370 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83370 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522033 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522033 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605403 # number of overall hits -system.cpu.dcache.overall_hits::total 42605403 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47768 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47768 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207743 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207743 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44596 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44596 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 300107 # number of overall misses -system.cpu.dcache.overall_misses::total 300107 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1443300500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1443300500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16810663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16810663000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18253963500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18253963500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18253963500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18253963500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927643 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits +system.cpu.dcache.overall_hits::total 42605646 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses +system.cpu.dcache.overall_misses::total 299891 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127966 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127966 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777544 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777544 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905510 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905510 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002083 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002083 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348499 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348499 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005973 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005973 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006995 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006995 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30214.798610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30214.798610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80920.478668 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80920.478668 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71441.008411 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71441.008411 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60824.850803 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60824.850803 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128383 # number of writebacks -system.cpu.dcache.writebacks::total 128383 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18246 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 18246 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100706 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100706 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 118952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 118952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 118952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 118952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29522 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29522 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks +system.cpu.dcache.writebacks::total 128145 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136559 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136559 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160540 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160540 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 576668000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 576668000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488003000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488003000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1709526500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1709526500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9064671000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9064671000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10774197500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10774197500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187401 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187401 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19533.500440 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19533.500440 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79299.709446 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79299.709446 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71286.706142 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71286.706142 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66379.154798 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66379.154798 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67112.230597 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67112.230597 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 43538 # number of replacements -system.cpu.icache.tags.tagsinuse 1854.967198 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25047260 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45580 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 549.523036 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # 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Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 907 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1012 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50231262 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50231262 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25047260 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25047260 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25047260 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25047260 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25047260 # number of overall hits -system.cpu.icache.overall_hits::total 25047260 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45581 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45581 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45581 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45581 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45581 # 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number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25092841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25092841 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001816 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001816 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001816 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001816 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001816 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001816 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19884.831399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19884.831399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19884.831399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19884.831399 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits +system.cpu.icache.overall_hits::total 25047618 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # 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average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 43538 # number of writebacks -system.cpu.icache.writebacks::total 43538 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45581 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 45581 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 45581 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 45581 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 45581 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 45581 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 860790500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 860790500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 860790500 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18884.853338 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96393 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29915.680999 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 163475 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127546 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.281694 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26835.960013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1436.225853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1643.495133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.818969 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043830 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050155 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15761 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 596 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3420655 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3420655 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 128383 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128383 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 39935 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 39935 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4757 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 97176 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76442.904888 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 406103 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 200020 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 99083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 43538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38242 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 45581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 612223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5703552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24194624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96393 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5517568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 302514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.189899 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 97176 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 291272 96.28% 96.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11213 3.71% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 302514 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 374972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68384970 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240842435 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 26006 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86212 # Transaction distribution -system.membus.trans_dist::CleanEvict 6916 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26006 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 349700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13727872 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 26198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution +system.membus.trans_dist::CleanEvict 7237 # Transaction distribution +system.membus.trans_dist::ReadExReq 102317 # Transaction distribution +system.membus.trans_dist::ReadExResp 102317 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 221414 # Request fanout histogram +system.membus.snoop_fanout::samples 128515 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 221414 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 221414 # Request fanout histogram -system.membus.reqLayer0.occupancy 586752500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 128515 # Request fanout histogram +system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 676437000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 854b1472f..7d5e42cd5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033525 # Number of seconds simulated -sim_ticks 33524756000 # Number of ticks simulated -final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037283 # Number of seconds simulated +sim_ticks 37283333000 # Number of ticks simulated +final_tick 37283333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128434 # Simulator instruction rate (inst/s) -host_op_rate 164252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60722809 # Simulator tick rate (ticks/s) -host_mem_usage 277836 # Number of bytes of host memory used -host_seconds 552.10 # Real time elapsed on the host +host_inst_rate 125888 # Simulator instruction rate (inst/s) +host_op_rate 160996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66191855 # Simulator tick rate (ticks/s) +host_mem_usage 284264 # Number of bytes of host memory used +host_seconds 563.26 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory -system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory -system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 45743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 153088 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97140 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97140 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20819958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 87325080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 184105620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 292250658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20819958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20819958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 185443855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 185443855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 185443855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20819958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 87325080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 184105620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 477694513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 153089 # Number of read requests accepted -system.physmem.writeReqs 97140 # Number of write requests accepted -system.physmem.readBursts 153089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97140 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9788224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 6215872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9797696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6216960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2379328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5690752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6174592 # Number of bytes read from this memory +system.physmem.bytes_read::total 14244672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2379328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2379328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224768 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224768 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88918 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96478 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222573 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97262 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97262 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 63817470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 152635281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 165612661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 382065412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 63817470 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 63817470 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166958464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166958464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166958464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 63817470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 152635281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 165612661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 549023876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222574 # Number of read requests accepted +system.physmem.writeReqs 97262 # Number of write requests accepted +system.physmem.readBursts 222574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97262 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14235136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 6223360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14244736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9103 # Per bank write bursts -system.physmem.perBankRdBursts::1 9407 # Per bank write bursts -system.physmem.perBankRdBursts::2 9452 # Per bank write bursts -system.physmem.perBankRdBursts::3 11458 # Per bank write bursts -system.physmem.perBankRdBursts::4 10748 # Per bank write bursts -system.physmem.perBankRdBursts::5 11390 # Per bank write bursts -system.physmem.perBankRdBursts::6 10031 # Per bank write bursts -system.physmem.perBankRdBursts::7 8920 # Per bank write bursts -system.physmem.perBankRdBursts::8 9321 # Per bank write bursts -system.physmem.perBankRdBursts::9 9437 # Per bank write bursts -system.physmem.perBankRdBursts::10 9070 # Per bank write bursts -system.physmem.perBankRdBursts::11 9080 # Per bank write bursts -system.physmem.perBankRdBursts::12 8731 # Per bank write bursts -system.physmem.perBankRdBursts::13 8724 # Per bank write bursts -system.physmem.perBankRdBursts::14 9025 # Per bank write bursts -system.physmem.perBankRdBursts::15 9044 # Per bank write bursts -system.physmem.perBankWrBursts::0 5968 # Per bank write bursts -system.physmem.perBankWrBursts::1 6230 # Per bank write bursts -system.physmem.perBankWrBursts::2 6083 # Per bank write bursts -system.physmem.perBankWrBursts::3 6155 # Per bank write bursts -system.physmem.perBankWrBursts::4 6058 # Per bank write bursts -system.physmem.perBankWrBursts::5 6286 # Per bank write bursts -system.physmem.perBankWrBursts::6 6021 # Per bank write bursts -system.physmem.perBankWrBursts::7 5958 # Per bank write bursts -system.physmem.perBankWrBursts::8 5969 # Per bank write bursts -system.physmem.perBankWrBursts::9 6064 # Per bank write bursts -system.physmem.perBankWrBursts::10 6185 # Per bank write bursts -system.physmem.perBankWrBursts::11 5907 # Per bank write bursts -system.physmem.perBankWrBursts::12 6058 # Per bank write bursts -system.physmem.perBankWrBursts::13 6089 # Per bank write bursts -system.physmem.perBankWrBursts::14 6121 # Per bank write bursts -system.physmem.perBankWrBursts::15 5971 # Per bank write bursts +system.physmem.perBankRdBursts::0 9684 # Per bank write bursts +system.physmem.perBankRdBursts::1 9951 # Per bank write bursts +system.physmem.perBankRdBursts::2 12571 # Per bank write bursts +system.physmem.perBankRdBursts::3 25345 # Per bank write bursts +system.physmem.perBankRdBursts::4 17391 # Per bank write bursts +system.physmem.perBankRdBursts::5 22070 # Per bank write bursts +system.physmem.perBankRdBursts::6 11722 # Per bank write bursts +system.physmem.perBankRdBursts::7 14054 # Per bank write bursts +system.physmem.perBankRdBursts::8 11726 # Per bank write bursts +system.physmem.perBankRdBursts::9 15447 # Per bank write bursts +system.physmem.perBankRdBursts::10 11755 # Per bank write bursts +system.physmem.perBankRdBursts::11 11322 # Per bank write bursts +system.physmem.perBankRdBursts::12 9441 # Per bank write bursts +system.physmem.perBankRdBursts::13 9563 # Per bank write bursts +system.physmem.perBankRdBursts::14 9879 # Per bank write bursts +system.physmem.perBankRdBursts::15 20503 # Per bank write bursts +system.physmem.perBankWrBursts::0 5981 # Per bank write bursts +system.physmem.perBankWrBursts::1 6205 # Per bank write bursts +system.physmem.perBankWrBursts::2 6090 # Per bank write bursts +system.physmem.perBankWrBursts::3 6159 # Per bank write bursts +system.physmem.perBankWrBursts::4 6110 # Per bank write bursts +system.physmem.perBankWrBursts::5 6252 # Per bank write bursts +system.physmem.perBankWrBursts::6 5998 # Per bank write bursts +system.physmem.perBankWrBursts::7 5984 # Per bank write bursts +system.physmem.perBankWrBursts::8 5961 # Per bank write bursts +system.physmem.perBankWrBursts::9 6093 # Per bank write bursts +system.physmem.perBankWrBursts::10 6222 # Per bank write bursts +system.physmem.perBankWrBursts::11 5895 # Per bank write bursts +system.physmem.perBankWrBursts::12 6037 # Per bank write bursts +system.physmem.perBankWrBursts::13 6052 # Per bank write bursts +system.physmem.perBankWrBursts::14 6175 # Per bank write bursts +system.physmem.perBankWrBursts::15 6026 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33524744500 # Total gap between requests +system.physmem.totGap 37283321500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153089 # Read request sizes (log2) +system.physmem.readPktSize::6 222574 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97140 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97262 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 113358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,107 +198,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 166.118316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 104.810468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 234.858667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 60546 62.85% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22368 23.22% 86.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3987 4.14% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1542 1.60% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 931 0.97% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 863 0.90% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 636 0.66% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 773 0.80% 95.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4689 4.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96335 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5845 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.165269 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.412430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5844 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5845 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.616424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.570046 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.313075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4545 77.76% 77.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 48 0.82% 78.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 753 12.88% 91.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 215 3.68% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 127 2.17% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 88 1.51% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 42 0.72% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.29% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.09% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5845 # Writes before turning the bus around for reads -system.physmem.totQLat 6714977565 # Total ticks spent queuing -system.physmem.totMemAccLat 9582621315 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 764705000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43905.67 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 132565 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 154.319345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.621145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 210.186270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82651 62.35% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32256 24.33% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6354 4.79% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2721 2.05% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1163 0.88% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1002 0.76% 95.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 846 0.64% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 812 0.61% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4760 3.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132565 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.864488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.288279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5866 99.86% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 7 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.243213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4672 79.54% 79.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 38 0.65% 80.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 729 12.41% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 209 3.56% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 107 1.82% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 58 0.99% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.53% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 16 0.27% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.19% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5874 # Writes before turning the bus around for reads +system.physmem.totQLat 7261518854 # Total ticks spent queuing +system.physmem.totMemAccLat 11431968854 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32647.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62655.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 291.97 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 185.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 292.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 185.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51397.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 166.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 382.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 166.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.73 # Data bus utilization in percentage -system.physmem.busUtilRead 2.28 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.45 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.busUtil 4.29 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing -system.physmem.readRowHits 120882 # Number of row buffer hits during reads -system.physmem.writeRowHits 32837 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes -system.physmem.avgGap 133976.26 # Average gap between requests -system.physmem.pageHitRate 61.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378438480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206489250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 627572400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 315854640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15155251200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6817959750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25690916520 # Total energy per rank (pJ) -system.physmem_0.averagePower 766.433942 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11238384768 # Time in different power states -system.physmem_0.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem.readRowHits 157163 # Number of row buffer hits during reads +system.physmem.writeRowHits 29925 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.77 # Row buffer hit rate for writes +system.physmem.avgGap 116570.12 # Average gap between requests +system.physmem.pageHitRate 58.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 537077520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 293048250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 957496800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 315958320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 23206024395 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2012333250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 29756923815 # Total energy per rank (pJ) +system.physmem_0.averagePower 798.183082 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3201879547 # Time in different power states +system.physmem_0.memoryStateTime::REF 1244880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21162395232 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32834079203 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 349513920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 190707000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 564751200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313295040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13737724470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ) -system.physmem_1.averagePower 757.956338 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states -system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem_1.actEnergy 464871960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 253650375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 777051600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313949520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 21592790730 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3427453500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 29264752965 # Total energy per rank (pJ) +system.physmem_1.averagePower 784.981262 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 5568954615 # Time in different power states +system.physmem_1.memoryStateTime::REF 1244880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30467009135 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17055826 # Number of BP lookups -system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17068882 # Number of BP lookups +system.cpu.branchPred.condPredicted 11456187 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 597693 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9279962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7373647 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.457728 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1854916 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101589 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233217 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195584 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37633 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22185 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,130 +421,130 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 67049513 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 74566667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1224115 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12656 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22418203 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68072 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66043378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.665685 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.303820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5541341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87099155 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17068882 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9424147 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 65038748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1222021 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30739 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22432357 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69340 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 71233545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.545306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.327706 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20904696 31.65% 31.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8151419 12.34% 44.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9105743 13.79% 57.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27881520 42.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 26059108 36.58% 36.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8166381 11.46% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9112889 12.79% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27895167 39.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66043378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.254377 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.297952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8568047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20331818 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31035970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5662045 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 445498 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3138719 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168392 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100377883 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2807284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 445498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13201972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6021135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 843957 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31848304 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13682512 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98401933 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 864722 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3910657 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69359 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4461482 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5194138 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103316551 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453880702 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114363596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 71233545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.228908 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.168071 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8928507 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 25221623 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30949867 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5689167 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 444381 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3134053 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168503 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100299686 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2798262 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 444381 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13572247 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10675080 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 842433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31772787 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13926617 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98328841 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 859440 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4124148 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69439 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4596367 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5265270 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103255092 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453545884 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114277398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 716 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9687182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18952 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18977 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12759909 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24172969 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21779154 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1438398 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2287665 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97467378 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34812 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94518121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 609879 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6819583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18148637 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1026 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66043378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.431152 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.152558 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9625723 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18974 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19002 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12839389 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24155878 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21759886 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1433320 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2321800 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97398916 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34841 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94478155 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 593843 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6751150 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17960313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1055 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 71233545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.326316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.168839 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17971444 27.21% 27.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17366377 26.30% 53.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17018277 25.77% 79.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11635318 17.62% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2050574 3.10% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1388 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23112455 32.45% 32.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17441476 24.48% 56.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17040128 23.92% 80.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11602976 16.29% 97.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2035055 2.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1455 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66043378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 71233545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6745698 22.64% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 37 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11091756 37.22% 59.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11960162 40.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6731709 22.63% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11081856 37.26% 59.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11930481 40.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49324075 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86626 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49303920 52.19% 52.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86563 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -563,89 +565,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23968009 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21139361 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23954982 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21132627 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94518121 # Type of FU issued -system.cpu.iq.rate 1.409676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29797653 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315259 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285486823 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104332871 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93229184 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 329 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 574 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124315586 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1381077 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94478155 # Type of FU issued +system.cpu.iq.rate 1.267029 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29744084 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314825 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 290527434 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104196109 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93201296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 348 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 616 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124222040 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368179 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1306707 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11900 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1223416 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1289616 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2048 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1204148 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147221 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 186554 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 144864 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185613 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 445498 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 578203 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 566637 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97517928 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 444381 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 624509 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1115710 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97447803 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24172969 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21779154 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18892 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 562180 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11900 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250835 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 223196 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 474031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93719339 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23701905 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 798782 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24155878 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21759886 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18921 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1617 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1111435 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 249911 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221890 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 471801 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93685311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23691817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 792844 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15738 # number of nop insts executed -system.cpu.iew.exec_refs 44631646 # number of memory reference insts executed -system.cpu.iew.exec_branches 14212084 # Number of branches executed -system.cpu.iew.exec_stores 20929741 # Number of stores executed -system.cpu.iew.exec_rate 1.397763 # Inst execution rate -system.cpu.iew.wb_sent 93338125 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93229268 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44994314 # num instructions producing a value -system.cpu.iew.wb_consumers 76693481 # num instructions consuming a value -system.cpu.iew.wb_rate 1.390454 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586677 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5957514 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 14046 # number of nop insts executed +system.cpu.iew.exec_refs 44616394 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207133 # Number of branches executed +system.cpu.iew.exec_stores 20924577 # Number of stores executed +system.cpu.iew.exec_rate 1.256397 # Inst execution rate +system.cpu.iew.wb_sent 93308677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93201392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44951021 # num instructions producing a value +system.cpu.iew.wb_consumers 76633881 # num instructions consuming a value +system.cpu.iew.wb_rate 1.249907 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586569 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5894305 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 432296 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65078464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.393520 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.163869 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431064 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 70277782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.290424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.118209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31565690 48.50% 48.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16713735 25.68% 74.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4316875 6.63% 80.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4188712 6.44% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1942227 2.98% 90.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1235606 1.90% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 754913 1.16% 93.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 587526 0.90% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3773180 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 36842990 52.42% 52.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16674938 23.73% 76.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4291723 6.11% 82.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4149088 5.90% 88.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947878 2.77% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1240751 1.77% 92.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737656 1.05% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580756 0.83% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3812002 5.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65078464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 70277782 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -691,546 +693,552 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3773180 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 157925658 # The number of ROB reads -system.cpu.rob.rob_writes 194257744 # The number of ROB writes -system.cpu.timesIdled 27177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1006135 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3812002 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 163022945 # The number of ROB reads +system.cpu.rob.rob_writes 194122181 # The number of ROB writes +system.cpu.timesIdled 54257 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3333122 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.945589 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.945589 # CPI: Total CPI of All Threads -system.cpu.ipc 1.057542 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.057542 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102008139 # number of integer regfile reads -system.cpu.int_regfile_writes 56630693 # number of integer regfile writes -system.cpu.fp_regfile_reads 48 # number of floating regfile reads -system.cpu.fp_regfile_writes 42 # number of floating regfile writes -system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads -system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes -system.cpu.misc_regfile_reads 44112663 # number of misc regfile reads +system.cpu.cpi 1.051603 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051603 # CPI: Total CPI of All Threads +system.cpu.ipc 0.950930 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950930 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101976703 # number of integer regfile reads +system.cpu.int_regfile_writes 56611271 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.fp_regfile_writes 48 # number of floating regfile writes +system.cpu.cc_regfile_reads 345090037 # number of cc regfile reads +system.cpu.cc_regfile_writes 38758670 # number of cc regfile writes +system.cpu.misc_regfile_reads 44101489 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 486293 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484862 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.874566 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40338135 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485374 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.107325 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 151605500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.874566 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84467396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84467396 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21414103 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21414103 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18832546 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18832546 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60212 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60212 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15310 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15310 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40239255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40239255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40299249 # number of overall hits -system.cpu.dcache.overall_hits::total 40299249 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 567937 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 567937 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1017212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1017212 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68679 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68679 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1585149 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1585149 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1653828 # number of overall misses -system.cpu.dcache.overall_misses::total 1653828 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9485185000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9485185000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14264451930 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14264451930 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5633500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5633500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23749636930 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23749636930 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23749636930 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23749636930 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21974503 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21974503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40246649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40246649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40306861 # number of overall hits +system.cpu.dcache.overall_hits::total 40306861 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 566310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 566310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1017355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1017355 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68643 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68643 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 613 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 613 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1583665 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583665 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1652308 # number of overall misses +system.cpu.dcache.overall_misses::total 1652308 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13581553500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13581553500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13903205430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13903205430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5738500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5738500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27484758930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27484758930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27484758930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27484758930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128673 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128673 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15924 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15924 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41824404 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41824404 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41953077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41953077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025845 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025845 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051245 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.533748 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.533748 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038809 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038809 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037900 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037900 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039421 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039421 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9115.695793 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9115.695793 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14982.589605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks -system.cpu.dcache.writebacks::total 486293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1136028 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1136028 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1136028 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1136028 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 300545 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 300545 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148576 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37700 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37700 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449121 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449121 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 486821 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 486821 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3693304500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3693304500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2308719470 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2308719470 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1888982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1888982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6002023970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6002023970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7891006470 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7891006470 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013677 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013677 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010738 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010738 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011604 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325000 # number of replacements -system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy +system.cpu.dcache.demand_accesses::cpu.data 41830314 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830314 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41959169 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41959169 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051252 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051252 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532715 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532715 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037859 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037859 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039379 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039379 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9361.337684 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9361.337684 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17355.159664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16634.161990 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2820837 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 130956 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21.540342 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484862 # number of writebacks +system.cpu.dcache.writebacks::total 484862 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 267183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868792 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 868792 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 613 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 613 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1135975 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135975 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135975 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135975 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299127 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299127 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148563 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148563 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37696 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37696 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447690 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447690 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485386 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485386 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6671017500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6671017500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2276896471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2276896471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1910092000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1910092000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947913971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8947913971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10858005971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10858005971 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010703 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010703 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011568 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011568 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22301.622722 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22301.622722 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22083387 # 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number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45190725 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45190725 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22094458 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22094458 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22094458 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22094458 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22094458 # number of overall hits +system.cpu.icache.overall_hits::total 22094458 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337685 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337685 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337685 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22432143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22432143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22432143 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015054 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015054 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015054 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015054 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015054 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015054 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16485.450589 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16485.450589 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16485.450589 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16485.450589 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 546680 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 53 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25668 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325000 # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 325529 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3259633220 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3259633220 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3259633220 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3259633220 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3259633220 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3259633220 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.298114 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26.500000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 325915 # number of writebacks +system.cpu.icache.writebacks::total 325915 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 11245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 11245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 11245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 11245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326440 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 326440 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 326440 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 326440 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 326440 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 326440 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5156036946 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5156036946 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5156036946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5156036946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5156036946 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5156036946 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014552 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014552 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014552 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15794.746189 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15794.746189 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 822007 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 825699 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3235 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 128177 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 144531 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.195986 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78661 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 125486 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15697.579441 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 682126 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141813 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.810039 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 105.518503 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.969455 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006440 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.975895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 30 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16324 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680267500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680267500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2701591500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2701591500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5893524000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5893524000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2701591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6573791500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9275383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2701591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6573791500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19229866724 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033507 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.110605 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.110605 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069739 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113894 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239093 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239093 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155329 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.208431 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325529 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 338193 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976039 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1459935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2435974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41632640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62278272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103910912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318692 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6218112 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1131024 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.140178 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.373630 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297300 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73193.293592 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73558.106522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79676.925949 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1622603 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810817 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79904 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18775 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 663212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 351973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 556066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 144126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 326440 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336773 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 978779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2434413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41749696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62095104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103844800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 269627 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6225728 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1081438 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091286 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288019 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 983264 86.94% 86.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136975 12.11% 99.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10785 0.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 982719 90.87% 90.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98718 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 144751 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution -system.membus.trans_dist::CleanEvict 28117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 8337 # Transaction distribution -system.membus.trans_dist::ReadExResp 8337 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 431450 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16014592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16014592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 1081438 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1622078500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 489794228 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 728148836 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 348072 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97262 # Transaction distribution +system.membus.trans_dist::CleanEvict 28224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 8398 # Transaction distribution +system.membus.trans_dist::ReadExResp 8398 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570645 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20469440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20469440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 278362 # Request fanout histogram +system.membus.snoop_fanout::samples 222586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 278362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 278362 # Request fanout histogram -system.membus.reqLayer0.occupancy 747889943 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222586 # Request fanout histogram +system.membus.reqLayer0.occupancy 837454269 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 799798093 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1175863136 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 096e1a113..d8a41d287 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.219571 # Number of seconds simulated -sim_ticks 1219570622500 # Number of ticks simulated -final_tick 1219570622500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.222275 # Number of seconds simulated +sim_ticks 1222274983500 # Number of ticks simulated +final_tick 1222274983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 313924 # Simulator instruction rate (inst/s) -host_op_rate 313924 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209623743 # Simulator tick rate (ticks/s) -host_mem_usage 249764 # Number of bytes of host memory used -host_seconds 5817.90 # Real time elapsed on the host +host_inst_rate 407632 # Simulator instruction rate (inst/s) +host_op_rate 407632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272801132 # Simulator tick rate (ticks/s) +host_mem_usage 256700 # Number of bytes of host memory used +host_seconds 4480.46 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124970496 # Number of bytes read from this memory -system.physmem.bytes_read::total 125032128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65417280 # Number of bytes written to this memory -system.physmem.bytes_written::total 65417280 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952664 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1953627 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022145 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022145 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102470897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 102521433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 53639600 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 53639600 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 53639600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102470897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 156161033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1953627 # Number of read requests accepted -system.physmem.writeReqs 1022145 # Number of write requests accepted -system.physmem.readBursts 1953627 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1022145 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 124950016 # Total number of bytes read from DRAM +system.physmem.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 61440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126177664 # Number of bytes read from this memory +system.physmem.bytes_read::total 126239104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66092544 # Number of bytes written to this memory +system.physmem.bytes_written::total 66092544 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 960 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1971526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1972486 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032696 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032696 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103231814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103282081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54073384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54073384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54073384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103231814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157355465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1972486 # Number of read requests accepted +system.physmem.writeReqs 1032696 # Number of write requests accepted +system.physmem.readBursts 1972486 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1032696 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 126156992 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue -system.physmem.bytesWritten 65416064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125032128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65417280 # Total written bytes from the system interface side +system.physmem.bytesWritten 66090816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126239104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66092544 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118315 # Per bank write bursts -system.physmem.perBankRdBursts::1 113533 # Per bank write bursts -system.physmem.perBankRdBursts::2 115749 # Per bank write bursts -system.physmem.perBankRdBursts::3 117256 # Per bank write bursts -system.physmem.perBankRdBursts::4 117296 # Per bank write bursts -system.physmem.perBankRdBursts::5 117124 # Per bank write bursts -system.physmem.perBankRdBursts::6 119398 # Per bank write bursts -system.physmem.perBankRdBursts::7 124125 # Per bank write bursts -system.physmem.perBankRdBursts::8 126652 # Per bank write bursts -system.physmem.perBankRdBursts::9 129582 # Per bank write bursts -system.physmem.perBankRdBursts::10 128170 # Per bank write bursts -system.physmem.perBankRdBursts::11 129930 # Per bank write bursts -system.physmem.perBankRdBursts::12 125581 # Per bank write bursts -system.physmem.perBankRdBursts::13 124839 # Per bank write bursts -system.physmem.perBankRdBursts::14 122149 # Per bank write bursts -system.physmem.perBankRdBursts::15 122645 # Per bank write bursts -system.physmem.perBankWrBursts::0 61422 # Per bank write bursts -system.physmem.perBankWrBursts::1 61664 # Per bank write bursts -system.physmem.perBankWrBursts::2 60725 # Per bank write bursts -system.physmem.perBankWrBursts::3 61395 # Per bank write bursts -system.physmem.perBankWrBursts::4 61816 # Per bank write bursts -system.physmem.perBankWrBursts::5 63307 # Per bank write bursts -system.physmem.perBankWrBursts::6 64357 # Per bank write bursts -system.physmem.perBankWrBursts::7 65854 # Per bank write bursts -system.physmem.perBankWrBursts::8 65580 # Per bank write bursts -system.physmem.perBankWrBursts::9 66032 # Per bank write bursts -system.physmem.perBankWrBursts::10 65645 # Per bank write bursts -system.physmem.perBankWrBursts::11 65946 # Per bank write bursts -system.physmem.perBankWrBursts::12 64510 # Per bank write bursts -system.physmem.perBankWrBursts::13 64527 # Per bank write bursts -system.physmem.perBankWrBursts::14 64900 # Per bank write bursts -system.physmem.perBankWrBursts::15 64446 # Per bank write bursts +system.physmem.perBankRdBursts::0 119355 # Per bank write bursts +system.physmem.perBankRdBursts::1 114736 # Per bank write bursts +system.physmem.perBankRdBursts::2 116711 # Per bank write bursts +system.physmem.perBankRdBursts::3 118315 # Per bank write bursts +system.physmem.perBankRdBursts::4 118360 # Per bank write bursts +system.physmem.perBankRdBursts::5 118227 # Per bank write bursts +system.physmem.perBankRdBursts::6 120694 # Per bank write bursts +system.physmem.perBankRdBursts::7 125539 # Per bank write bursts +system.physmem.perBankRdBursts::8 127875 # Per bank write bursts +system.physmem.perBankRdBursts::9 130856 # Per bank write bursts +system.physmem.perBankRdBursts::10 129453 # Per bank write bursts +system.physmem.perBankRdBursts::11 131175 # Per bank write bursts +system.physmem.perBankRdBursts::12 126741 # Per bank write bursts +system.physmem.perBankRdBursts::13 125953 # Per bank write bursts +system.physmem.perBankRdBursts::14 123325 # Per bank write bursts +system.physmem.perBankRdBursts::15 123888 # Per bank write bursts +system.physmem.perBankWrBursts::0 62004 # Per bank write bursts +system.physmem.perBankWrBursts::1 62322 # Per bank write bursts +system.physmem.perBankWrBursts::2 61319 # Per bank write bursts +system.physmem.perBankWrBursts::3 62011 # Per bank write bursts +system.physmem.perBankWrBursts::4 62436 # Per bank write bursts +system.physmem.perBankWrBursts::5 63988 # Per bank write bursts +system.physmem.perBankWrBursts::6 65064 # Per bank write bursts +system.physmem.perBankWrBursts::7 66489 # Per bank write bursts +system.physmem.perBankWrBursts::8 66234 # Per bank write bursts +system.physmem.perBankWrBursts::9 66705 # Per bank write bursts +system.physmem.perBankWrBursts::10 66339 # Per bank write bursts +system.physmem.perBankWrBursts::11 66709 # Per bank write bursts +system.physmem.perBankWrBursts::12 65174 # Per bank write bursts +system.physmem.perBankWrBursts::13 65212 # Per bank write bursts +system.physmem.perBankWrBursts::14 65629 # Per bank write bursts +system.physmem.perBankWrBursts::15 65034 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1219570506500 # Total gap between requests +system.physmem.totGap 1222274866500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1953627 # Read request sizes (log2) +system.physmem.readPktSize::6 1972486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1022145 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1032696 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1847755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,139 +194,137 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1832533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.880589 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.106196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.417770 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1454670 79.38% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261169 14.25% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48917 2.67% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20611 1.12% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13239 0.72% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7059 0.39% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5499 0.30% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4584 0.25% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16785 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1832533 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59623 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.744209 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.154914 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59464 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 114 0.19% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 6 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1846311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.123632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.172382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 131.523418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1463397 79.26% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 266113 14.41% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48771 2.64% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20101 1.09% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12770 0.69% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7489 0.41% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5280 0.29% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4734 0.26% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17656 0.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1846311 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60557 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.510131 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.099317 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 136.122575 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60389 99.72% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 130 0.21% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 8 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 5 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 1 0.00% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3584-4095 4 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59623 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.143149 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.107238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.113236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27459 46.05% 46.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1251 2.10% 48.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26456 44.37% 92.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3936 6.60% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 436 0.73% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 70 0.12% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59623 # Writes before turning the bus around for reads -system.physmem.totQLat 36415699500 # Total ticks spent queuing -system.physmem.totMemAccLat 73022149500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9761720000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18652.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60557 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.052843 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.021089 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.041900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29161 48.15% 48.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1164 1.92% 50.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28160 46.50% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2021 3.34% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 45 0.07% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60557 # Writes before turning the bus around for reads +system.physmem.totQLat 36942736250 # Total ticks spent queuing +system.physmem.totMemAccLat 73902792500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9856015000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18741.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37402.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 102.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 53.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 102.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 53.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37491.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.22 # Data bus utilization in percentage -system.physmem.busUtilRead 0.80 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.66 # Average write queue length when enqueuing -system.physmem.readRowHits 723035 # Number of row buffer hits during reads -system.physmem.writeRowHits 418897 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.98 # Row buffer hit rate for writes -system.physmem.avgGap 409833.32 # Average gap between requests -system.physmem.pageHitRate 38.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6719093640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3666172125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7353785400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3243499200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 79656261360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 415707006375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 367085761500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 883431579600 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.380520 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 607907659750 # Time in different power states -system.physmem_0.memoryStateTime::REF 40724060000 # Time in different power states +system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing +system.physmem.readRowHits 727606 # Number of row buffer hits during reads +system.physmem.writeRowHits 429946 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes +system.physmem.avgGap 406722.41 # Average gap between requests +system.physmem.pageHitRate 38.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6766986240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3692304000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7425061800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3276501840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416045775330 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 368409693000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 885449053890 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.429872 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 610096075500 # Time in different power states +system.physmem_0.memoryStateTime::REF 40814280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 570937965250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 571360638500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7134833160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3893014125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7874240400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3379877280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 79656261360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 426752022060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 357397152750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 886087401135 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.558192 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 591710247250 # Time in different power states -system.physmem_1.memoryStateTime::REF 40724060000 # Time in different power states +system.physmem_1.actEnergy 7191102240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3923716500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7949838000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3415193280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 427319070030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 358520838000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 888152489730 # Total energy per rank (pJ) +system.physmem_1.averagePower 726.641687 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 593574305750 # Time in different power states +system.physmem_1.memoryStateTime::REF 40814280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 587134092250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 587881640500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 246937199 # Number of BP lookups -system.cpu.branchPred.condPredicted 186891611 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15587043 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168278704 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165579614 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 246953326 # Number of BP lookups +system.cpu.branchPred.condPredicted 186908369 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15587365 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 168276583 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165592346 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.396060 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18556464 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 106119 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 314 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 98.404866 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18556185 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 105918 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 63 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 252 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 453406129 # DTB read hits -system.cpu.dtb.read_misses 5001511 # DTB read misses +system.cpu.dtb.read_hits 453405484 # DTB read hits +system.cpu.dtb.read_misses 5001335 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 458407640 # DTB read accesses -system.cpu.dtb.write_hits 161376524 # DTB write hits -system.cpu.dtb.write_misses 1709205 # DTB write misses +system.cpu.dtb.read_accesses 458406819 # DTB read accesses +system.cpu.dtb.write_hits 161377349 # DTB write hits +system.cpu.dtb.write_misses 1709149 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163085729 # DTB write accesses -system.cpu.dtb.data_hits 614782653 # DTB hits -system.cpu.dtb.data_misses 6710716 # DTB misses +system.cpu.dtb.write_accesses 163086498 # DTB write accesses +system.cpu.dtb.data_hits 614782833 # DTB hits +system.cpu.dtb.data_misses 6710484 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 621493369 # DTB accesses -system.cpu.itb.fetch_hits 600073027 # ITB hits +system.cpu.dtb.data_accesses 621493317 # DTB accesses +system.cpu.itb.fetch_hits 600105517 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 600073046 # ITB accesses +system.cpu.itb.fetch_accesses 600105536 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -340,16 +338,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2439141245 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2444549967 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 55113124 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 55126564 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.335507 # CPI: cycles per instruction -system.cpu.ipc 0.748779 # IPC: instructions per cycle +system.cpu.cpi 1.338468 # CPI: cycles per instruction +system.cpu.ipc 0.747123 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction @@ -385,59 +383,59 @@ system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1826378509 # Class of committed instruction -system.cpu.tickCycles 2082121954 # Number of cycles that the object actually ticked -system.cpu.idleCycles 357019291 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9121976 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.816467 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 602780801 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126072 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 66.050410 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16880243500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.816467 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996293 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996293 # Average percentage of cache occupancy +system.cpu.tickCycles 2082292947 # Number of cycles that the object actually ticked +system.cpu.idleCycles 362257020 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9121995 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.838657 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 602779955 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126091 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 66.050180 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16887433500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.838657 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996299 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996299 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1561 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1547 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2420 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1233657814 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1233657814 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 444298266 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 444298266 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158482535 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158482535 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 602780801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 602780801 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 602780801 # number of overall hits -system.cpu.dcache.overall_hits::total 602780801 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7239103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7239103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2245967 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2245967 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9485070 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9485070 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9485070 # number of overall misses -system.cpu.dcache.overall_misses::total 9485070 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 184068939500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 184068939500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108510867000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108510867000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 292579806500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 292579806500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 292579806500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 292579806500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 451537369 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 451537369 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1233656307 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1233656307 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 444297476 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 444297476 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158482479 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158482479 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 602779955 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 602779955 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 602779955 # number of overall hits +system.cpu.dcache.overall_hits::total 602779955 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7239130 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7239130 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2246023 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2246023 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9485153 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9485153 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9485153 # number of overall misses +system.cpu.dcache.overall_misses::total 9485153 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 185791393500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 185791393500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110650401500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110650401500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296441795000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296441795000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296441795000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296441795000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 451536606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 451536606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 612265871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 612265871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 612265871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 612265871 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 612265108 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 612265108 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 612265108 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 612265108 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013974 # miss rate for WriteReq accesses @@ -446,46 +444,46 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015492 system.cpu.dcache.demand_miss_rate::total 0.015492 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015492 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015492 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25427.036955 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25427.036955 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48313.651536 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48313.651536 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30846.351846 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30846.351846 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30846.351846 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30846.351846 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25664.878722 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25664.878722 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49265.034908 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49265.034908 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31253.243358 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31253.243358 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3686661 # number of writebacks -system.cpu.dcache.writebacks::total 3686661 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 370 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 358628 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 358628 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 358998 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 358998 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 358998 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 358998 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238733 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238733 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887339 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887339 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126072 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126072 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126072 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126072 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176823131500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 176823131500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83341929000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83341929000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260165060500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260165060500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260165060500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 260165060500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3671998 # number of writebacks +system.cpu.dcache.writebacks::total 3671998 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 362 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 358700 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 358700 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 359062 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 359062 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 359062 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 359062 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238768 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238768 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887323 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126091 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126091 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126091 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126091 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 178546113500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 178546113500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85195528000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85195528000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263741641500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 263741641500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263741641500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 263741641500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -494,67 +492,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014905 system.cpu.dcache.demand_mshr_miss_rate::total 0.014905 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014905 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24427.359249 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24427.359249 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44158.430997 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44158.430997 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28507.890416 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28507.890416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28507.890416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28507.890416 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24665.262583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24665.262583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45140.936660 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45140.936660 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28899.738289 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28899.738289 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28899.738289 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28899.738289 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 752.953880 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 600072064 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 623127.792316 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 752.723923 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 600104557 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 625108.913542 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 752.953880 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367653 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367653 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 878 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1200147017 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1200147017 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 600072064 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 600072064 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 600072064 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 600072064 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 600072064 # number of overall hits -system.cpu.icache.overall_hits::total 600072064 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 963 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 963 # 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number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 600073027 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 600073027 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 600073027 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 752.723923 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.367541 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.367541 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 957 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.467285 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1200211994 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1200211994 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 600104557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 600104557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 600104557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 600104557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 600104557 # number of overall hits +system.cpu.icache.overall_hits::total 600104557 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 960 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 960 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 960 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 960 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 960 # number of overall misses +system.cpu.icache.overall_misses::total 960 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 77923500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 77923500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 77923500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 77923500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 77923500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 77923500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 600105517 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 600105517 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 600105517 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 600105517 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 600105517 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 600105517 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79261.163032 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 79261.163032 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 79261.163032 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 79261.163032 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78667.708333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88684.566676 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88679.691516 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1022145 # number of writebacks -system.cpu.l2cache.writebacks::total 1022145 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1032696 # number of writebacks +system.cpu.l2cache.writebacks::total 1032696 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780512 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 780512 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 963 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 963 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172152 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172152 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1952664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1953627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1952664 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1953627 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61012806000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61012806000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64288500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64288500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90528433000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90528433000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64288500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151541239000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 151605527500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64288500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151541239000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 151605527500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 792050 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 792050 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 960 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 960 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1179476 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1179476 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 960 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1971526 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1972486 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 960 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1971526 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1972486 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62873970500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62873970500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65921000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65921000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 92254698500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 92254698500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65921000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 155128669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 155194590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65921000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 155128669000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 155194590000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413552 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413552 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419668 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419668 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161928 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161928 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162939 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162939 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216114 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214048 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78170.234410 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78170.234410 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66758.566978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66758.566978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77232.673749 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77232.673749 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66758.566978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77607.432205 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77602.084482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66758.566978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77607.432205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77602.084482 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18249014 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121979 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216114 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79381.314942 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79381.314942 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68667.708333 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68667.708333 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78216.681391 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78216.681391 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18249049 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121998 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1272 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1439 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7239696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4708806 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7239728 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4704694 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6334072 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 963 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238733 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1929 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27376049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820014912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820076736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1920902 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65417280 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11047937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010729 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::CleanEvict 6357340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238768 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1923 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27376100 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819077696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819139328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1940039 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66092544 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11067090 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011402 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11046665 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1272 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11065651 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1439 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11047937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12811171000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1444500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11067090 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12796525500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1440000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689108000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13689136500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1173115 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1022145 # Transaction distribution -system.membus.trans_dist::CleanEvict 897727 # Transaction distribution -system.membus.trans_dist::ReadExReq 780512 # Transaction distribution -system.membus.trans_dist::ReadExResp 780512 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1173115 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5827126 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190449408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190449408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3911328 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1938842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1180436 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032696 # Transaction distribution +system.membus.trans_dist::CleanEvict 906146 # Transaction distribution +system.membus.trans_dist::ReadExReq 792050 # Transaction distribution +system.membus.trans_dist::ReadExResp 792050 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1180436 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5883814 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192331648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192331648 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3873499 # Request fanout histogram +system.membus.snoop_fanout::samples 1972486 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3873499 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1972486 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3873499 # Request fanout histogram -system.membus.reqLayer0.occupancy 8456520500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1972486 # Request fanout histogram +system.membus.reqLayer0.occupancy 8508050000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10686565250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10787775250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index cd08b0f17..7435ab9ce 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.669588 # Number of seconds simulated -sim_ticks 669587683000 # Number of ticks simulated -final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629948 # Number of seconds simulated +sim_ticks 629947889500 # Number of ticks simulated +final_tick 629947889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 209688 # Simulator instruction rate (inst/s) -host_op_rate 209688 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80876198 # Simulator tick rate (ticks/s) -host_mem_usage 251300 # Number of bytes of host memory used -host_seconds 8279.17 # Real time elapsed on the host -sim_insts 1736043781 # Number of instructions simulated -sim_ops 1736043781 # Number of ops (including micro ops) simulated +host_inst_rate 297749 # Simulator instruction rate (inst/s) +host_op_rate 297749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111692471 # Simulator tick rate (ticks/s) +host_mem_usage 257464 # Number of bytes of host memory used +host_seconds 5640.02 # Real time elapsed on the host +sim_insts 1679312925 # Number of instructions simulated +sim_ops 1679312925 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory -system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65555456 # Number of bytes written to this memory -system.physmem.bytes_written::total 65555456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960774 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961723 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1024304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1024304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 187413149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 187503855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97904214 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97904214 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97904214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 187413149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 285408070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961723 # Number of read requests accepted -system.physmem.writeReqs 1024304 # Number of write requests accepted -system.physmem.readBursts 1961723 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1024304 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125465280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84992 # Total number of bytes read from write queue -system.physmem.bytesWritten 65553920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125550272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65555456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1328 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 56512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 116052224 # Number of bytes read from this memory +system.physmem.bytes_read::total 116108736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 56512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 56512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65771840 # Number of bytes written to this memory +system.physmem.bytes_written::total 65771840 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1813316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1814199 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1027685 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1027685 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 184225118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 184314827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89709 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89709 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 104408382 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 104408382 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 104408382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 184225118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 288723209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1814199 # Number of read requests accepted +system.physmem.writeReqs 1027685 # Number of write requests accepted +system.physmem.readBursts 1814199 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1027685 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 116025984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82752 # Total number of bytes read from write queue +system.physmem.bytesWritten 65770240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 116108736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65771840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1293 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118674 # Per bank write bursts -system.physmem.perBankRdBursts::1 113905 # Per bank write bursts -system.physmem.perBankRdBursts::2 116110 # Per bank write bursts -system.physmem.perBankRdBursts::3 117640 # Per bank write bursts -system.physmem.perBankRdBursts::4 117758 # Per bank write bursts -system.physmem.perBankRdBursts::5 117504 # Per bank write bursts -system.physmem.perBankRdBursts::6 119855 # Per bank write bursts -system.physmem.perBankRdBursts::7 124644 # Per bank write bursts -system.physmem.perBankRdBursts::8 127350 # Per bank write bursts -system.physmem.perBankRdBursts::9 130115 # Per bank write bursts -system.physmem.perBankRdBursts::10 128783 # Per bank write bursts -system.physmem.perBankRdBursts::11 130505 # Per bank write bursts -system.physmem.perBankRdBursts::12 126282 # Per bank write bursts -system.physmem.perBankRdBursts::13 125429 # Per bank write bursts -system.physmem.perBankRdBursts::14 122618 # Per bank write bursts -system.physmem.perBankRdBursts::15 123223 # Per bank write bursts -system.physmem.perBankWrBursts::0 61508 # Per bank write bursts -system.physmem.perBankWrBursts::1 61766 # Per bank write bursts -system.physmem.perBankWrBursts::2 60822 # Per bank write bursts -system.physmem.perBankWrBursts::3 61512 # Per bank write bursts -system.physmem.perBankWrBursts::4 61965 # Per bank write bursts -system.physmem.perBankWrBursts::5 63432 # Per bank write bursts -system.physmem.perBankWrBursts::6 64483 # Per bank write bursts -system.physmem.perBankWrBursts::7 65996 # Per bank write bursts -system.physmem.perBankWrBursts::8 65772 # Per bank write bursts -system.physmem.perBankWrBursts::9 66160 # Per bank write bursts -system.physmem.perBankWrBursts::10 65806 # Per bank write bursts -system.physmem.perBankWrBursts::11 66084 # Per bank write bursts -system.physmem.perBankWrBursts::12 64700 # Per bank write bursts -system.physmem.perBankWrBursts::13 64663 # Per bank write bursts -system.physmem.perBankWrBursts::14 65022 # Per bank write bursts -system.physmem.perBankWrBursts::15 64589 # Per bank write bursts +system.physmem.perBankRdBursts::0 109825 # Per bank write bursts +system.physmem.perBankRdBursts::1 106113 # Per bank write bursts +system.physmem.perBankRdBursts::2 107421 # Per bank write bursts +system.physmem.perBankRdBursts::3 108541 # Per bank write bursts +system.physmem.perBankRdBursts::4 108748 # Per bank write bursts +system.physmem.perBankRdBursts::5 108721 # Per bank write bursts +system.physmem.perBankRdBursts::6 111475 # Per bank write bursts +system.physmem.perBankRdBursts::7 116266 # Per bank write bursts +system.physmem.perBankRdBursts::8 117532 # Per bank write bursts +system.physmem.perBankRdBursts::9 120021 # Per bank write bursts +system.physmem.perBankRdBursts::10 119000 # Per bank write bursts +system.physmem.perBankRdBursts::11 120366 # Per bank write bursts +system.physmem.perBankRdBursts::12 116224 # Per bank write bursts +system.physmem.perBankRdBursts::13 115367 # Per bank write bursts +system.physmem.perBankRdBursts::14 113352 # Per bank write bursts +system.physmem.perBankRdBursts::15 113934 # Per bank write bursts +system.physmem.perBankWrBursts::0 61679 # Per bank write bursts +system.physmem.perBankWrBursts::1 62003 # Per bank write bursts +system.physmem.perBankWrBursts::2 61008 # Per bank write bursts +system.physmem.perBankWrBursts::3 61698 # Per bank write bursts +system.physmem.perBankWrBursts::4 62148 # Per bank write bursts +system.physmem.perBankWrBursts::5 63666 # Per bank write bursts +system.physmem.perBankWrBursts::6 64723 # Per bank write bursts +system.physmem.perBankWrBursts::7 66137 # Per bank write bursts +system.physmem.perBankWrBursts::8 65915 # Per bank write bursts +system.physmem.perBankWrBursts::9 66335 # Per bank write bursts +system.physmem.perBankWrBursts::10 66021 # Per bank write bursts +system.physmem.perBankWrBursts::11 66389 # Per bank write bursts +system.physmem.perBankWrBursts::12 64907 # Per bank write bursts +system.physmem.perBankWrBursts::13 64927 # Per bank write bursts +system.physmem.perBankWrBursts::14 65328 # Per bank write bursts +system.physmem.perBankWrBursts::15 64776 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 669587587500 # Total gap between requests +system.physmem.totGap 629947397500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961723 # Read request sizes (log2) +system.physmem.readPktSize::6 1814199 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1024304 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1618543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241060 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1027685 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1469096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -145,29 +145,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 65120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -194,156 +194,139 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1769781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.933083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.950192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.486388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1375005 77.69% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271238 15.33% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53445 3.02% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21262 1.20% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12891 0.73% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6578 0.37% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4909 0.28% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3869 0.22% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20584 1.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1769781 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60104 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.614784 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.080179 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59932 99.71% 99.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 127 0.21% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 7 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1631200 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 111.449220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 84.546651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 143.577205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1240852 76.07% 76.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 269138 16.50% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51923 3.18% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20333 1.25% 97.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12353 0.76% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6354 0.39% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4947 0.30% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3735 0.23% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21565 1.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1631200 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60546 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.938741 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 22.568202 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 131.498063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60449 99.84% 99.84% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 61 0.10% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 7 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 2 0.00% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60104 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60104 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.041794 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.999820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.231211 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31815 52.93% 52.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1444 2.40% 55.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21085 35.08% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4727 7.86% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 762 1.27% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 188 0.31% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 35 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 13 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60104 # Writes before turning the bus around for reads -system.physmem.totQLat 40549512750 # Total ticks spent queuing -system.physmem.totMemAccLat 77306919000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9801975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20684.36 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60546 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60546 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.973210 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.937472 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.113084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 32669 53.96% 53.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1474 2.43% 56.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 22634 37.38% 93.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3027 5.00% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 624 1.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 106 0.18% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60546 # Writes before turning the bus around for reads +system.physmem.totQLat 37088946500 # Total ticks spent queuing +system.physmem.totMemAccLat 71080934000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9064530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20458.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39434.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 187.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 97.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 187.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 97.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39208.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 184.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 104.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 184.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 104.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.23 # Data bus utilization in percentage -system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.25 # Data bus utilization in percentage +system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.82 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing -system.physmem.readRowHits 792652 # Number of row buffer hits during reads -system.physmem.writeRowHits 422237 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.22 # Row buffer hit rate for writes -system.physmem.avgGap 224240.30 # Average gap between requests -system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6484506840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3538173375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7379478600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3249616320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43734125760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 304395031755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134738783250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 503519715900 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.985934 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 222173701250 # Time in different power states -system.physmem_0.memoryStateTime::REF 22358960000 # Time in different power states +system.physmem.avgWrQLen 24.61 # Average write queue length when enqueuing +system.physmem.readRowHits 781743 # Number of row buffer hits during reads +system.physmem.writeRowHits 427619 # Number of row buffer hits during writes +system.physmem.readRowHitRate 43.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.61 # Row buffer hit rate for writes +system.physmem.avgGap 221665.42 # Average gap between requests +system.physmem.pageHitRate 42.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5990438160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3268592250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6841434600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3259841760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 41145046800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 279886127580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 132453942750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 472845423900 # Total energy per rank (pJ) +system.physmem_0.averagePower 750.611658 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 218497726500 # Time in different power states +system.physmem_0.memoryStateTime::REF 21035300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 425054234250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 390413882500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6895022400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3762165000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7911430800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3387718080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43734125760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 311120339490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 128839390500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 505650192030 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.167712 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 212315780250 # Time in different power states -system.physmem_1.memoryStateTime::REF 22358960000 # Time in different power states +system.physmem_1.actEnergy 6341433840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3460107750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7299201000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3399395040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 41145046800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 287961158835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125370582000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 474976925265 # Total energy per rank (pJ) +system.physmem_1.averagePower 753.995279 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206677750500 # Time in different power states +system.physmem_1.memoryStateTime::REF 21035300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 402234088500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 409349783 # Number of BP lookups -system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282310323 # Number of BTB lookups -system.cpu.branchPred.BTBHits 278567233 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 393343738 # Number of BP lookups +system.cpu.branchPred.condPredicted 308206683 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15638618 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 270406177 # Number of BTB lookups +system.cpu.branchPred.BTBHits 266678706 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.674122 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26172089 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 12632 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1004 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 11628 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 98.621529 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24232356 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 43 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 11458 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 743 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 10715 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 54 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 644930756 # DTB read hits -system.cpu.dtb.read_misses 12159240 # DTB read misses +system.cpu.dtb.read_hits 615604408 # DTB read hits +system.cpu.dtb.read_misses 10829988 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 657089996 # DTB read accesses -system.cpu.dtb.write_hits 218090963 # DTB write hits -system.cpu.dtb.write_misses 7511655 # DTB write misses +system.cpu.dtb.read_accesses 626434396 # DTB read accesses +system.cpu.dtb.write_hits 204678819 # DTB write hits +system.cpu.dtb.write_misses 7425838 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225602618 # DTB write accesses -system.cpu.dtb.data_hits 863021719 # DTB hits -system.cpu.dtb.data_misses 19670895 # DTB misses +system.cpu.dtb.write_accesses 212104657 # DTB write accesses +system.cpu.dtb.data_hits 820283227 # DTB hits +system.cpu.dtb.data_misses 18255826 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 882692614 # DTB accesses -system.cpu.itb.fetch_hits 420612911 # ITB hits +system.cpu.dtb.data_accesses 838539053 # DTB accesses +system.cpu.itb.fetch_hits 399075166 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 420612948 # ITB accesses +system.cpu.itb.fetch_accesses 399075203 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -356,753 +339,751 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1339175367 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 23 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1259895780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 431750962 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3410040939 # Number of instructions fetch has processed -system.cpu.fetch.Branches 409349783 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 304740326 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 884658040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45380368 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 409587649 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3241372877 # Number of instructions fetch has processed +system.cpu.fetch.Branches 393343738 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 290911805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 828631431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 43212526 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1660 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 420612911 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8286314 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1339100880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.546515 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1670 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 399075166 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7874466 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1259827144 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.572871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.161590 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 714090223 53.33% 53.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47658538 3.56% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24213511 1.81% 58.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45104764 3.37% 62.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142790793 10.66% 72.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 65948937 4.92% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43596223 3.26% 80.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29427236 2.20% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226270655 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 668246093 53.04% 53.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43806893 3.48% 56.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23751936 1.89% 58.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40823777 3.24% 61.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 134784051 10.70% 72.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61318653 4.87% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43063501 3.42% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28777614 2.28% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215254626 17.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1339100880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305673 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.546374 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 353769972 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 403619551 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 524217734 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34804152 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22689471 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62026814 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256105292 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2070 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22689471 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 372006695 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212568628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 537155412 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194673252 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3173749438 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1811256 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20472342 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 148588016 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30888023 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2371822708 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4117670877 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4117534302 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136574 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 995619745 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 151 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 149 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99632674 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 717246724 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272457234 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90451892 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58631522 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2884174304 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 130 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620036143 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1544818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1148130652 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 502718906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 101 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1339100880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.956564 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.148176 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1259827144 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.312203 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.572731 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 336809889 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370413676 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 497881112 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 33116842 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21605625 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58265374 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3099960384 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1859 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21605625 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354079753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 199727925 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5296 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 510193154 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 174215391 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3021993285 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1813082 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19910474 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 129183664 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30561708 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2254247429 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3918399799 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3918272154 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 127644 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1331032194 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 923215197 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 126 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 124 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 94488821 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 681241316 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255797496 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 84438658 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55736283 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2741763403 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 107 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2499259906 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1517170 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1062450541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 465504121 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 84 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1259827144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.983812 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.153359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 535608565 40.00% 40.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169639715 12.67% 52.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 157955882 11.80% 64.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149207498 11.14% 75.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126008488 9.41% 85.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84159132 6.28% 91.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68020206 5.08% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34099830 2.55% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14401564 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 494791866 39.27% 39.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 161324184 12.81% 52.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 149742004 11.89% 63.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141543893 11.24% 75.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 119990032 9.52% 84.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80369213 6.38% 91.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 66025796 5.24% 96.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 32462182 2.58% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13577974 1.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1339100880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1259827144 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13158046 35.85% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18960543 51.65% 87.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4589272 12.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 12419183 35.12% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18417667 52.09% 87.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4521757 12.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1716921702 65.53% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 112 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896133 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 22 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671538399 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230679552 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1641003125 65.66% 65.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896111 0.04% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 23 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 640377775 25.62% 91.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 216982552 8.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620036143 # Type of FU issued -system.cpu.iq.rate 1.956455 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36707861 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014010 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6615486651 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4031199558 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2518604332 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1939194 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1248781 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 886609 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655777108 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 966896 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69396468 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2499259906 # Type of FU issued +system.cpu.iq.rate 1.983704 # Inst issue rate +system.cpu.iq.fu_busy_cnt 35358607 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014148 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6293293204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3803117225 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2401572542 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1929523 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1233317 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 883284 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2533656719 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 961794 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 60564498 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 272651061 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 372885 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 145563 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 111728732 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 251534222 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 355806 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 138747 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 101659209 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 286 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6308614 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 256 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6319064 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22689471 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149827283 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21278630 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3035173177 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6594541 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 717246724 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272457234 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 130 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 801857 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20733670 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 145563 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10633550 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8701156 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19334706 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2574881369 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 657090005 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45154774 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21605625 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 137066476 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20199207 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2888644044 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6351774 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 681241316 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255797496 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 107 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 653480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19719948 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 138747 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10434747 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8530204 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18964951 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2455710851 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 626434405 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 43549049 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 150998743 # number of nop insts executed -system.cpu.iew.exec_refs 882692691 # number of memory reference insts executed -system.cpu.iew.exec_branches 315484112 # Number of branches executed -system.cpu.iew.exec_stores 225602686 # Number of stores executed -system.cpu.iew.exec_rate 1.922737 # Inst execution rate -system.cpu.iew.wb_sent 2549313271 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2519490941 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1487485532 # num instructions producing a value -system.cpu.iew.wb_consumers 1918368513 # num instructions consuming a value -system.cpu.iew.wb_rate 1.881375 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775391 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 998632615 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15962246 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1201120469 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.515069 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.548329 # Number of insts commited each cycle +system.cpu.iew.exec_nop 146880534 # number of nop insts executed +system.cpu.iew.exec_refs 838539129 # number of memory reference insts executed +system.cpu.iew.exec_branches 303173790 # Number of branches executed +system.cpu.iew.exec_stores 212104724 # Number of stores executed +system.cpu.iew.exec_rate 1.949138 # Inst execution rate +system.cpu.iew.wb_sent 2430569294 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2402455826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1423499549 # num instructions producing a value +system.cpu.iew.wb_consumers 1834375042 # num instructions consuming a value +system.cpu.iew.wb_rate 1.906869 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.776013 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 934600585 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 23 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15637980 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1130658933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.557680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.564025 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 712379439 59.31% 59.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159650119 13.29% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79517213 6.62% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52024602 4.33% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28479101 2.37% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19489140 1.62% 87.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19970906 1.66% 89.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23045357 1.92% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106564592 8.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 654603026 57.90% 57.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 156815138 13.87% 71.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 77634971 6.87% 78.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 50637990 4.48% 83.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28095009 2.48% 85.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18859448 1.67% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19659708 1.74% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22259274 1.97% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102094369 9.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1201120469 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1819780126 # Number of instructions committed -system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1130658933 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1761204444 # Number of instructions committed +system.cpu.commit.committedOps 1761204444 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 605324165 # Number of memory references committed -system.cpu.commit.loads 444595663 # Number of loads committed +system.cpu.commit.refs 583845365 # Number of memory references committed +system.cpu.commit.loads 429707085 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 214632552 # Number of branches committed -system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. -system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction +system.cpu.commit.branches 208988363 # Number of branches committed +system.cpu.commit.fp_insts 805327 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1662744776 # Number of committed integer instructions. +system.cpu.commit.function_calls 16089601 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 81891519 4.65% 4.65% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1094662288 62.15% 66.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 66 0.00% 66.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 805058 0.05% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 429707085 24.40% 91.25% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 154138280 8.75% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106564592 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3827189418 # The number of ROB reads -system.cpu.rob.rob_writes 5774940551 # The number of ROB writes -system.cpu.timesIdled 705 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 74487 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1736043781 # Number of Instructions Simulated -system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.771395 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.771395 # CPI: Total CPI of All Threads -system.cpu.ipc 1.296353 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.296353 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3463571137 # number of integer regfile reads -system.cpu.int_regfile_writes 2019338951 # number of integer regfile writes -system.cpu.fp_regfile_reads 39668 # number of floating regfile reads -system.cpu.fp_regfile_writes 612 # number of floating regfile writes +system.cpu.commit.op_class_0::total 1761204444 # Class of committed instruction +system.cpu.commit.bw_lim_events 102094369 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3648383709 # The number of ROB reads +system.cpu.rob.rob_writes 5520911290 # The number of ROB writes +system.cpu.timesIdled 650 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1679312925 # Number of Instructions Simulated +system.cpu.committedOps 1679312925 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.750245 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750245 # CPI: Total CPI of All Threads +system.cpu.ipc 1.332898 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.332898 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3307128958 # number of integer regfile reads +system.cpu.int_regfile_writes 1925697564 # number of integer regfile writes +system.cpu.fp_regfile_reads 36300 # number of floating regfile reads +system.cpu.fp_regfile_writes 615 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9207202 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9211298 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.334011 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.451175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997913 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997913 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 8606834 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.896222 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 685926884 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 8610930 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.657701 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5135502500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.896222 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997777 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997777 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 699 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 950 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2966 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 11 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155498172 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1415363302 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1415363302 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 536911304 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 536911304 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 149015576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 149015576 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 712346620 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 712346620 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 712346620 # number of overall hits -system.cpu.dcache.overall_hits::total 712346620 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12894733 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12894733 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5230330 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5230330 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 685926880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 685926880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 685926880 # number of overall hits +system.cpu.dcache.overall_hits::total 685926880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12326597 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12326597 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5122704 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5122704 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18125063 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18125063 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18125063 # number of overall misses -system.cpu.dcache.overall_misses::total 18125063 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412093066500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412093066500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 315139193599 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 315139193599 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 85500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 727232260099 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 727232260099 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 727232260099 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 727232260099 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 569743181 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 569743181 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17449301 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17449301 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17449301 # number of overall misses +system.cpu.dcache.overall_misses::total 17449301 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 397459380500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 397459380500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 314315569058 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 314315569058 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 73500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 73500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 711774949558 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 711774949558 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 711774949558 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 711774949558 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549237901 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549237901 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 154138280 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 154138280 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 730471683 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 730471683 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 730471683 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 730471683 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022633 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022633 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032541 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032541 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 703376181 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 703376181 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 703376181 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 703376181 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022443 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022443 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.033234 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024813 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024813 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31958.247332 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31958.247332 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60252.258194 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60252.258194 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40123.019716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40123.019716 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15672953 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9573691 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1104455 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 68040 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.190667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 140.706805 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3727750 # number of writebacks -system.cpu.dcache.writebacks::total 3727750 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5562625 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5562625 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3351141 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3351141 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8913766 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8913766 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8913766 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8913766 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7332108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879189 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879189 # number of WriteReq MSHR misses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024808 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024808 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024808 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024808 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32244.047607 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32244.047607 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61357.355228 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61357.355228 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 73500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 73500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40791.029369 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40791.029369 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40791.029369 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40791.029369 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16026921 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9753373 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1104089 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 68174 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.515968 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 143.065876 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3596228 # number of writebacks +system.cpu.dcache.writebacks::total 3596228 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5571741 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5571741 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3266630 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3266630 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8838371 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8838371 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8838371 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8838371 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 6754856 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 6754856 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1856074 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1856074 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9211297 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9211297 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9211297 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9211297 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182971511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 182971511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84313777567 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84313777567 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267285289067 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 267285289067 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267285289067 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 267285289067 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 8610930 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8610930 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8610930 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8610930 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 164940989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 164940989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84797281851 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84797281851 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 72500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 72500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 249738270851 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 249738270851 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 249738270851 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 249738270851 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012299 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012299 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.012042 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.012042 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.830384 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.830384 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44867.108932 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44867.108932 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 443215.407798 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012242 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012242 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012242 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012242 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24418.135487 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24418.135487 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45686.369105 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45686.369105 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 72500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 72500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29002.473699 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29002.473699 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29002.473699 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29002.473699 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 744.964371 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 399073789 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 883 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 451952.195923 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 753.790798 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.368062 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.368062 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses -system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420611422 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420611422 # number of overall hits -system.cpu.icache.overall_hits::total 420611422 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses -system.cpu.icache.overall_misses::total 1489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114620499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114620499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114620499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114620499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114620499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114620499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420612911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420612911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420612911 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420612911 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420612911 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420612911 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # 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number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 399073789 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 399073789 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 399073789 # number of overall hits +system.cpu.icache.overall_hits::total 399073789 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1377 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1377 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1377 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1377 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1377 # number of overall misses +system.cpu.icache.overall_misses::total 1377 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 106712499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 106712499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 106712499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 106712499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 106712499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 106712499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 399075166 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 399075166 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 399075166 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 399075166 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 399075166 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 399075166 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77496.368192 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77496.368192 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77496.368192 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77496.368192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77496.368192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77496.368192 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 390 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 130 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 540 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 540 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 540 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 540 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 949 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 949 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 949 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 949 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79774499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 79774499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79774499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 79774499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79774499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 79774499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 494 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 494 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 494 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 494 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 494 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 494 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 883 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 883 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 883 # 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mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84061.642782 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84061.642782 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1929018 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958805 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.443396 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28140218000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14352.619403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.692409 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17030.315030 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.438007 # 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Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1106786 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1106786 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6143738 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6143738 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7250524 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7250524 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7250524 # 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number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332093 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7332093 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 949 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9211298 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9212247 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 949 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9211298 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9212247 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411035 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411035 # miss rate for ReadExReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85009.625142 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22514 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5526 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139563701 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139563701 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3596228 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3596228 # number of WritebackDirty hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1089344 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1089344 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5708271 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89669.259116 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82552.687039 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89672.703483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89669.259116 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.210583 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.210664 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91318.006638 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91318.006638 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83501.698754 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83501.698754 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89770.039969 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89770.039969 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83501.698754 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90424.584297 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 90421.214817 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83501.698754 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90424.584297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 90421.214817 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1024304 # number of writebacks -system.cpu.l2cache.writebacks::total 1024304 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772419 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 772419 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188355 # 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number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 164 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 164 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 766745 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 766745 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 883 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 883 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1046571 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1046571 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 883 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1813316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1814199 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145835185500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145900087500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64902000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145835185500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145900087500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411035 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411035 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413097 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413097 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162076 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162076 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.154936 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.154936 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212866 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212947 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79631.695495 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18419450 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207203 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.210583 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80421.214817 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73501.698754 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80424.584297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80421.214817 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 17218648 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 8606834 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1383 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1383 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6384166 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332093 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629798 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27631697 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828099072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 828159872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1929018 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65555456 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11141265 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000114 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010697 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 6755724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4623913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5764670 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1856089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1856089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6754842 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1766 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 25828695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 25830461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 781258112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 781314624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1781749 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 65771840 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 10393563 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000133 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011535 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11139990 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1275 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10392180 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1383 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11141265 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12937476000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10393563 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12205552000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1423999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1324500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12916395000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1189304 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution -system.membus.trans_dist::CleanEvict 903679 # Transaction distribution -system.membus.trans_dist::ReadExReq 772419 # Transaction distribution -system.membus.trans_dist::ReadExResp 772419 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189304 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851429 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5851429 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191105728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191105728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3594729 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1780530 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1047454 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1027685 # Transaction distribution +system.membus.trans_dist::CleanEvict 752845 # Transaction distribution +system.membus.trans_dist::ReadExReq 766745 # Transaction distribution +system.membus.trans_dist::ReadExResp 766745 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1047454 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5408928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5408928 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 181880576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 181880576 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3889706 # Request fanout histogram +system.membus.snoop_fanout::samples 1814199 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3889706 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1814199 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3889706 # Request fanout histogram -system.membus.reqLayer0.occupancy 8475680000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1814199 # Request fanout histogram +system.membus.reqLayer0.occupancy 8122837000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 10684396000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9853981000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 9e88e1d85..5f8a25a7f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2010513 # Simulator instruction rate (inst/s) -host_op_rate 2010513 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1008901575 # Simulator tick rate (ticks/s) -host_mem_usage 239516 # Number of bytes of host memory used -host_seconds 905.13 # Real time elapsed on the host +host_inst_rate 1729437 # Simulator instruction rate (inst/s) +host_op_rate 1729437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 867853739 # Simulator tick rate (ticks/s) +host_mem_usage 243124 # Number of bytes of host memory used +host_seconds 1052.24 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 10108087278 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram -system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram -system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2431702674 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2431702674 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 6bd6eda32..622e92943 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.636720 # Number of seconds simulated -sim_ticks 2636719559500 # Number of ticks simulated -final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.639614 # Number of seconds simulated +sim_ticks 2639613874500 # Number of ticks simulated +final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1223384 # Simulator instruction rate (inst/s) -host_op_rate 1223384 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1772587765 # Simulator tick rate (ticks/s) -host_mem_usage 249508 # Number of bytes of host memory used -host_seconds 1487.50 # Real time elapsed on the host +host_inst_rate 1111155 # Simulator instruction rate (inst/s) +host_op_rate 1111155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1611744129 # Simulator tick rate (ticks/s) +host_mem_usage 254908 # Number of bytes of host memory used +host_seconds 1637.74 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory -system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126106432 # Number of bytes read from this memory +system.physmem.bytes_read::total 126157760 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory -system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 66087296 # Number of bytes written to this memory +system.physmem.bytes_written::total 66087296 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 1970413 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1971215 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032614 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032614 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47774575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47794021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25036729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25036729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25036729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47774575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72830749 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5273439119 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 2639613874500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5279227749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -92,7 +92,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5273439119 # Number of busy cycles +system.cpu.num_busy_cycles 5279227749 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -131,26 +131,26 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4079.303630 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 41048093500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.303630 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995924 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2646 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -167,14 +167,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152711735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152711735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64261460000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64261460000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 216973195000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 216973195000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 216973195000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 216973195000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -191,22 +191,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21144.140311 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21144.140311 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34013.009972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34013.009972 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23812.503196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23812.503196 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks -system.cpu.dcache.writebacks::total 3679426 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3664823 # number of writebacks +system.cpu.dcache.writebacks::total 3664823 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -215,14 +215,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145489321000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 145489321000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62372140000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62372140000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207861461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207861461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207861461000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207861461000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -231,24 +231,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20144.140311 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20144.140311 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33013.009972 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33013.009972 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.633318 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 612.633318 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299137 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -256,7 +256,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 730 system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -269,12 +269,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50541500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50541500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50541500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50541500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50541500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50541500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -287,12 +287,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63019.326683 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63019.326683 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63019.326683 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63019.326683 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,86 +307,86 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 48957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 48957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48957500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 48957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49739500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49739500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49739500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49739500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49739500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49739500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1919525 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1949317 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.377074 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218471945000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.824340 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.460561 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001185 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.470286 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.932032 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1058 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62019.326683 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62019.326683 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1938767 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31260.683710 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16248398 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1971535 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.241496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 217871689000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8.109026 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.419408 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31214.155276 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000247 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001172 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.952580 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.954000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 664 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1281 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27794 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 147732935 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 147732935 # 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miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161865 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161865 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162883 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162883 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214168 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214237 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.216250 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.216319 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216319 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50509.975062 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50509.975062 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.002550 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.002550 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1292 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1292 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4697437 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6348968 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution @@ -504,53 +504,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919525 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65405568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 817699648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 817751040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1938767 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66087296 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11051303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000117 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010812 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11050011 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1292 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11051303 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12774911500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1169857 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution -system.membus.trans_dist::CleanEvict 896683 # Transaction distribution -system.membus.trans_dist::ReadExReq 782385 # Transaction distribution -system.membus.trans_dist::ReadExResp 782385 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3908932 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1937717 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1177209 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032614 # Transaction distribution +system.membus.trans_dist::CleanEvict 905103 # Transaction distribution +system.membus.trans_dist::ReadExReq 794006 # Transaction distribution +system.membus.trans_dist::ReadExResp 794006 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1177209 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5880147 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5880147 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192245056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192245056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3870887 # Request fanout histogram +system.membus.snoop_fanout::samples 1971215 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1971215 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870887 # Request fanout histogram -system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1971215 # Request fanout histogram +system.membus.reqLayer0.occupancy 8039396000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9856075000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index a63511156..ddbab1eb8 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.128034 # Number of seconds simulated -sim_ticks 1128033563500 # Number of ticks simulated -final_tick 1128033563500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.130744 # Number of seconds simulated +sim_ticks 1130744162500 # Number of ticks simulated +final_tick 1130744162500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 296898 # Simulator instruction rate (inst/s) -host_op_rate 319862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216832014 # Simulator tick rate (ticks/s) -host_mem_usage 266856 # Number of bytes of host memory used -host_seconds 5202.34 # Real time elapsed on the host +host_inst_rate 210155 # Simulator instruction rate (inst/s) +host_op_rate 226410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153850224 # Simulator tick rate (ticks/s) +host_mem_usage 274312 # Number of bytes of host memory used +host_seconds 7349.64 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130888128 # Number of bytes read from this memory -system.physmem.bytes_read::total 130938240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67194432 # Number of bytes written to this memory -system.physmem.bytes_written::total 67194432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2045910 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1049913 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1049913 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 116032122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116076546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 59567759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59567759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59567759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 116032122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 175644306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2045910 # Number of read requests accepted -system.physmem.writeReqs 1049913 # Number of write requests accepted -system.physmem.readBursts 2045910 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1049913 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130851840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86400 # Total number of bytes read from write queue -system.physmem.bytesWritten 67192960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130938240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67194432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1350 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132094976 # Number of bytes read from this memory +system.physmem.bytes_read::total 132145216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67850112 # Number of bytes written to this memory +system.physmem.bytes_written::total 67850112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2063984 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064769 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060158 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060158 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 44431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 116821276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116865707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60004831 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60004831 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60004831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 116821276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 176870538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064769 # Number of read requests accepted +system.physmem.writeReqs 1060158 # Number of write requests accepted +system.physmem.readBursts 2064769 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060158 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132060352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue +system.physmem.bytesWritten 67848640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132145216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67850112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127234 # Per bank write bursts -system.physmem.perBankRdBursts::1 124635 # Per bank write bursts -system.physmem.perBankRdBursts::2 121565 # Per bank write bursts -system.physmem.perBankRdBursts::3 123578 # Per bank write bursts -system.physmem.perBankRdBursts::4 122544 # Per bank write bursts -system.physmem.perBankRdBursts::5 122632 # Per bank write bursts -system.physmem.perBankRdBursts::6 123221 # Per bank write bursts -system.physmem.perBankRdBursts::7 123735 # Per bank write bursts -system.physmem.perBankRdBursts::8 131340 # Per bank write bursts -system.physmem.perBankRdBursts::9 133478 # Per bank write bursts -system.physmem.perBankRdBursts::10 132036 # Per bank write bursts -system.physmem.perBankRdBursts::11 133242 # Per bank write bursts -system.physmem.perBankRdBursts::12 133211 # Per bank write bursts -system.physmem.perBankRdBursts::13 133326 # Per bank write bursts -system.physmem.perBankRdBursts::14 129274 # Per bank write bursts -system.physmem.perBankRdBursts::15 129509 # Per bank write bursts -system.physmem.perBankWrBursts::0 66120 # Per bank write bursts -system.physmem.perBankWrBursts::1 64398 # Per bank write bursts -system.physmem.perBankWrBursts::2 62563 # Per bank write bursts -system.physmem.perBankWrBursts::3 62980 # Per bank write bursts -system.physmem.perBankWrBursts::4 62981 # Per bank write bursts -system.physmem.perBankWrBursts::5 63086 # Per bank write bursts -system.physmem.perBankWrBursts::6 64437 # Per bank write bursts -system.physmem.perBankWrBursts::7 65431 # Per bank write bursts -system.physmem.perBankWrBursts::8 67296 # Per bank write bursts -system.physmem.perBankWrBursts::9 67792 # Per bank write bursts -system.physmem.perBankWrBursts::10 67535 # Per bank write bursts -system.physmem.perBankWrBursts::11 67858 # Per bank write bursts -system.physmem.perBankWrBursts::12 67312 # Per bank write bursts -system.physmem.perBankWrBursts::13 67784 # Per bank write bursts -system.physmem.perBankWrBursts::14 66474 # Per bank write bursts -system.physmem.perBankWrBursts::15 65843 # Per bank write bursts +system.physmem.perBankRdBursts::0 128520 # Per bank write bursts +system.physmem.perBankRdBursts::1 125806 # Per bank write bursts +system.physmem.perBankRdBursts::2 122672 # Per bank write bursts +system.physmem.perBankRdBursts::3 124571 # Per bank write bursts +system.physmem.perBankRdBursts::4 123572 # Per bank write bursts +system.physmem.perBankRdBursts::5 123679 # Per bank write bursts +system.physmem.perBankRdBursts::6 124365 # Per bank write bursts +system.physmem.perBankRdBursts::7 124958 # Per bank write bursts +system.physmem.perBankRdBursts::8 132489 # Per bank write bursts +system.physmem.perBankRdBursts::9 134780 # Per bank write bursts +system.physmem.perBankRdBursts::10 133233 # Per bank write bursts +system.physmem.perBankRdBursts::11 134506 # Per bank write bursts +system.physmem.perBankRdBursts::12 134518 # Per bank write bursts +system.physmem.perBankRdBursts::13 134594 # Per bank write bursts +system.physmem.perBankRdBursts::14 130540 # Per bank write bursts +system.physmem.perBankRdBursts::15 130640 # Per bank write bursts +system.physmem.perBankWrBursts::0 66781 # Per bank write bursts +system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::2 63173 # Per bank write bursts +system.physmem.perBankWrBursts::3 63584 # Per bank write bursts +system.physmem.perBankWrBursts::4 63558 # Per bank write bursts +system.physmem.perBankWrBursts::5 63644 # Per bank write bursts +system.physmem.perBankWrBursts::6 65047 # Per bank write bursts +system.physmem.perBankWrBursts::7 66055 # Per bank write bursts +system.physmem.perBankWrBursts::8 67972 # Per bank write bursts +system.physmem.perBankWrBursts::9 68438 # Per bank write bursts +system.physmem.perBankWrBursts::10 68161 # Per bank write bursts +system.physmem.perBankWrBursts::11 68586 # Per bank write bursts +system.physmem.perBankWrBursts::12 68040 # Per bank write bursts +system.physmem.perBankWrBursts::13 68530 # Per bank write bursts +system.physmem.perBankWrBursts::14 67159 # Per bank write bursts +system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1128033469500 # Total gap between requests +system.physmem.totGap 1130744067500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2045910 # Read request sizes (log2) +system.physmem.readPktSize::6 2064769 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1049913 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1917702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126844 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060158 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1931837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131592 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,113 +194,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910047 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.685692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.490486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485463 77.77% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305174 15.98% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52509 2.75% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20929 1.10% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13256 0.69% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7619 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5519 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5102 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14476 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910047 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61113 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.412400 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.518866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61065 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 24 0.04% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1925169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.839212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.850367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 126.421931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1496084 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 309482 16.08% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52255 2.71% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20716 1.08% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12793 0.66% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7748 0.40% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5753 0.30% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5054 0.26% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15284 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1925169 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.244314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.928422 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.698604 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61952 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61113 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.179487 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.144319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.100540 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26981 44.15% 44.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1028 1.68% 45.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28814 47.15% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3825 6.26% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 400 0.65% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 47 0.08% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61113 # Writes before turning the bus around for reads -system.physmem.totQLat 38097515250 # Total ticks spent queuing -system.physmem.totMemAccLat 76433015250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10222800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18633.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.101710 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.070337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.034747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 28322 45.69% 45.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1015 1.64% 47.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 30732 49.58% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1873 3.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 43 0.07% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61990 # Writes before turning the bus around for reads +system.physmem.totQLat 38536102500 # Total ticks spent queuing +system.physmem.totMemAccLat 77225658750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18675.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37383.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 59.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.08 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37425.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.37 # Data bus utilization in percentage +system.physmem.busUtil 1.38 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 772369 # Number of row buffer hits during reads -system.physmem.writeRowHits 412032 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.24 # Row buffer hit rate for writes -system.physmem.avgGap 364372.73 # Average gap between requests -system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7040703600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3841653750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7715315400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3317734080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 423036881190 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 305734953750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 824364871770 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.798394 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 505893058250 # Time in different power states -system.physmem_0.memoryStateTime::REF 37667500000 # Time in different power states +system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing +system.physmem.readRowHits 775929 # Number of row buffer hits during reads +system.physmem.writeRowHits 422476 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.85 # Row buffer hit rate for writes +system.physmem.avgGap 361846.55 # Average gap between requests +system.physmem.pageHitRate 38.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7091695800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3869476875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7785421800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3348753840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 423921506085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 306584736000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 826456199280 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.896688 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 507283799000 # Time in different power states +system.physmem_0.memoryStateTime::REF 37757980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 584472684250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 585701078500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7399251720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4037290125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8232221400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3485553120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 432494110575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 297439138500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 826765195440 # Total energy per rank (pJ) -system.physmem_1.averagePower 732.926278 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 492041493250 # Time in different power states -system.physmem_1.memoryStateTime::REF 37667500000 # Time in different power states +system.physmem_1.actEnergy 7462581840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4071845250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8309316600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3520920960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 432965070225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 298651785000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 828836128755 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.001436 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 494051909000 # Time in different power states +system.physmem_1.memoryStateTime::REF 37757980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 598324400250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 598934101500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019627 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610234 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019432 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610009 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131647639 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324320 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131647101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324380 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.917975 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657430 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.918400 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 534 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 302 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,16 +419,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2256067127 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2261488325 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363716 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363718 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.460651 # CPI: cycles per instruction -system.cpu.ipc 0.684626 # IPC: instructions per cycle +system.cpu.cpi 1.464161 # CPI: cycles per instruction +system.cpu.ipc 0.682985 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -466,61 +464,61 @@ system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1844612574 # Number of cycles that the object actually ticked -system.cpu.idleCycles 411454553 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220101 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.702912 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624495427 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701874 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9818932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.702912 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997486 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997486 # Average percentage of cache occupancy +system.cpu.tickCycles 1844743027 # Number of cycles that the object actually ticked +system.cpu.idleCycles 416745298 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220102 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.712457 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624495296 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224198 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.701853 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9823555500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.712457 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997488 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997488 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1240 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391791 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391791 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454164210 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454164210 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331094 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331094 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391740 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391740 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454164183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454164183 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170330990 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170330990 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624495304 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624495304 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624495305 # number of overall hits -system.cpu.dcache.overall_hits::total 624495305 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333415 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333415 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254953 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254953 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624495173 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624495173 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624495174 # number of overall hits +system.cpu.dcache.overall_hits::total 624495174 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333416 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333416 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2255057 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2255057 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9588368 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9588368 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9588370 # number of overall misses -system.cpu.dcache.overall_misses::total 9588370 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190988166000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190988166000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108977258000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108977258000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 299965424000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 299965424000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 299965424000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 299965424000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9588473 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9588473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9588475 # number of overall misses +system.cpu.dcache.overall_misses::total 9588475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192638967000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 111261397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 303900364000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 303900364000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 303900364000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 303900364000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497599 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -529,10 +527,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083672 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083672 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083675 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083675 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083646 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083646 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083649 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083649 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -543,50 +541,50 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26043.550788 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26043.550788 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48327.950960 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48327.950960 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.304482 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31284.304482 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.297957 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31284.297957 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31694.344240 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31694.337629 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3684499 # number of writebacks -system.cpu.dcache.writebacks::total 3684499 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670051 # number of writebacks +system.cpu.dcache.writebacks::total 3670051 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364123 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364123 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364172 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364172 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364172 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364172 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333366 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333366 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364227 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364227 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364276 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364276 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364276 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364276 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333367 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333367 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224196 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224196 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224197 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183652478000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183652478000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84692070000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84692070000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268344548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268344548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268344622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268344622000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224198 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224198 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86626211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86626211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 271929707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 271929782500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -597,338 +595,344 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25043.408170 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.408170 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44790.948948 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44790.948948 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.375335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.375335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.380204 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.380204 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 30 # number of replacements -system.cpu.icache.tags.tagsinuse 660.287317 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466254411 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 569297.205128 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 33 # number of replacements +system.cpu.icache.tags.tagsinuse 660.343836 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466264831 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 567232.154501 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.287317 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322406 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322406 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.343836 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322434 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322434 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932511279 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932511279 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466254411 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466254411 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466254411 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61690000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61690000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466255230 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466255230 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466255230 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466255230 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466255230 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466255230 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 932532128 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932532128 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466264831 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466264831 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466264831 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466264831 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466264831 # number of overall hits +system.cpu.icache.overall_hits::total 466264831 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses +system.cpu.icache.overall_misses::total 822 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62977000 # 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number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75323.565324 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75323.565324 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75323.565324 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75323.565324 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76614.355231 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76614.355231 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76614.355231 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 30 # number of writebacks -system.cpu.icache.writebacks::total 30 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60871000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 60871000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60871000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 60871000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60871000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 60871000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 33 # number of writebacks +system.cpu.icache.writebacks::total 33 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 822 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 822 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 822 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62155000 # 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mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74323.565324 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74323.565324 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2013239 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31266.385554 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14508014 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2043015 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.101276 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 59831992000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14855.828649 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.313947 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16384.242958 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.453364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.500007 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.954174 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12853 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151482269 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151482269 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3684499 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3684499 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 30 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 30 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1089818 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1089818 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089246 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6089246 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7179064 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7179100 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7179064 # number of overall hits -system.cpu.l2cache.overall_hits::total 7179100 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 801012 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75614.355231 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2032337 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31884.361365 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16378235 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2065105 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.930945 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 54418076000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 10.408988 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.813492 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31848.138885 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000318 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000788 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.971928 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.973033 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 912 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2876 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7195 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21737 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149613593 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423630 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169651 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169651 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.221778 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.221778 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77875.455049 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77875.455049 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65647.509579 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65647.509579 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77380.803222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77380.803222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445147 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220143 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223823 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223823 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445155 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220147 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1285 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1445 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4734412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6498928 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333367 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1668 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670163 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826156544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 826210880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013239 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67194432 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11238255 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016087 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333368 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825231936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825286656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032337 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67850112 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257357 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016509 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11235364 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2885 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254306 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3045 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11238255 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12907102500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257357 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892661500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836298494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836299994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1244898 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1049913 # Transaction distribution -system.membus.trans_dist::CleanEvict 962255 # Transaction distribution -system.membus.trans_dist::ReadExReq 801012 # Transaction distribution -system.membus.trans_dist::ReadExResp 801012 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1244898 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6103988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6103988 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198132672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198132672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 4095876 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252445 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060158 # Transaction distribution +system.membus.trans_dist::CleanEvict 970949 # Transaction distribution +system.membus.trans_dist::ReadExReq 812324 # Transaction distribution +system.membus.trans_dist::ReadExResp 812324 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252445 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160645 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199995328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4058078 # Request fanout histogram +system.membus.snoop_fanout::samples 2064769 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4058078 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064769 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4058078 # Request fanout histogram -system.membus.reqLayer0.occupancy 8755432500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064769 # Request fanout histogram +system.membus.reqLayer0.occupancy 8803577000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11187827500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11289358000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 3edaccc65..4f03996ba 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767804 # Number of seconds simulated -sim_ticks 767803843500 # Number of ticks simulated -final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770752 # Number of seconds simulated +sim_ticks 770752376500 # Number of ticks simulated +final_tick 770752376500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212750 # Simulator instruction rate (inst/s) -host_op_rate 229206 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 105758139 # Simulator tick rate (ticks/s) -host_mem_usage 308972 # Number of bytes of host memory used -host_seconds 7260.00 # Real time elapsed on the host +host_inst_rate 147248 # Simulator instruction rate (inst/s) +host_op_rate 158637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73478006 # Simulator tick rate (ticks/s) +host_mem_usage 329736 # Number of bytes of host memory used +host_seconds 10489.57 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory -system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory -system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4673385 # Number of read requests accepted -system.physmem.writeReqs 1635896 # Number of write requests accepted -system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue -system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236002624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63781504 # Number of bytes read from this memory +system.physmem.bytes_read::total 299849792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104607936 # Number of bytes written to this memory +system.physmem.bytes_written::total 104607936 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3687541 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996586 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4685153 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634499 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634499 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306197725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82752264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389035183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 135721847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 135721847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 135721847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306197725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82752264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 524757030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4685154 # Number of read requests accepted +system.physmem.writeReqs 1634499 # Number of write requests accepted +system.physmem.readBursts 4685154 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634499 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299347712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 502144 # Total number of bytes read from write queue +system.physmem.bytesWritten 104604544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299849856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104607936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7846 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301126 # Per bank write bursts -system.physmem.perBankRdBursts::1 298685 # Per bank write bursts -system.physmem.perBankRdBursts::2 284250 # Per bank write bursts -system.physmem.perBankRdBursts::3 287696 # Per bank write bursts -system.physmem.perBankRdBursts::4 287908 # Per bank write bursts -system.physmem.perBankRdBursts::5 285921 # Per bank write bursts -system.physmem.perBankRdBursts::6 280645 # Per bank write bursts -system.physmem.perBankRdBursts::7 277366 # Per bank write bursts -system.physmem.perBankRdBursts::8 293768 # Per bank write bursts -system.physmem.perBankRdBursts::9 299240 # Per bank write bursts -system.physmem.perBankRdBursts::10 292091 # Per bank write bursts -system.physmem.perBankRdBursts::11 297828 # Per bank write bursts -system.physmem.perBankRdBursts::12 299005 # Per bank write bursts -system.physmem.perBankRdBursts::13 298032 # Per bank write bursts -system.physmem.perBankRdBursts::14 293386 # Per bank write bursts -system.physmem.perBankRdBursts::15 288652 # Per bank write bursts -system.physmem.perBankWrBursts::0 103980 # Per bank write bursts -system.physmem.perBankWrBursts::1 101811 # Per bank write bursts -system.physmem.perBankWrBursts::2 99205 # Per bank write bursts -system.physmem.perBankWrBursts::3 99712 # Per bank write bursts -system.physmem.perBankWrBursts::4 99000 # Per bank write bursts -system.physmem.perBankWrBursts::5 99026 # Per bank write bursts -system.physmem.perBankWrBursts::6 102693 # Per bank write bursts -system.physmem.perBankWrBursts::7 104157 # Per bank write bursts -system.physmem.perBankWrBursts::8 105172 # Per bank write bursts -system.physmem.perBankWrBursts::9 104159 # Per bank write bursts -system.physmem.perBankWrBursts::10 102137 # Per bank write bursts -system.physmem.perBankWrBursts::11 102620 # Per bank write bursts -system.physmem.perBankWrBursts::12 102863 # Per bank write bursts -system.physmem.perBankWrBursts::13 102594 # Per bank write bursts -system.physmem.perBankWrBursts::14 104213 # Per bank write bursts -system.physmem.perBankWrBursts::15 102497 # Per bank write bursts +system.physmem.perBankRdBursts::0 301314 # Per bank write bursts +system.physmem.perBankRdBursts::1 301808 # Per bank write bursts +system.physmem.perBankRdBursts::2 285079 # Per bank write bursts +system.physmem.perBankRdBursts::3 287721 # Per bank write bursts +system.physmem.perBankRdBursts::4 288732 # Per bank write bursts +system.physmem.perBankRdBursts::5 286480 # Per bank write bursts +system.physmem.perBankRdBursts::6 281880 # Per bank write bursts +system.physmem.perBankRdBursts::7 278193 # Per bank write bursts +system.physmem.perBankRdBursts::8 293719 # Per bank write bursts +system.physmem.perBankRdBursts::9 299847 # Per bank write bursts +system.physmem.perBankRdBursts::10 291529 # Per bank write bursts +system.physmem.perBankRdBursts::11 297903 # Per bank write bursts +system.physmem.perBankRdBursts::12 299405 # Per bank write bursts +system.physmem.perBankRdBursts::13 299387 # Per bank write bursts +system.physmem.perBankRdBursts::14 294305 # Per bank write bursts +system.physmem.perBankRdBursts::15 290006 # Per bank write bursts +system.physmem.perBankWrBursts::0 103629 # Per bank write bursts +system.physmem.perBankWrBursts::1 101748 # Per bank write bursts +system.physmem.perBankWrBursts::2 99222 # Per bank write bursts +system.physmem.perBankWrBursts::3 99944 # Per bank write bursts +system.physmem.perBankWrBursts::4 98990 # Per bank write bursts +system.physmem.perBankWrBursts::5 98822 # Per bank write bursts +system.physmem.perBankWrBursts::6 102440 # Per bank write bursts +system.physmem.perBankWrBursts::7 104048 # Per bank write bursts +system.physmem.perBankWrBursts::8 105134 # Per bank write bursts +system.physmem.perBankWrBursts::9 103994 # Per bank write bursts +system.physmem.perBankWrBursts::10 101818 # Per bank write bursts +system.physmem.perBankWrBursts::11 102570 # Per bank write bursts +system.physmem.perBankWrBursts::12 102850 # Per bank write bursts +system.physmem.perBankWrBursts::13 102376 # Per bank write bursts +system.physmem.perBankWrBursts::14 104237 # Per bank write bursts +system.physmem.perBankWrBursts::15 102624 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767803802500 # Total gap between requests +system.physmem.totGap 770752366000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4673385 # Read request sizes (log2) +system.physmem.readPktSize::6 4685154 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1635896 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634499 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2776424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1031022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 327510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 229431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 146630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 80164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 110766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 100949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,123 +198,130 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads -system.physmem.totQLat 128478496877 # Total ticks spent queuing -system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4255173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.931559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.862227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.833954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3394354 79.77% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 663703 15.60% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94226 2.21% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35436 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22765 0.53% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12171 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7342 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19831 0.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4255173 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97794 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.827914 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.473591 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 93707 95.82% 95.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1671 1.71% 97.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 768 0.79% 98.31% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 406 0.42% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 365 0.37% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 337 0.34% 99.45% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 234 0.24% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 165 0.17% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 89 0.09% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 24 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 12 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1664-1791 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3968-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97794 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97794 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.713152 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.671812 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.223073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68724 70.27% 70.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1896 1.94% 72.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18671 19.09% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5634 5.76% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1729 1.77% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 613 0.63% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 266 0.27% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 147 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 67 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 30 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97794 # Writes before turning the bus around for reads +system.physmem.totQLat 128325813562 # Total ticks spent queuing +system.physmem.totMemAccLat 216025338562 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23386540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27435.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46185.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 135.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 135.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.10 # Data bus utilization in percentage -system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes +system.physmem.busUtil 4.09 # Data bus utilization in percentage +system.physmem.busUtilRead 3.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing -system.physmem.readRowHits 1710736 # Number of row buffer hits during reads -system.physmem.writeRowHits 347188 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing +system.physmem.readRowHits 1715091 # Number of row buffer hits during reads +system.physmem.writeRowHits 341475 # Number of row buffer hits during writes system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes -system.physmem.avgGap 121694.34 # Average gap between requests -system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.947771 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states -system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states +system.physmem.writeRowHitRate 20.89 # Row buffer hit rate for writes +system.physmem.avgGap 121961.18 # Average gap between requests +system.physmem.pageHitRate 32.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15989112720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8724218250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18025846800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5241069360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 417928675995 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 95843265750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 612093526155 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.157652 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 156909498029 # Time in different power states +system.physmem_0.memoryStateTime::REF 25736880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states +system.physmem_0.memoryStateTime::ACT 588099785971 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.363055 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states -system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states +system.physmem_1.actEnergy 16179556680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8828131125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18455494200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5349602880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 412908393870 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100247038500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612309554535 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.437909 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 164276600328 # Time in different power states +system.physmem_1.memoryStateTime::REF 25736880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states +system.physmem_1.memoryStateTime::ACT 580733308672 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286292198 # Number of BP lookups -system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286275195 # Number of BP lookups +system.cpu.branchPred.condPredicted 223398341 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14628424 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157667483 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150349199 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.358406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16643020 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3069 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1906 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1163 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 137 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -344,7 +351,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -374,7 +381,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -404,7 +411,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -435,95 +442,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1535607688 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1541504754 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925502 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067484101 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286275195 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166994125 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1512857238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29281631 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 279 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1018 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656940019 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 946 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1541424852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.436951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229037 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 459011037 29.78% 29.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465435057 30.20% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101419068 6.58% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515559690 33.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128568020 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1541424852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185712 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.341212 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74709451 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 544021839 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849845592 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58207832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14640138 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42201657 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 726 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037180089 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52484609 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14640138 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139806563 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462600801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15884 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837785307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86576159 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976384850 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26739549 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45323653 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126929 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1602638 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25499860 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985860548 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128169124 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432875929 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 174 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 310961603 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 175 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 111534180 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542566077 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199303375 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26892889 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29237160 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947969517 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647584065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857492369 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13496690 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283937332 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647289356 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1541424852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150817 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 588435916 38.17% 38.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326131475 21.16% 59.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378210554 24.54% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219654013 14.25% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28986723 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6171 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1541424852 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166021321 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1993 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available @@ -551,13 +558,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191489776 47.28% 88.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47539480 11.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138243662 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800931 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -579,88 +586,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532135699 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186312026 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued -system.cpu.iq.rate 1.209614 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857492369 # Type of FU issued +system.cpu.iq.rate 1.204986 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405052570 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218064 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674958613 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231919871 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805704142 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262544806 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17811536 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84259743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66618 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13244 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24456330 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4512030 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4891489 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14640138 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25364964 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1346928 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947969899 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542566077 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199303375 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 159350 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1186169 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13244 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7699482 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8703162 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16402644 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827831567 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516957415 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29660802 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542687 # Number of branches executed -system.cpu.iew.exec_stores 181751910 # Number of stores executed -system.cpu.iew.exec_rate 1.190295 # Inst execution rate -system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169207800 # num instructions producing a value -system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle +system.cpu.iew.exec_nop 151 # number of nop insts executed +system.cpu.iew.exec_refs 698708795 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542425 # Number of branches executed +system.cpu.iew.exec_stores 181751380 # Number of stores executed +system.cpu.iew.exec_rate 1.185745 # Inst execution rate +system.cpu.iew.wb_sent 1808736265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805704212 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169174812 # num instructions producing a value +system.cpu.iew.wb_consumers 1689572222 # num instructions consuming a value +system.cpu.iew.wb_rate 1.171391 # insts written-back per cycle system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258041892 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14627747 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1501940299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.107922 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025263 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 921653315 61.36% 61.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250636600 16.69% 78.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110060462 7.33% 85.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55269176 3.68% 89.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29319156 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34080655 2.27% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24723288 1.65% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18133421 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58064226 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1501940299 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -706,78 +713,78 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360114616 # The number of ROB reads -system.cpu.rob.rob_writes 3883791528 # The number of ROB writes -system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58064226 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3365949800 # The number of ROB reads +system.cpu.rob.rob_writes 3883638365 # The number of ROB writes +system.cpu.timesIdled 837 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79902 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads -system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes +system.cpu.cpi 0.998020 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.998020 # CPI: Total CPI of All Threads +system.cpu.ipc 1.001984 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.001984 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175818987 # number of integer regfile reads +system.cpu.int_regfile_writes 1261576435 # number of integer regfile writes system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads -system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes -system.cpu.misc_regfile_reads 675853618 # number of misc regfile reads +system.cpu.fp_regfile_writes 52 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965775009 # number of cc regfile reads +system.cpu.cc_regfile_writes 551856674 # number of cc regfile writes +system.cpu.misc_regfile_reads 675846934 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003710 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17003150 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964340 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638065664 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17003662 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79206500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964340 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335709608 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335709608 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469347574 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469347574 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168717937 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168717937 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits -system.cpu.dcache.overall_hits::total 638076218 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638065511 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638065511 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638065511 # number of overall hits +system.cpu.dcache.overall_hits::total 638065511 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17419228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17419228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3868110 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3868110 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses -system.cpu.dcache.overall_misses::total 21285744 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21287338 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21287338 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21287340 # number of overall misses +system.cpu.dcache.overall_misses::total 21287340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 416423435500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 150253086257 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 199500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 566676521757 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 566676521757 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 566676521757 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 566676521757 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486766802 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486766802 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -786,470 +793,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659352849 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659352849 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659352851 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659352851 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022413 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022413 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks -system.cpu.dcache.writebacks::total 17003710 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.032285 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032285 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032285 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032285 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49875 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49875 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26620.356277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26620.353776 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20685246 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3452781 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946049 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67233 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.864878 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51.355450 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17003150 # number of writebacks +system.cpu.dcache.writebacks::total 17003150 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3153076 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3153076 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130592 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1130592 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4283668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4283668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4283668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4283668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266152 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266152 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737518 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737518 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17003670 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17003670 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17003671 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17003671 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451887651533 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451887720533 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 589 # number of replacements -system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025788 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025788 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 588 # number of replacements +system.cpu.icache.tags.tagsinuse 444.874436 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656938405 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611674.492551 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.874436 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868895 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868895 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits -system.cpu.icache.overall_hits::total 656966815 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses -system.cpu.icache.overall_misses::total 1620 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 463 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4068 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2886 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1253 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008728 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561777243 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561777243 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 4835234 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312336320998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 312404671498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68350500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312336320998 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 385622836136 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356810 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356810 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216837 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287303 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34008488 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003756 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 201663 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 201662 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14267181 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6469733 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12168504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3012569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1490485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737555 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737555 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104697920 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266107 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2738 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51010503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51013241 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176436672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176543040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6137564 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104608640 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23142303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009630 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097659 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22919446 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 222856 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23142303 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34007983525 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 16538 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1611000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25505500994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3696594 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution -system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 976790 # Transaction distribution -system.membus.trans_dist::ReadExResp 976790 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 9332231 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4668264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3708204 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634499 # Transaction distribution +system.membus.trans_dist::CleanEvict 3012569 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 976948 # Transaction distribution +system.membus.trans_dist::ReadExResp 976948 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3708206 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14017383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14017383 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404457664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404457664 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 9311100 # Request fanout histogram +system.membus.snoop_fanout::samples 4685163 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4685163 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9311100 # Request fanout histogram -system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4685163 # Request fanout histogram +system.membus.reqLayer0.occupancy 17662405597 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25476549560 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index a861bb889..ddb5178a1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1008264 # Simulator instruction rate (inst/s) -host_op_rate 1086251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 543126570 # Simulator tick rate (ticks/s) -host_mem_usage 256604 # Number of bytes of host memory used -host_seconds 1531.90 # Real time elapsed on the host +host_inst_rate 1176831 # Simulator instruction rate (inst/s) +host_op_rate 1267857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 633929666 # Simulator tick rate (ticks/s) +host_mem_usage 260476 # Number of bytes of host memory used +host_seconds 1312.48 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 8383808423 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram -system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2172060895 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2172060895 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e3d403cda..02e32a48c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.377030 # Number of seconds simulated -sim_ticks 2377029670500 # Number of ticks simulated -final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.379922 # Number of seconds simulated +sim_ticks 2379921906500 # Number of ticks simulated +final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744525 # Simulator instruction rate (inst/s) -host_op_rate 802329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1150119113 # Simulator tick rate (ticks/s) -host_mem_usage 266344 # Number of bytes of host memory used -host_seconds 2066.77 # Real time elapsed on the host +host_inst_rate 802178 # Simulator instruction rate (inst/s) +host_op_rate 864460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1240688848 # Simulator tick rate (ticks/s) +host_mem_usage 272000 # Number of bytes of host memory used +host_seconds 1918.23 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory -system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory +system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory -system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory +system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 4754059341 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 4759843813 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -221,26 +221,26 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -263,14 +263,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -295,22 +295,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks -system.cpu.dcache.writebacks::total 3681379 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks +system.cpu.dcache.writebacks::total 3667054 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -321,16 +321,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -341,26 +341,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -368,7 +368,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 606 system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,90 +419,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1919027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1938113 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000309 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000710 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.965759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.966777 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 744 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27370 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3667054 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses +system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 37281000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71177285500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71177285500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37281000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 119233240500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37281000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 119233240500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3667054 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3667054 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) @@ -517,101 +517,101 @@ system.cpu.l2cache.demand_accesses::total 9115874 # n system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420134 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.420134 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162779 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162779 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.216117 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.216169 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.216117 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.216169 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks -system.cpu.l2cache.writebacks::total 1021127 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks +system.cpu.l2cache.writebacks::total 1031709 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176258 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176258 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1969954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1970570 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1969954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1970570 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40081714000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40081714000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 31121000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 31121000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59414705500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59414705500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31121000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99496419500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 99527540500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution @@ -620,53 +620,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919027 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65352128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1938113 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1169580 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution -system.membus.trans_dist::CleanEvict 897056 # Transaction distribution -system.membus.trans_dist::ReadExReq 782134 # Transaction distribution -system.membus.trans_dist::ReadExResp 782134 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1176874 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution +system.membus.trans_dist::CleanEvict 905404 # Transaction distribution +system.membus.trans_dist::ReadExReq 793696 # Transaction distribution +system.membus.trans_dist::ReadExResp 793696 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3869897 # Request fanout histogram +system.membus.snoop_fanout::samples 1970570 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1970570 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3869897 # Request fanout histogram -system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1970570 # Request fanout histogram +system.membus.reqLayer0.occupancy 8048170000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9852850000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 907fd74ca..e4956c5fa 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 953043 # Simulator instruction rate (inst/s) -host_op_rate 1484927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 901693633 # Simulator tick rate (ticks/s) -host_mem_usage 259304 # Number of bytes of host memory used -host_seconds 3156.29 # Real time elapsed on the host +host_inst_rate 913315 # Simulator instruction rate (inst/s) +host_op_rate 1423027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864105629 # Simulator tick rate (ticks/s) +host_mem_usage 264708 # Number of bytes of host memory used +host_seconds 3293.59 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 38674388193 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram -system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram -system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5690945966 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5690945966 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 33a716627..3b577baaf 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.895948 # Number of seconds simulated -sim_ticks 5895947852500 # Number of ticks simulated -final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.898831 # Number of seconds simulated +sim_ticks 5898831348500 # Number of ticks simulated +final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 735742 # Simulator instruction rate (inst/s) -host_op_rate 1146353 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1442081312 # Simulator tick rate (ticks/s) -host_mem_usage 269296 # Number of bytes of host memory used -host_seconds 4088.50 # Real time elapsed on the host +host_inst_rate 637466 # Simulator instruction rate (inst/s) +host_op_rate 993229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1250066735 # Simulator tick rate (ticks/s) +host_mem_usage 275724 # Number of bytes of host memory used +host_seconds 4718.81 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory -system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory +system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory -system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory +system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11791895705 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 11797662697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -66,7 +66,7 @@ system.cpu.num_mem_refs 1677713084 # nu system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles +system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 248500691 # Number of branches fetched @@ -105,26 +105,26 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits @@ -141,14 +141,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) @@ -165,22 +165,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks -system.cpu.dcache.writebacks::total 3682716 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks +system.cpu.dcache.writebacks::total 3669049 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses @@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -205,31 +205,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits @@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses @@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,86 +280,86 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1919169 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1938075 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107394 # 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number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses +system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) @@ -374,101 +374,101 @@ system.cpu.l2cache.demand_accesses::total 9113352 # n system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks -system.cpu.l2cache.writebacks::total 1022289 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks +system.cpu.l2cache.writebacks::total 1032938 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution @@ -477,55 +477,61 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919169 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65426496 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1938075 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1169437 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution -system.membus.trans_dist::CleanEvict 896090 # Transaction distribution -system.membus.trans_dist::ReadExReq 782433 # Transaction distribution -system.membus.trans_dist::ReadExResp 782433 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1176539 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution +system.membus.trans_dist::CleanEvict 904164 # Transaction distribution +system.membus.trans_dist::ReadExReq 793964 # Transaction distribution +system.membus.trans_dist::ReadExResp 793964 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3870249 # Request fanout histogram +system.membus.snoop_fanout::samples 1970503 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870249 # Request fanout histogram -system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1970503 # Request fanout histogram +system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 78502d1ca..d3e370d8a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053345 # Number of seconds simulated -sim_ticks 53344764500 # Number of ticks simulated -final_tick 53344764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.053349 # Number of seconds simulated +sim_ticks 53349450500 # Number of ticks simulated +final_tick 53349450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260335 # Simulator instruction rate (inst/s) -host_op_rate 260335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151110624 # Simulator tick rate (ticks/s) -host_mem_usage 253412 # Number of bytes of host memory used -host_seconds 353.02 # Real time elapsed on the host +host_inst_rate 273465 # Simulator instruction rate (inst/s) +host_op_rate 273465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158745564 # Simulator tick rate (ticks/s) +host_mem_usage 258296 # Number of bytes of host memory used +host_seconds 336.07 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory system.physmem.bytes_read::total 340608 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 202880 # Nu system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3803185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6385031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3803185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3803185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3803185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2581847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6385031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3802851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6384471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3802851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3802851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3802851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2581620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6384471 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5322 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53344677500 # Total gap between requests +system.physmem.totGap 53349362500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 4932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.749242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.692592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.528362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 314 31.75% 31.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 216 21.84% 53.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 8.90% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 117 11.83% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 52 5.26% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 40 4.04% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.93% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 2.12% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 112 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 989 # Bytes accessed per row activation -system.physmem.totQLat 40222250 # Total ticks spent queuing -system.physmem.totMemAccLat 140009750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.743381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.338865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.606559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 303 30.86% 30.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 220 22.40% 53.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 9.57% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 10.69% 73.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 62 6.31% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 3.67% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 2.95% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 2.24% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 111 11.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation +system.physmem.totQLat 40016750 # Total ticks spent queuing +system.physmem.totMemAccLat 139804250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7557.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7519.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26307.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26269.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -217,49 +217,49 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4331 # Number of row buffer hits during reads +system.physmem.readRowHits 4333 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10023426.81 # Average gap between requests -system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3538080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1930500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 20022600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 10024307.12 # Average gap between requests +system.physmem.pageHitRate 81.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3462480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1889250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1791514845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30434811000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 35735961585 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.917071 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 50627942250 # Time in different power states +system.physmem_0.actBackEnergy 1795262310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30431523750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 35736125550 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.920144 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 50622338000 # Time in different power states system.physmem_0.memoryStateTime::REF 1781260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 934855250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 940274500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3938760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2149125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21411000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3923640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2140875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21247200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1835182260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30396506250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35743331955 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.055238 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 50563679500 # Time in different power states +system.physmem_1.actBackEnergy 1822659075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 30407483250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 35741598600 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.022916 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 50582866250 # Time in different power states system.physmem_1.memoryStateTime::REF 1781260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 998933000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 980601250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450644 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210940 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11450641 # Number of BP lookups +system.cpu.branchPred.condPredicted 8210938 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085193 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320740 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6085190 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5320739 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.437490 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176675 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.437516 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176674 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. @@ -270,22 +270,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20415220 # DTB read hits +system.cpu.dtb.read_hits 20415218 # DTB read hits system.cpu.dtb.read_misses 43383 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20458603 # DTB read accesses +system.cpu.dtb.read_accesses 20458601 # DTB read accesses system.cpu.dtb.write_hits 6579912 # DTB write hits system.cpu.dtb.write_misses 276 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 6580188 # DTB write accesses -system.cpu.dtb.data_hits 26995132 # DTB hits +system.cpu.dtb.data_hits 26995130 # DTB hits system.cpu.dtb.data_misses 43659 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27038791 # DTB accesses -system.cpu.itb.fetch_hits 22968620 # ITB hits +system.cpu.dtb.data_accesses 27038789 # DTB accesses +system.cpu.itb.fetch_hits 22968614 # ITB hits system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968710 # ITB accesses +system.cpu.itb.fetch_accesses 22968704 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106689529 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 106698901 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191325 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2191321 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.160892 # CPI: cycles per instruction -system.cpu.ipc 0.861407 # IPC: instructions per cycle +system.cpu.cpi 1.160994 # CPI: cycles per instruction +system.cpu.ipc 0.861331 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction @@ -344,16 +344,16 @@ system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103791732 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2897797 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 103791781 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2907120 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.584436 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572205 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.584590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572201 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.445988 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11910.444195 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584436 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584590 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.353414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id @@ -363,41 +363,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153443 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153443 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074007 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074007 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498198 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498198 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572205 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572205 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572205 # number of overall hits -system.cpu.dcache.overall_hits::total 26572205 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53153439 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153439 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20074005 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074005 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498196 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498196 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572201 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572201 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572201 # number of overall hits +system.cpu.dcache.overall_hits::total 26572201 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2905 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2905 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3401 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3401 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3401 # number of overall misses -system.cpu.dcache.overall_misses::total 3401 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37448500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37448500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 219755500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 219755500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 257204000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 257204000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 257204000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 257204000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074503 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2907 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2907 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3403 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3403 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3403 # number of overall misses +system.cpu.dcache.overall_misses::total 3403 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37687000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37687000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 223750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 223750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 261437000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 261437000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 261437000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 261437000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074501 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575606 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575606 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575606 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575606 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26575604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575604 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75501.008065 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75501.008065 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75647.332186 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75647.332186 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75625.992355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75625.992355 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76825.448134 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76825.448134 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1162 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1162 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1170 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1164 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1164 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1172 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1172 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1172 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1172 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2231 system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36544000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36544000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 137282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 173826000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 173826000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 173826000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 173826000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36777500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36777500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 140150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 140150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 176927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 176927500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -454,24 +454,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74885.245902 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74885.245902 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78761.904762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78761.904762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.714068 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952789 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1642.701416 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22952783 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.955085 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.954706 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.714068 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.802106 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.802106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.701416 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.802100 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.802100 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -479,45 +479,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670 system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953070 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953070 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952789 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952789 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952789 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952789 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952789 # number of overall hits -system.cpu.icache.overall_hits::total 22952789 # number of overall hits +system.cpu.icache.tags.tag_accesses 45953058 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45953058 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22952783 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22952783 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22952783 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22952783 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22952783 # number of overall hits +system.cpu.icache.overall_hits::total 22952783 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409090000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409090000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409090000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409090000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409090000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409090000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968620 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 411111000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 411111000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 411111000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 411111000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 411111000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 411111000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22968614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22968614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22968614 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22968614 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22968614 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22968614 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25841.071316 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25841.071316 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25841.071316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25841.071316 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25968.732234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25968.732234 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,48 +532,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15831 system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393260000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 393260000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393260000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 393260000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393260000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 393260000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 395281000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 395281000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 395281000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 395281000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 395281000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 395281000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24841.134483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24841.134483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2482.282304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 26642 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3671 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.257423 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3575.444447 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.761061 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.458659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 362.062585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000542 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.450993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.993454 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075753 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3671 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2509 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.112030 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 262078 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 262078 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044952 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109114 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits @@ -602,18 +600,18 @@ system.cpu.l2cache.demand_misses::total 5322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 134394000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 134394000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236583500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 236583500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 35249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 236583500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169643500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406227000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 236583500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169643500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406227000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 137262000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 137262000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 238604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 238604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35483000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 35483000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238604500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 172745000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 411349500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238604500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 172745000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 411349500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) @@ -642,18 +640,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294668 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78272.568433 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78272.568433 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74632.018927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74632.018927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76329.763247 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76329.763247 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,18 +670,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 117224000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 117224000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204883500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204883500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30899500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30899500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204883500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148123500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 353007000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204883500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148123500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 353007000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120092000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120092000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 206904500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 206904500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31133000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31133000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206904500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151225000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 358129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206904500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151225000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 358129500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses @@ -696,25 +694,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68272.568433 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68272.568433 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64632.018927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64632.018927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution @@ -748,7 +746,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23745000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3605 # Transaction distribution system.membus.trans_dist::ReadExReq 1717 # Transaction distribution system.membus.trans_dist::ReadExResp 1717 # Transaction distribution @@ -769,9 +773,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6419500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6421000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28179750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28180500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 002e3eec9..720778178 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021909 # Number of seconds simulated -sim_ticks 21909208500 # Number of ticks simulated -final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021906 # Number of seconds simulated +sim_ticks 21906070500 # Number of ticks simulated +final_tick 21906070500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183723 # Simulator instruction rate (inst/s) -host_op_rate 183723 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47816944 # Simulator tick rate (ticks/s) -host_mem_usage 254944 # Number of bytes of host memory used -host_seconds 458.19 # Real time elapsed on the host +host_inst_rate 201237 # Simulator instruction rate (inst/s) +host_op_rate 201237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52367931 # Simulator tick rate (ticks/s) +host_mem_usage 260088 # Number of bytes of host memory used +host_seconds 418.31 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory system.physmem.bytes_read::total 334528 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 195968 # Nu system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8944550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6324281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15268831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8944550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8944550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8944550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6324281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15268831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8945831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6325187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15271018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8945831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8945831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8945831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6325187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15271018 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5227 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue @@ -43,7 +43,7 @@ system.physmem.servicedByWrQ 0 # Nu system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 470 # Per bank write bursts -system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::1 292 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts @@ -55,7 +55,7 @@ system.physmem.perBankRdBursts::9 278 # Pe system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 251 # Per bank write bursts system.physmem.perBankRdBursts::12 395 # Per bank write bursts -system.physmem.perBankRdBursts::13 339 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 492 # Per bank write bursts system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21909113500 # Total gap between requests +system.physmem.totGap 21905974500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.435239 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 233.348968 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.138574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 246 28.70% 28.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186 21.70% 50.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 85 9.92% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 7.58% 67.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37 4.32% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 35 4.08% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 3.97% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 49 5.72% 86.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 120 14.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 857 # Bytes accessed per row activation -system.physmem.totQLat 42496500 # Total ticks spent queuing -system.physmem.totMemAccLat 140502750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.707657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.399691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.883028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 260 30.16% 30.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 179 20.77% 50.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 10.79% 61.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.61% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 30 3.48% 71.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.29% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 31 3.60% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 50 5.80% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 125 14.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 862 # Bytes accessed per row activation +system.physmem.totQLat 40339750 # Total ticks spent queuing +system.physmem.totMemAccLat 138346000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8130.19 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7717.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26880.19 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26467.57 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4359 # Number of row buffer hits during reads +system.physmem.readRowHits 4357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4191527.36 # Average gap between requests -system.physmem.pageHitRate 83.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3076920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1678875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19468800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4190926.82 # Average gap between requests +system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19570200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 930163050 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12325856250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14710823175 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.635656 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20502630500 # Time in different power states +system.physmem_0.actBackEnergy 905463810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12347522250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14707973130 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.505534 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20538678250 # Time in different power states system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 668984500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 632936750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20771400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3333960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1819125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20779200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 904676355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12348213000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14709404805 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.570899 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20540502500 # Time in different power states +system.physmem_1.actBackEnergy 902236185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12350353500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14709101250 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.557040 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20543762750 # Time in different power states system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 628284250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16102191 # Number of BP lookups -system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8963309 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7508263 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16102243 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688063 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 931000 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8962915 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7507921 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.766642 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1594548 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 465 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 29370 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3646 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 83.766509 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594308 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 29379 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25730 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3649 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24064579 # DTB read hits -system.cpu.dtb.read_misses 206327 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 24270906 # DTB read accesses -system.cpu.dtb.write_hits 7168860 # DTB write hits -system.cpu.dtb.write_misses 1193 # DTB write misses +system.cpu.dtb.read_hits 24059471 # DTB read hits +system.cpu.dtb.read_misses 206747 # DTB read misses +system.cpu.dtb.read_acv 6 # DTB read access violations +system.cpu.dtb.read_accesses 24266218 # DTB read accesses +system.cpu.dtb.write_hits 7167964 # DTB write hits +system.cpu.dtb.write_misses 1190 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7170053 # DTB write accesses -system.cpu.dtb.data_hits 31233439 # DTB hits -system.cpu.dtb.data_misses 207520 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 31440959 # DTB accesses -system.cpu.itb.fetch_hits 15932703 # ITB hits +system.cpu.dtb.write_accesses 7169154 # DTB write accesses +system.cpu.dtb.data_hits 31227435 # DTB hits +system.cpu.dtb.data_misses 207937 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 31435372 # DTB accesses +system.cpu.itb.fetch_hits 15930202 # ITB hits system.cpu.itb.fetch_misses 79 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15932782 # ITB accesses +system.cpu.itb.fetch_accesses 15930281 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,140 +299,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43818418 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 43812142 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16643559 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137979359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16102191 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9128535 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25956071 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1939868 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2614 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15932703 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367699 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43572351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.166672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433625 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16640800 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137955116 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102243 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9127959 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25951378 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939862 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2284 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15930202 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367997 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43564561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.166682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433652 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19392056 44.51% 44.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2618542 6.01% 50.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1330036 3.05% 53.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1934112 4.44% 58.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3001913 6.89% 64.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1292242 2.97% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1355704 3.11% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 886645 2.03% 73.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11761101 26.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19388904 44.51% 44.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2617971 6.01% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1329653 3.05% 53.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1933242 4.44% 58.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001866 6.89% 64.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292154 2.97% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355153 3.11% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 885983 2.03% 73.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11759635 26.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43572351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367475 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.148890 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12867028 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8206518 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19434084 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2106116 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 958605 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2654233 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11853 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132149690 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49712 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 958605 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13986113 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4641138 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10397 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20305818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3670280 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128777120 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70822 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2026790 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1359443 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 54939 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94599417 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167333836 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159779688 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7554147 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43564561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367529 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.148787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12866207 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8201064 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19435677 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2103016 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958597 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2653560 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11864 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132121785 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49799 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13983011 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4637206 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10599 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3669868 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128752916 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70736 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2012785 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1367413 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 56554 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94580122 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167299448 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159747069 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7552378 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26172056 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 950 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8271760 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26904379 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8704430 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3459754 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1614105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111855372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99762873 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119457 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27677581 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21095041 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1530 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43572351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.289591 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099378 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26152761 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 954 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 949 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8254781 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26901517 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704631 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3463893 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1634991 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111837286 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1924 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99746434 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118591 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27659500 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21091403 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1535 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43564561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099110 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11226739 25.77% 25.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7658694 17.58% 43.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7470474 17.14% 60.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5702469 13.09% 73.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4463101 10.24% 83.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2983064 6.85% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2041659 4.69% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1171062 2.69% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 855089 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11223672 25.76% 25.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7655343 17.57% 43.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7467756 17.14% 60.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5704970 13.10% 73.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4467403 10.25% 83.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2981246 6.84% 90.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2039535 4.68% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1169471 2.68% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855165 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43572351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43564561 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 483998 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481664 20.16% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 522 0.02% 20.18% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34928 1.45% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12187 0.51% 22.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1012495 42.17% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 694978 28.95% 93.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161680 6.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34768 1.46% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12121 0.51% 22.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1011551 42.34% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 688710 28.83% 93.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159620 6.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60663003 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60652801 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489881 0.49% 61.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2847512 2.85% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2443315 2.45% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314199 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847832 2.86% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115342 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2442782 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314177 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766025 0.77% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued @@ -454,82 +454,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24854808 24.91% 92.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7268585 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24850091 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7267177 7.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99762873 # Type of FU issued -system.cpu.iq.rate 2.276734 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2400804 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024065 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229929463 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129921880 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89757813 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15688895 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9653551 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7189472 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93781732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8381938 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1923340 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99746434 # Type of FU issued +system.cpu.iq.rate 2.276685 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2388956 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023950 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229877287 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129889935 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89741335 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15687689 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9649325 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93754597 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8380786 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1921314 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6908181 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11335 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40937 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2203327 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6905319 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11494 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40918 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203528 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42874 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1494 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 958605 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3611196 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 465334 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122779718 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241439 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26904379 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8704430 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1919 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38387 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 421097 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40937 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034339 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98437326 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24271451 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1325547 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 958597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3610605 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 461685 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122758059 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241249 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26901517 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704631 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1924 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38682 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 417297 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40918 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531922 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502439 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98421413 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24266766 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325021 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10922427 # number of nop insts executed -system.cpu.iew.exec_refs 31441543 # number of memory reference insts executed -system.cpu.iew.exec_branches 12471856 # Number of branches executed -system.cpu.iew.exec_stores 7170092 # Number of stores executed -system.cpu.iew.exec_rate 2.246483 # Inst execution rate -system.cpu.iew.wb_sent 97646069 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96947285 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66976790 # num instructions producing a value -system.cpu.iew.wb_consumers 94960923 # num instructions consuming a value -system.cpu.iew.wb_rate 2.212478 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705309 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30878414 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10918849 # number of nop insts executed +system.cpu.iew.exec_refs 31435958 # number of memory reference insts executed +system.cpu.iew.exec_branches 12470734 # Number of branches executed +system.cpu.iew.exec_stores 7169192 # Number of stores executed +system.cpu.iew.exec_rate 2.246441 # Inst execution rate +system.cpu.iew.wb_sent 97629714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96930630 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66965531 # num instructions producing a value +system.cpu.iew.wb_consumers 94946242 # num instructions consuming a value +system.cpu.iew.wb_rate 2.212415 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705299 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30856710 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 919665 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39078577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.351750 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.919984 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 919666 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39073158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.352076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.920100 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14680368 37.57% 37.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8532696 21.83% 59.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3879932 9.93% 69.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1909819 4.89% 74.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1376650 3.52% 77.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1035169 2.65% 80.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692226 1.77% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 728499 1.86% 84.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6243218 15.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14677251 37.56% 37.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8528323 21.83% 59.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3880033 9.93% 69.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1914323 4.90% 74.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1374739 3.52% 77.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1034073 2.65% 80.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692942 1.77% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727068 1.86% 84.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6244406 15.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39078577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39073158 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -575,118 +575,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6243218 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155615788 # The number of ROB reads -system.cpu.rob.rob_writes 250112160 # The number of ROB writes -system.cpu.timesIdled 4756 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 246067 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6244406 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155587477 # The number of ROB reads +system.cpu.rob.rob_writes 250066312 # The number of ROB writes +system.cpu.timesIdled 4758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 247581 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520534 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520534 # CPI: Total CPI of All Threads -system.cpu.ipc 1.921103 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.921103 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133011224 # number of integer regfile reads -system.cpu.int_regfile_writes 72905073 # number of integer regfile writes -system.cpu.fp_regfile_reads 6263399 # number of floating regfile reads -system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes -system.cpu.misc_regfile_reads 719113 # number of misc regfile reads +system.cpu.cpi 0.520460 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520460 # CPI: Total CPI of All Threads +system.cpu.ipc 1.921379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.921379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 132984940 # number of integer regfile reads +system.cpu.int_regfile_writes 72890464 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263699 # number of floating regfile reads +system.cpu.fp_regfile_writes 6177982 # number of floating regfile writes +system.cpu.misc_regfile_reads 719169 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.358075 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28585648 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12734.411136 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12733.028062 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.375474 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355805 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.358075 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355800 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355800 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 536 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492632 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28588283 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28588283 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28588283 # number of overall hits -system.cpu.dcache.overall_hits::total 28588283 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1074 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1074 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8471 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8471 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 57192649 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57192649 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22092545 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22092545 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492630 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492630 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 473 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 473 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28585175 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28585175 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28585175 # number of overall hits +system.cpu.dcache.overall_hits::total 28585175 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1080 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1080 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8473 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8473 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9545 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9545 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9545 # number of overall misses -system.cpu.dcache.overall_misses::total 9545 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71413000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71413000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 546757246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 546757246 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 618170246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 618170246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 618170246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 618170246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22096725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22096725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9553 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9553 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9553 # number of overall misses +system.cpu.dcache.overall_misses::total 9553 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 72549500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 72549500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 550211742 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 550211742 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 86000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 86000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 622761242 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 622761242 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 622761242 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 622761242 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22093625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22093625 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28597828 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28597828 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28597828 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28597828 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28594728 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28594728 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28594728 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28594728 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002110 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002110 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66492.551210 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66492.551210 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64544.592846 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64544.592846 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64763.776427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64763.776427 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32543 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 392 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67175.462963 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67175.462963 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64937.063850 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64937.063850 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 86000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 86000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65190.122684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65190.122684 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 396 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.017857 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.487374 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 559 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 559 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6742 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6742 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7301 # 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number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses @@ -697,154 +697,152 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2244 system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39779500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39779500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135885995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 135885995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175665495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 175665495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175665495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 175665495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136978995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 136978995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 85000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 85000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177801495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 177801495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177801495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 177801495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002110 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77241.747573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77241.747573 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78592.246964 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78592.246964 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79266.990291 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79266.990291 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79224.404280 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79224.404280 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 85000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 85000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9515 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1600.893985 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15915792 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11453 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1389.880119 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1389.661399 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.928709 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781703 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.893985 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781687 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781687 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 943 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31876857 # 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miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000905 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31066.625026 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31066.625026 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31066.625026 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31066.625026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31066.625026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31066.625026 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 446 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 89.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 9515 # number of writebacks system.cpu.icache.writebacks::total 9515 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2951 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2951 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2951 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2951 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2951 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2951 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2955 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2955 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2955 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2955 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2955 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2955 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11454 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 11454 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 11454 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11454 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11454 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11454 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 336702000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 336702000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 336702000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 336702000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 336702000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 336702000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 337628000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 337628000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 337628000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 337628000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337628000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 337628000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000719 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000719 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29396.018858 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29396.018858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29476.863978 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29476.863978 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.022848 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3490.224517 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 18145 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5227 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.471399 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.652891 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.506649 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 381.204708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011633 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073467 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.515587 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.708930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061265 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045249 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106513 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5227 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1371 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3517 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.159515 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 192203 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 192203 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits @@ -873,18 +871,18 @@ system.cpu.l2cache.demand_misses::total 5227 # nu system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses system.cpu.l2cache.overall_misses::total 5227 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 132876500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 132876500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 231097000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 231097000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38506000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 38506000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 231097000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 171382500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 402479500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 231097000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 171382500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 402479500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 133969500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 133969500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 232023500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 232023500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 39550000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 39550000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 232023500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 173519500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 405543000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 232023500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 173519500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 405543000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 9515 # number of WritebackClean accesses(hits+misses) @@ -913,18 +911,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.381561 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267330 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.381561 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78024.955960 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78024.955960 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75472.566950 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75472.566950 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83346.320346 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83346.320346 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77000.095657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77000.095657 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78666.764533 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78666.764533 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75775.146963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75775.146963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85606.060606 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85606.060606 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77586.187105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77586.187105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -943,18 +941,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5227 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115846500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115846500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200477000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200477000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33886000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33886000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200477000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149732500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 350209500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200477000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149732500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 350209500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 116939500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 116939500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 201403500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 201403500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34930000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34930000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 201403500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 353273000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 201403500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 353273000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses @@ -967,25 +965,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68666.764533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68666.764533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65775.146963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65775.146963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75606.060606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75606.060606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution @@ -1019,7 +1017,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 17179500 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5227 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3524 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution @@ -1040,9 +1044,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5227 # Request fanout histogram -system.membus.reqLayer0.occupancy 6276500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6278000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27456000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27461750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 91b6b6b0a..9382954d5 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132486 # Number of seconds simulated -sim_ticks 132485848500 # Number of ticks simulated -final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132488 # Number of seconds simulated +sim_ticks 132487590500 # Number of ticks simulated +final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159309 # Simulator instruction rate (inst/s) -host_op_rate 167937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122483807 # Simulator tick rate (ticks/s) -host_mem_usage 270152 # Number of bytes of host memory used -host_seconds 1081.66 # Real time elapsed on the host +host_inst_rate 200266 # Simulator instruction rate (inst/s) +host_op_rate 211113 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153975874 # Simulator tick rate (ticks/s) +host_mem_usage 275560 # Number of bytes of host memory used +host_seconds 860.44 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132485754500 # Total gap between requests +system.physmem.totGap 132487495500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation -system.physmem.totQLat 30291250 # Total ticks spent queuing -system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation +system.physmem.totQLat 28381250 # Total ticks spent queuing +system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -217,56 +217,56 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2934 # Number of row buffer hits during reads +system.physmem.readRowHits 2936 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34251746.25 # Average gap between requests -system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 34252196.35 # Average gap between requests +system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.835850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states +system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.825360 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833625 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states +system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.826698 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693791 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693795 # Number of BP lookups +system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264971697 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264975181 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.537692 # CPI: cycles per instruction -system.cpu.ipc 0.650325 # IPC: instructions per cycle +system.cpu.cpi 1.537712 # CPI: cycles per instruction +system.cpu.ipc 0.650317 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -451,11 +451,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits @@ -464,10 +464,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits -system.cpu.dcache.overall_hits::total 40710586 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits +system.cpu.dcache.overall_hits::total 40710587 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses @@ -478,16 +478,16 @@ system.cpu.dcache.demand_misses::cpu.data 2402 # n system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses system.cpu.dcache.overall_misses::total 2403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses @@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -564,26 +564,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id @@ -593,7 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits @@ -606,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 4664 # n system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses @@ -624,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4664 system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76244 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits @@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 3885 # nu system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 162646500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 134659500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 297306000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 162646500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) @@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.600000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses @@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution @@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 6994999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 46c589cfc..834ad990c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084938 # Number of seconds simulated -sim_ticks 84937723500 # Number of ticks simulated -final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085052 # Number of seconds simulated +sim_ticks 85051506000 # Number of ticks simulated +final_tick 85051506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178410 # Simulator instruction rate (inst/s) -host_op_rate 188074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87948168 # Simulator tick rate (ticks/s) -host_mem_usage 268236 # Number of bytes of host memory used -host_seconds 965.77 # Real time elapsed on the host +host_inst_rate 137318 # Simulator instruction rate (inst/s) +host_op_rate 144756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67782320 # Simulator tick rate (ticks/s) +host_mem_usage 272616 # Number of bytes of host memory used +host_seconds 1254.77 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory -system.physmem.bytes_read::total 790400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory -system.physmem.num_reads::total 12350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12351 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 192256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 914880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651584 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3004 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14295 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7661052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2260466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10756776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7661052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7661052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7661052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2260466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10756776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14295 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14295 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 914880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 790464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 914880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1113 # Per bank write bursts -system.physmem.perBankRdBursts::1 381 # Per bank write bursts -system.physmem.perBankRdBursts::2 5089 # Per bank write bursts -system.physmem.perBankRdBursts::3 423 # Per bank write bursts -system.physmem.perBankRdBursts::4 1959 # Per bank write bursts +system.physmem.perBankRdBursts::0 1374 # Per bank write bursts +system.physmem.perBankRdBursts::1 495 # Per bank write bursts +system.physmem.perBankRdBursts::2 5094 # Per bank write bursts +system.physmem.perBankRdBursts::3 807 # Per bank write bursts +system.physmem.perBankRdBursts::4 2274 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts -system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 373 # Per bank write bursts -system.physmem.perBankRdBursts::8 266 # Per bank write bursts -system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 324 # Per bank write bursts -system.physmem.perBankRdBursts::12 199 # Per bank write bursts -system.physmem.perBankRdBursts::13 249 # Per bank write bursts -system.physmem.perBankRdBursts::14 229 # Per bank write bursts -system.physmem.perBankRdBursts::15 543 # Per bank write bursts +system.physmem.perBankRdBursts::6 384 # Per bank write bursts +system.physmem.perBankRdBursts::7 621 # Per bank write bursts +system.physmem.perBankRdBursts::8 270 # Per bank write bursts +system.physmem.perBankRdBursts::9 230 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 348 # Per bank write bursts +system.physmem.perBankRdBursts::12 319 # Per bank write bursts +system.physmem.perBankRdBursts::13 267 # Per bank write bursts +system.physmem.perBankRdBursts::14 239 # Per bank write bursts +system.physmem.perBankRdBursts::15 795 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 84937714500 # Total gap between requests +system.physmem.totGap 85051447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 12351 # Read request sizes (log2) +system.physmem.readPktSize::6 14295 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -191,86 +191,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation -system.physmem.totQLat 171430514 # Total ticks spent queuing -system.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 61755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.242978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.732821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 121.093987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6415 73.25% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1879 21.45% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 191 2.18% 96.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 97 1.11% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 0.40% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 0.35% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 0.24% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 0.19% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8758 # Bytes accessed per row activation +system.physmem.totQLat 205669486 # Total ticks spent queuing +system.physmem.totMemAccLat 473700736 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14387.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33137.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.76 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5094 # Number of row buffer hits during reads +system.physmem.readRowHits 5530 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 38.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6876990.89 # Average gap between requests -system.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 5949734.00 # Average gap between requests +system.physmem.pageHitRate 38.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 56571480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 30867375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 89442600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.186004 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states -system.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_0.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 17335593540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 35823020250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 58890496125 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.426384 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 59484367239 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22725351261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9616320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5247000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21801000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.405119 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states -system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_1.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4216606920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 47330903250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 57139175370 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.834595 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 78723898183 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3485604317 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85626366 # Number of BP lookups -system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85633597 # Number of BP lookups +system.cpu.branchPred.condPredicted 68181299 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935035 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39958046 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38197568 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.594184 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683467 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81914 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681978 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 654112 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27866 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40296 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,97 +391,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 169875448 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 170103013 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5682904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347166765 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85633597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42535147 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 157608501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884039 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3989 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78333693 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18018 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169239484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.146393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.050401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17572638 10.38% 10.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30072408 17.77% 28.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31601234 18.67% 46.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89993204 53.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121866560 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108355768 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187780717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169239484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.503422 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.040921 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17519961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17356982 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121861075 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6734206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767260 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189821 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304987544 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27243895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767260 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37487022 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8574296 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 598391 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108353196 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8459319 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277412346 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13179472 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3059617 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 843440 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2298708 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 38369 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27077 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481431446 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187749796 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296450503 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005240 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23603 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216955908 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188454517 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23636 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23644 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13356506 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33916395 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14406588 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2541453 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1809916 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263792468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45987 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214404594 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5189732 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82202501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216956580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 771 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169239484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.266871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52525006 31.04% 31.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35947009 21.24% 52.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65510390 38.71% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13639375 8.06% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570056 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47432 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 216 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169239484 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35663808 66.17% 66.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153282 0.28% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available @@ -500,22 +500,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34308 0.06% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14056089 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3953676 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166984371 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919276 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued @@ -534,91 +534,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460481 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206631 0.10% 78.87% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31870339 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13371616 6.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214411803 # Type of FU issued -system.cpu.iq.rate 1.262171 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214404594 # Type of FU issued +system.cpu.iq.rate 1.260440 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53899365 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653186184 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344036614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204245973 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3951585 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011286 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266171590 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2132369 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1599233 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6020251 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7425 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7087 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1761954 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25499 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5767260 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5621824 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 63176 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263858489 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33916395 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14406588 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23579 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3874 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56135 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7087 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3147809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246868 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6394677 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207120469 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30635063 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7284125 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20217 # number of nop insts executed -system.cpu.iew.exec_refs 43771495 # number of memory reference insts executed -system.cpu.iew.exec_branches 44852998 # Number of branches executed -system.cpu.iew.exec_stores 13138140 # Number of stores executed -system.cpu.iew.exec_rate 1.219281 # Inst execution rate -system.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206057927 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129397136 # num instructions producing a value -system.cpu.iew.wb_consumers 221651580 # num instructions consuming a value -system.cpu.iew.wb_rate 1.212994 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20034 # number of nop insts executed +system.cpu.iew.exec_refs 43773548 # number of memory reference insts executed +system.cpu.iew.exec_branches 44851099 # Number of branches executed +system.cpu.iew.exec_stores 13138485 # Number of stores executed +system.cpu.iew.exec_rate 1.217618 # Inst execution rate +system.cpu.iew.wb_sent 206362307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206052365 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129396792 # num instructions producing a value +system.cpu.iew.wb_consumers 221653711 # num instructions consuming a value +system.cpu.iew.wb_rate 1.211339 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583779 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68665439 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5760276 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157944348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.150091 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.652266 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73354007 46.44% 46.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41142542 26.05% 72.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22532573 14.27% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9515365 6.02% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3551587 2.25% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2142504 1.36% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1329210 0.84% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1010049 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3366511 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157944348 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,83 +664,83 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 404773869 # The number of ROB reads -system.cpu.rob.rob_writes 511956769 # The number of ROB writes -system.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3366511 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 404888417 # The number of ROB reads +system.cpu.rob.rob_writes 511940612 # The number of ROB writes +system.cpu.timesIdled 9843 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 863529 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.985911 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads -system.cpu.ipc 1.014290 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218725741 # number of integer regfile reads -system.cpu.int_regfile_writes 114168991 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes -system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads -system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes -system.cpu.misc_regfile_reads 57440842 # number of misc regfile reads +system.cpu.cpi 0.987232 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987232 # CPI: Total CPI of All Threads +system.cpu.ipc 1.012933 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.012933 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218721236 # number of integer regfile reads +system.cpu.int_regfile_writes 114166498 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904044 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441835 # number of floating regfile writes +system.cpu.cc_regfile_reads 708181937 # number of cc regfile reads +system.cpu.cc_regfile_writes 229500026 # number of cc regfile writes +system.cpu.misc_regfile_reads 57441519 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72581 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72593 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.410345 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41032184 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73105 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.277396 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 509673500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.410345 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998848 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82362697 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82362697 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28645946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28645946 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits -system.cpu.dcache.overall_hits::total 40986622 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40987266 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40987266 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40987630 # number of overall hits +system.cpu.dcache.overall_hits::total 40987630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89269 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89269 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses -system.cpu.dcache.overall_misses::total 112319 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112236 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112236 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112352 # number of overall misses +system.cpu.dcache.overall_misses::total 112352 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1192862000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1192862000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244207999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244207999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1437069999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1437069999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1437069999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1437069999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28735215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28735215 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) @@ -749,70 +749,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41099502 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41099502 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41099982 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41099982 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003107 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003107 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8880.769231 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8880.769231 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12804.002272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12790.782532 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10626 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks -system.cpu.dcache.writebacks::total 72581 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64425 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8555 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8555 # number of WriteReq MSHR misses +system.cpu.dcache.blocked::no_targets 868 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.241935 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72593 # number of writebacks +system.cpu.dcache.writebacks::total 72593 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24834 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14410 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14410 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 739220499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 740182499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 72992 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72992 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73105 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 724757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 724757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85765499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85765499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 963000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 963000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 810522499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 810522499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 811485499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 811485499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses @@ -821,370 +821,373 @@ system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # 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Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001779 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11247.877706 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11247.877706 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10022.846675 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10022.846675 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8522.123894 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8522.123894 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11104.264837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11104.264837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11100.273565 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11100.273565 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53637 # number of replacements +system.cpu.icache.tags.tagsinuse 510.592571 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78276090 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54149 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1445.568524 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84288957500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.592571 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997251 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997251 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78269055 # 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1245757924 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1245757924 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1245757924 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1245757924 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78333663 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78333663 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78333663 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78333663 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78333663 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78333663 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # 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average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21637.884494 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21637.884494 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21637.884494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21637.884494 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76503 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 31 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20772.141274 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20772.141274 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20772.141274 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20772.141274 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20772.141274 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007385 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4005348 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4005348 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 64707 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64707 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 51067 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 51067 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8388 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 220162000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1008008136 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # 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average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 13357 # Total snoops (count) +system.cpu.l2cache.overall_mshr_miss_rate::total 0.119437 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33222.758689 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72811.440678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72811.440678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253485 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126250 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 904 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 903 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64481 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218803 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6898304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9324672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16222976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2352 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129607 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.087812 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118227 91.22% 91.22% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11379 8.78% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129607 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252972500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81228989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109661492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 12116 # Transaction distribution -system.membus.trans_dist::ReadExReq 234 # Transaction distribution -system.membus.trans_dist::ReadExResp 234 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 14295 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14059 # Transaction distribution +system.membus.trans_dist::ReadExReq 236 # Transaction distribution +system.membus.trans_dist::ReadExResp 236 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14059 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28590 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 914880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 914880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 12351 # Request fanout histogram +system.membus.snoop_fanout::samples 14295 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14295 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 12351 # Request fanout histogram -system.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14295 # Request fanout histogram +system.membus.reqLayer0.occupancy 18052130 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77159307 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index d24e062d1..c2d15923a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103324 # Number of seconds simulated -sim_ticks 103324153500 # Number of ticks simulated -final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.103278 # Number of seconds simulated +sim_ticks 103278421500 # Number of ticks simulated +final_tick 103278421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51505 # Simulator instruction rate (inst/s) -host_op_rate 86327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40294413 # Simulator tick rate (ticks/s) -host_mem_usage 304184 # Number of bytes of host memory used -host_seconds 2564.23 # Real time elapsed on the host +host_inst_rate 68420 # Simulator instruction rate (inst/s) +host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53503682 # Simulator tick rate (ticks/s) +host_mem_usage 309068 # Number of bytes of host memory used +host_seconds 1930.31 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory -system.physmem.bytes_read::total 361984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 362688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2240405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1262977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3503382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2240405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2240405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2240405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1262977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3503382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5656 # Number of read requests accepted +system.physmem.num_reads::total 5667 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2248214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1263536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3511750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2248214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2248214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2248214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1263536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3511750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5668 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5656 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5668 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 361984 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 362752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 361984 # Total read bytes from the system interface side +system.physmem.bytesReadSys 362752 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 310 # Per bank write bursts -system.physmem.perBankRdBursts::1 382 # Per bank write bursts -system.physmem.perBankRdBursts::2 476 # Per bank write bursts -system.physmem.perBankRdBursts::3 358 # Per bank write bursts -system.physmem.perBankRdBursts::4 362 # Per bank write bursts -system.physmem.perBankRdBursts::5 335 # Per bank write bursts -system.physmem.perBankRdBursts::6 419 # Per bank write bursts -system.physmem.perBankRdBursts::7 385 # Per bank write bursts +system.physmem.perBankRdBursts::0 314 # Per bank write bursts +system.physmem.perBankRdBursts::1 385 # Per bank write bursts +system.physmem.perBankRdBursts::2 471 # Per bank write bursts +system.physmem.perBankRdBursts::3 359 # Per bank write bursts +system.physmem.perBankRdBursts::4 360 # Per bank write bursts +system.physmem.perBankRdBursts::5 334 # Per bank write bursts +system.physmem.perBankRdBursts::6 420 # Per bank write bursts +system.physmem.perBankRdBursts::7 393 # Per bank write bursts system.physmem.perBankRdBursts::8 389 # Per bank write bursts -system.physmem.perBankRdBursts::9 295 # Per bank write bursts -system.physmem.perBankRdBursts::10 260 # Per bank write bursts -system.physmem.perBankRdBursts::11 270 # Per bank write bursts -system.physmem.perBankRdBursts::12 228 # Per bank write bursts -system.physmem.perBankRdBursts::13 484 # Per bank write bursts -system.physmem.perBankRdBursts::14 420 # Per bank write bursts +system.physmem.perBankRdBursts::9 296 # Per bank write bursts +system.physmem.perBankRdBursts::10 257 # Per bank write bursts +system.physmem.perBankRdBursts::11 272 # Per bank write bursts +system.physmem.perBankRdBursts::12 232 # Per bank write bursts +system.physmem.perBankRdBursts::13 487 # Per bank write bursts +system.physmem.perBankRdBursts::14 416 # Per bank write bursts system.physmem.perBankRdBursts::15 283 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103323899000 # Total gap between requests +system.physmem.totGap 103278386000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5656 # Read request sizes (log2) +system.physmem.readPktSize::6 5668 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,321 +187,321 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 286.278481 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.439317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.670037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 554 43.83% 43.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 264 20.89% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 105 8.31% 73.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 5.46% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 45 3.56% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.51% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 2.22% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.34% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 9.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1264 # Bytes accessed per row activation -system.physmem.totQLat 43672750 # Total ticks spent queuing -system.physmem.totMemAccLat 149722750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7721.49 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1276 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 283.335423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.570090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 315.354372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 562 44.04% 44.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 260 20.38% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 126 9.87% 74.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.09% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 2.98% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 4.08% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.51% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.96% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 9.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1276 # Bytes accessed per row activation +system.physmem.totQLat 44968750 # Total ticks spent queuing +system.physmem.totMemAccLat 151243750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7933.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26471.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26683.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4391 # Number of row buffer hits during reads +system.physmem.readRowHits 4387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18268016.09 # Average gap between requests -system.physmem.pageHitRate 77.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5624640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3069000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 23610600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 18221310.16 # Average gap between requests +system.physmem.pageHitRate 77.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5677560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3097875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 23649600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3147948405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 59232949500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 69161793345 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.369133 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 98535205500 # Time in different power states -system.physmem_0.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_0.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3123252585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 59226559500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 69127776960 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.342795 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 98524507750 # Time in different power states +system.physmem_0.memoryStateTime::REF 3448640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1338454000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1303957250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3931200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2145000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20490600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3969000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2165625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20412600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2964574845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.095685 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states -system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_1.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3000772125 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 59333991750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 69106850940 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.140248 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 98704275500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3448640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1124404000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40908032 # Number of BP lookups -system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40909998 # Number of BP lookups +system.cpu.branchPred.condPredicted 40909998 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6747980 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35338690 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3198330 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 606499 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35338690 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9879284 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25459406 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5040736 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206648308 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 206556844 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14935189 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 126 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 68758 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 764 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41261989 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1525874 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206453541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.416062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 46378865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 420308215 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40909998 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13077614 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152415438 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14966481 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 135 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 72789 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 564 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41283191 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1528436 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206357094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.419964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660932 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99211398 48.06% 48.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5135847 2.49% 50.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5374620 2.60% 53.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5328555 2.58% 55.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6013612 2.91% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5856529 2.84% 61.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5733209 2.78% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4747222 2.30% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 69052549 33.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99044157 48.00% 48.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5139433 2.49% 50.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5380650 2.61% 53.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5336666 2.59% 55.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6016483 2.92% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5851353 2.84% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5736237 2.78% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4733991 2.29% 66.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 69118124 33.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206453541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197960 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032586 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32305475 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86547165 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62440790 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17692517 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7467594 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 591140753 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7467594 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42099614 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46622929 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29580 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68917298 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41316526 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 552365156 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1615 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36415427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4818042 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 146051 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 629691896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1486514399 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 974943820 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15152274 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 206357094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.198057 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.034831 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32325248 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86371056 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62511253 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17666297 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7483240 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 591444337 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7483240 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42110583 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46566289 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29410 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68967744 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41199828 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 552624215 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1533 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36277086 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4842177 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 151976 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 630066400 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1487530571 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 975657611 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15077279 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 370262446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2381 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2386 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89347483 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128815998 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45923960 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77358410 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25275137 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 490566423 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 62065 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338414549 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1099553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 269265104 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 527048763 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60820 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206453541 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.639180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.804126 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 370636950 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2363 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2376 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89140950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128894590 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45939948 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77227738 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25186602 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 490698604 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 59973 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338566221 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1098463 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 269395193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 527209931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 58728 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206357094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640681 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805896 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73345677 35.53% 35.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46646037 22.59% 58.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32854801 15.91% 74.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20905072 10.13% 84.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15063521 7.30% 91.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8409386 4.07% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5213188 2.53% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2363320 1.14% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1652539 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73312584 35.53% 35.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46573584 22.57% 58.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32816576 15.90% 74.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20907210 10.13% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15065478 7.30% 91.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8412685 4.08% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5234413 2.54% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2370472 1.15% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1664092 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206453541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206357094 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 758238 19.31% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2733075 69.60% 88.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 435620 11.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 762770 19.47% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2718793 69.40% 88.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 436106 11.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211810 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216608884 64.01% 64.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 799973 0.24% 64.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7048329 2.08% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1813849 0.54% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 84312637 24.91% 92.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26619067 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211777 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216613901 63.98% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 799985 0.24% 64.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7047582 2.08% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1810682 0.53% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 84424015 24.94% 92.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26658279 7.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338414549 # Type of FU issued -system.cpu.iq.rate 1.637635 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3926933 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011604 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 880106724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 745207821 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 316030450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8202401 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15512263 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3567674 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 337013730 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4115942 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18154732 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 338566221 # Type of FU issued +system.cpu.iq.rate 1.639095 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3917669 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011571 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 880328489 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 745561228 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 316131833 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8177179 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15427221 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3556889 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 337169115 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4102998 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18179072 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72166411 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54986 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 863760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25408243 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 72245003 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55572 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 872144 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25424231 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50543 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50651 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7467594 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35770303 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 592137 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490628488 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1259959 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128815998 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45923960 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22654 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 545800 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38626 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 863760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1294864 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6880130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8174994 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326485130 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80685795 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11929419 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7483240 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35798970 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 583606 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490758577 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1261619 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128894590 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45939948 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 21909 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 539997 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 37637 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 872144 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1294345 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6884684 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8179029 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326602378 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80777118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11963843 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106318426 # number of memory reference insts executed -system.cpu.iew.exec_branches 18939296 # Number of branches executed -system.cpu.iew.exec_stores 25632631 # Number of stores executed -system.cpu.iew.exec_rate 1.579907 # Inst execution rate -system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256503247 # num instructions producing a value -system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value -system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 106442155 # number of memory reference insts executed +system.cpu.iew.exec_branches 18940356 # Number of branches executed +system.cpu.iew.exec_stores 25665037 # Number of stores executed +system.cpu.iew.exec_rate 1.581174 # Inst execution rate +system.cpu.iew.wb_sent 322715986 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319688722 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256576217 # num instructions producing a value +system.cpu.iew.wb_consumers 435723594 # num instructions consuming a value +system.cpu.iew.wb_rate 1.547703 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588851 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 269420821 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6753005 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163742250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.351901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.936120 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67180478 41.03% 41.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54846489 33.50% 74.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13227508 8.08% 82.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10675855 6.52% 89.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5434961 3.32% 92.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3126709 1.91% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1096647 0.67% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1147781 0.70% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7005822 4.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163742250 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -547,478 +547,469 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 647577665 # The number of ROB reads -system.cpu.rob.rob_writes 1024269930 # The number of ROB writes -system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7005822 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 647520633 # The number of ROB reads +system.cpu.rob.rob_writes 1024585644 # The number of ROB writes +system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199750 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524516370 # number of integer regfile reads -system.cpu.int_regfile_writes 289029189 # number of integer regfile writes -system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads -system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes -system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads -system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes -system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads +system.cpu.cpi 1.563981 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.563981 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639394 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639394 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524858514 # number of integer regfile reads +system.cpu.int_regfile_writes 289109549 # number of integer regfile writes +system.cpu.fp_regfile_reads 4527972 # number of floating regfile reads +system.cpu.fp_regfile_writes 3322072 # number of floating regfile writes +system.cpu.cc_regfile_reads 107078976 # number of cc regfile reads +system.cpu.cc_regfile_writes 65816113 # number of cc regfile writes +system.cpu.misc_regfile_reads 177007720 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72 # number of replacements -system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 77 # number of replacements +system.cpu.dcache.tags.tagsinuse 1524.395872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82831685 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2117 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39126.917808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits -system.cpu.dcache.overall_hits::total 82765643 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses -system.cpu.dcache.overall_misses::total 3286 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1524.395872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.372167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.372167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2040 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 411 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1479 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165670739 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165670739 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 62317357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62317357 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513773 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513773 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82831130 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82831130 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82831130 # number of overall hits +system.cpu.dcache.overall_hits::total 82831130 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1223 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1223 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1958 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1958 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3181 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3181 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3181 # number of overall misses +system.cpu.dcache.overall_misses::total 3181 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77985000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77985000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 124974000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124974000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 202959000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 202959000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 202959000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 202959000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62318580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62318580 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 82834311 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82834311 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82834311 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82834311 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000095 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63765.331153 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63765.331153 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63827.374872 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63827.374872 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63803.520905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63803.520905 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 403 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.777778 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 622 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 622 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1950 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1950 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47286500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47286500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 122663000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 122663000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 169949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 169949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 169949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 169949500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6515 # number of replacements -system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78679.700499 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78679.700499 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62904.102564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62904.102564 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6489 # number of replacements +system.cpu.icache.tags.tagsinuse 1681.757073 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41270224 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8478 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4867.919792 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses -system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits -system.cpu.icache.overall_hits::total 41248897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13089 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13089 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13089 # number of overall misses -system.cpu.icache.overall_misses::total 13089 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 485791000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 485791000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 485791000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 485791000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 485791000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 485791000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41261986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41261986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41261986 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41261986 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41261986 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41261986 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000317 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000317 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000317 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000317 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000317 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000317 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37114.447246 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6515 # number of writebacks -system.cpu.icache.writebacks::total 6515 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9001 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9001 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9001 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9001 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9001 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9001 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340708000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 340708000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340708000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 340708000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340708000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 340708000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.occ_blocks::cpu.inst 1681.757073 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.821170 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.821170 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1989 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 832 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 747 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.971191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 82575282 # Number of tag accesses +system.cpu.icache.tags.data_accesses 82575282 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 41270227 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41270227 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 41270227 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41270227 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 41270227 # number of overall hits +system.cpu.icache.overall_hits::total 41270227 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12961 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12961 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12961 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12961 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12961 # number of overall misses +system.cpu.icache.overall_misses::total 12961 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 483569000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 483569000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 483569000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 483569000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 483569000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 483569000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41283188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41283188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41283188 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41283188 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 41283188 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41283188 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000314 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000314 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000314 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000314 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000314 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000314 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37309.544017 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37309.544017 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37309.544017 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37309.544017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37309.544017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37309.544017 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1349 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53.960000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6489 # number of writebacks +system.cpu.icache.writebacks::total 6489 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4054 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4054 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4054 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4054 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4054 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4054 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8907 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8907 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8907 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8907 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8907 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 345609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 345609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 345609000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000216 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000216 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000216 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38801.953520 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38801.953520 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38801.953520 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38801.953520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3906.658043 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 11874 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5667 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.095289 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 389.769746 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073306 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.085353 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3628 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3628 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 528 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 528 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2040 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5668 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5668 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99707000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99707000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 244218500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 244218500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40155000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40155000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244218500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 139862000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 384080500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244218500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 139862000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 384080500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995392 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995392 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.881469 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.881469 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.535121 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.535121 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65943.783069 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65943.783069 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67314.911797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67314.911797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76051.136364 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76051.136364 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18024 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7043 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 507 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 32448 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11619 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.094328 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.292297 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 61 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 599 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23869 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1094080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 433 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 27712 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11458 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.082912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.275760 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10523 90.57% 90.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1096 9.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10508 91.71% 91.71% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 950 8.29% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11458 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15517998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13359000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3392501 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4149 # Transaction distribution -system.membus.trans_dist::UpgradeReq 500 # Transaction distribution -system.membus.trans_dist::ReadExReq 1507 # Transaction distribution -system.membus.trans_dist::ReadExResp 1507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 361984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 361984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 5668 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4155 # Transaction distribution +system.membus.trans_dist::ReadExReq 1512 # Transaction distribution +system.membus.trans_dist::ReadExResp 1512 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4156 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 362688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6156 # Request fanout histogram +system.membus.snoop_fanout::samples 5668 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5668 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6156 # Request fanout histogram -system.membus.reqLayer0.occupancy 7649501 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5668 # Request fanout histogram +system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30011250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30060000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |