diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
| commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
| tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff /tests/long/se | |
| parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
| download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz | |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Diffstat (limited to 'tests/long/se')
47 files changed, 2382 insertions, 2073 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 38958d98d..0c54e3227 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.062553 # Nu sim_ticks 62552970500 # Number of ticks simulated final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185964 # Simulator instruction rate (inst/s) -host_op_rate 186891 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 128391357 # Simulator tick rate (ticks/s) -host_mem_usage 403424 # Number of bytes of host memory used -host_seconds 487.21 # Real time elapsed on the host +host_inst_rate 423901 # Simulator instruction rate (inst/s) +host_op_rate 426012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292664487 # Simulator tick rate (ticks/s) +host_mem_usage 404124 # Number of bytes of host memory used +host_seconds 213.74 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction @@ -437,8 +439,10 @@ system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction -system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction +system.cpu.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 3b8f7cb56..4f68c8fbf 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.058675 # Nu sim_ticks 58675371500 # Number of ticks simulated final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111966 # Simulator instruction rate (inst/s) -host_op_rate 112523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72520515 # Simulator tick rate (ticks/s) -host_mem_usage 490592 # Number of bytes of host memory used -host_seconds 809.09 # Real time elapsed on the host +host_inst_rate 241655 # Simulator instruction rate (inst/s) +host_op_rate 242858 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 156520643 # Simulator tick rate (ticks/s) +host_mem_usage 492304 # Number of bytes of host memory used +host_seconds 374.87 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -515,7 +515,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available @@ -537,8 +539,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615894 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702925 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615891 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702910 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -549,7 +553,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued @@ -571,22 +577,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337772 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047242 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337764 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047220 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued system.cpu.iq.rate 0.863794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20102375 # FU busy when requested +system.cpu.iq.fu_busy_cnt 20102384 # FU busy when requested system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 467 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 238 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 247 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed @@ -665,7 +673,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction @@ -687,8 +697,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b27dfcb1b..ff7ca3031 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361613 # Nu sim_ticks 361613361500 # Number of ticks simulated final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1370596 # Simulator instruction rate (inst/s) -host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2032709522 # Simulator tick rate (ticks/s) -host_mem_usage 385816 # Number of bytes of host memory used -host_seconds 177.90 # Real time elapsed on the host +host_inst_rate 1844871 # Simulator instruction rate (inst/s) +host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2736100211 # Simulator tick rate (ticks/s) +host_mem_usage 385448 # Number of bytes of host memory used +host_seconds 132.16 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -65,7 +65,9 @@ system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Cl system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction @@ -87,8 +89,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index dac7009e5..48f2e7ba9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.066079 # Nu sim_ticks 66079350000 # Number of ticks simulated final_tick 66079350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104457 # Simulator instruction rate (inst/s) -host_op_rate 183932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43689609 # Simulator tick rate (ticks/s) -host_mem_usage 414668 # Number of bytes of host memory used -host_seconds 1512.47 # Real time elapsed on the host +host_inst_rate 185548 # Simulator instruction rate (inst/s) +host_op_rate 326721 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77606283 # Simulator tick rate (ticks/s) +host_mem_usage 417148 # Number of bytes of host memory used +host_seconds 851.47 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,7 +403,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available @@ -425,8 +427,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3544036 86.42% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 190508 4.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3544032 86.41% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 189377 4.62% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 6 0.00% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1660 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued @@ -437,7 +441,9 @@ system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 57.24% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.24% # Type of FU issued @@ -459,22 +465,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101489755 31.85% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34771062 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101489286 31.85% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34764932 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 469 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 6130 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 318634973 # Type of FU issued system.cpu.iq.rate 2.411003 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4100758 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012870 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 773602517 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 4101289 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012871 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 773603045 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 412934380 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 314305089 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 19287 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 19290 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 34996 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4478 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 322693854 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8537 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 322694382 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8540 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57471685 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 22103872 # Number of loads squashed @@ -553,7 +561,9 @@ system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction @@ -575,8 +585,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 90779371 32.63% 88.70% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 31439738 11.30% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 14 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 683cfaa02..141b0c04b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.366229 # Nu sim_ticks 366229314500 # Number of ticks simulated final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 561124 # Simulator instruction rate (inst/s) -host_op_rate 988050 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1300728257 # Simulator tick rate (ticks/s) -host_mem_usage 412916 # Number of bytes of host memory used -host_seconds 281.56 # Real time elapsed on the host +host_inst_rate 1002365 # Simulator instruction rate (inst/s) +host_op_rate 1765004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2323557450 # Simulator tick rate (ticks/s) +host_mem_usage 412036 # Number of bytes of host memory used +host_seconds 157.62 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -78,7 +78,9 @@ system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Cl system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction @@ -100,8 +102,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index ddf2151ed..61f620036 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.422343 # Nu sim_ticks 422342506500 # Number of ticks simulated final_tick 422342506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265332 # Simulator instruction rate (inst/s) -host_op_rate 265332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 183135937 # Simulator tick rate (ticks/s) -host_mem_usage 256400 # Number of bytes of host memory used -host_seconds 2306.17 # Real time elapsed on the host +host_inst_rate 474436 # Simulator instruction rate (inst/s) +host_op_rate 474436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 327462122 # Simulator tick rate (ticks/s) +host_mem_usage 257604 # Number of bytes of host memory used +host_seconds 1289.74 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -356,7 +356,9 @@ system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Cl system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction @@ -378,8 +380,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::MemRead 146565535 23.95% 90.65% # Class of committed instruction -system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 146469180 23.94% 90.63% # Class of committed instruction +system.cpu.op_class_0::MemWrite 57213427 9.35% 99.98% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 96355 0.02% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 7556 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 611901617 # Class of committed instruction diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 3968e09e7..3b6bf0c6f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.368600 # Nu sim_ticks 368600034500 # Number of ticks simulated final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189198 # Simulator instruction rate (inst/s) -host_op_rate 204927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137665575 # Simulator tick rate (ticks/s) -host_mem_usage 274600 # Number of bytes of host memory used -host_seconds 2677.50 # Real time elapsed on the host +host_inst_rate 368828 # Simulator instruction rate (inst/s) +host_op_rate 399489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 268368313 # Simulator tick rate (ticks/s) +host_mem_usage 276836 # Number of bytes of host memory used +host_seconds 1373.49 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -442,7 +442,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction @@ -465,7 +467,9 @@ system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Cl system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction -system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemWrite 56860206 10.36% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 48fa8fd80..36fb98963 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.236034 # Nu sim_ticks 236034256000 # Number of ticks simulated final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147811 # Simulator instruction rate (inst/s) -host_op_rate 160132 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69053974 # Simulator tick rate (ticks/s) -host_mem_usage 301356 # Number of bytes of host memory used -host_seconds 3418.11 # Real time elapsed on the host +host_inst_rate 253188 # Simulator instruction rate (inst/s) +host_op_rate 274292 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118283576 # Simulator tick rate (ticks/s) +host_mem_usage 302048 # Number of bytes of host memory used +host_seconds 1995.49 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -531,7 +531,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available @@ -553,8 +555,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44305814 32.74% 85.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19132145 14.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44305802 32.74% 85.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19132129 14.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 12 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -565,7 +569,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued @@ -587,22 +593,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133573210 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62394989 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133573188 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62394973 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 22 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued system.cpu.iq.rate 1.289866 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135340476 # FU busy when requested +system.cpu.iq.fu_busy_cnt 135340482 # FU busy when requested system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 106 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 112 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed @@ -681,7 +689,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction @@ -704,7 +714,9 @@ system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 6a67fce1b..15befb0d8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1206466 # Simulator instruction rate (inst/s) -host_op_rate 1306763 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 665324846 # Simulator tick rate (ticks/s) -host_mem_usage 263448 # Number of bytes of host memory used -host_seconds 419.89 # Real time elapsed on the host +host_inst_rate 2213544 # Simulator instruction rate (inst/s) +host_op_rate 2397561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220693561 # Simulator tick rate (ticks/s) +host_mem_usage 263256 # Number of bytes of host memory used +host_seconds 228.85 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Cl system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction @@ -216,7 +218,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 9780dac13..dc3d7ebff 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.708700 # Nu sim_ticks 708700329500 # Number of ticks simulated final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 820539 # Simulator instruction rate (inst/s) -host_op_rate 888607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1151553403 # Simulator tick rate (ticks/s) -host_mem_usage 275232 # Number of bytes of host memory used -host_seconds 615.43 # Real time elapsed on the host +host_inst_rate 1580290 # Simulator instruction rate (inst/s) +host_op_rate 1711383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2217795996 # Simulator tick rate (ticks/s) +host_mem_usage 275040 # Number of bytes of host memory used +host_seconds 319.55 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -194,7 +194,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Cl system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction @@ -217,7 +219,9 @@ system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Cl system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 97084638c..32b980d52 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.487015 # Nu sim_ticks 487015166000 # Number of ticks simulated final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125191 # Simulator instruction rate (inst/s) -host_op_rate 231667 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73737953 # Simulator tick rate (ticks/s) -host_mem_usage 321616 # Number of bytes of host memory used -host_seconds 6604.67 # Real time elapsed on the host +host_inst_rate 149671 # Simulator instruction rate (inst/s) +host_op_rate 276966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88156571 # Simulator tick rate (ticks/s) +host_mem_usage 323840 # Number of bytes of host memory used +host_seconds 5524.43 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -404,37 +404,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11212757 43.22% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11924633 45.96% 89.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2807188 10.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11212757 43.19% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11924633 45.93% 89.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2727831 10.51% 99.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 98893 0.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued @@ -445,7 +449,9 @@ system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued @@ -467,22 +473,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471201648 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186365855 9.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471201643 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 185912277 9.30% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 453578 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued system.cpu.iq.rate 2.052607 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25944578 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012977 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5000714674 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 25964114 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012987 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5000734134 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1300906 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 1300982 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021778795 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 552407 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 2021798255 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 552483 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed @@ -561,7 +569,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction @@ -585,6 +595,8 @@ system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15 system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 76b9b35da..e99a80294 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885773 # Nu sim_ticks 885772926000 # Number of ticks simulated final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 861241 # Simulator instruction rate (inst/s) -host_op_rate 1593729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 922618164 # Simulator tick rate (ticks/s) -host_mem_usage 273768 # Number of bytes of host memory used -host_seconds 960.06 # Real time elapsed on the host +host_inst_rate 1551014 # Simulator instruction rate (inst/s) +host_op_rate 2870153 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1661547121 # Simulator tick rate (ticks/s) +host_mem_usage 272636 # Number of bytes of host memory used +host_seconds 533.10 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -77,7 +77,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction @@ -101,6 +103,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 9b8e6bb2d..4f486e613 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.650924 # Nu sim_ticks 1650923912500 # Number of ticks simulated final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 598809 # Simulator instruction rate (inst/s) -host_op_rate 1108098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1195612149 # Simulator tick rate (ticks/s) -host_mem_usage 285816 # Number of bytes of host memory used -host_seconds 1380.82 # Real time elapsed on the host +host_inst_rate 1073233 # Simulator instruction rate (inst/s) +host_op_rate 1986019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2142868820 # Simulator tick rate (ticks/s) +host_mem_usage 285448 # Number of bytes of host memory used +host_seconds 770.43 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -78,7 +78,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Cl system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction @@ -102,6 +104,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index e0c918d80..2ec97b33e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.233641 # Nu sim_ticks 233641094500 # Number of ticks simulated final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295188 # Simulator instruction rate (inst/s) -host_op_rate 295188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172997788 # Simulator tick rate (ticks/s) -host_mem_usage 258004 # Number of bytes of host memory used -host_seconds 1350.54 # Real time elapsed on the host +host_inst_rate 449379 # Simulator instruction rate (inst/s) +host_op_rate 449379 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 263362780 # Simulator tick rate (ticks/s) +host_mem_usage 260228 # Number of bytes of host memory used +host_seconds 887.15 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -327,7 +327,9 @@ system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Cl system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction @@ -349,8 +351,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::MemRead 94754510 23.77% 81.56% # Class of committed instruction -system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 46072315 11.56% 69.35% # Class of committed instruction +system.cpu.op_class_0::MemWrite 30396984 7.62% 76.97% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 48682195 12.21% 89.18% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 43123780 10.82% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 1a8043b05..54dc9e079 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.064255 # Nu sim_ticks 64255452000 # Number of ticks simulated final_tick 64255452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260947 # Simulator instruction rate (inst/s) -host_op_rate 260947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44644346 # Simulator tick rate (ticks/s) -host_mem_usage 259540 # Number of bytes of host memory used -host_seconds 1439.27 # Real time elapsed on the host +host_inst_rate 443081 # Simulator instruction rate (inst/s) +host_op_rate 443081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75804731 # Simulator tick rate (ticks/s) +host_mem_usage 261252 # Number of bytes of host memory used +host_seconds 847.64 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -402,37 +402,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 128152674 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 253970 1.40% 1.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 1.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138834 0.77% 2.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 79013 0.44% 2.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3443745 19.00% 21.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1647907 9.09% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8047413 44.40% 75.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4509145 24.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 253970 1.29% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138834 0.71% 2.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 79013 0.40% 2.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3443745 17.54% 19.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1647907 8.39% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3789083 19.30% 47.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1973005 10.05% 57.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5150981 26.24% 83.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3150937 16.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued @@ -443,7 +447,9 @@ system.cpu.iq.FU_type_0::FloatAdd 36418443 9.36% 47.68% # Ty system.cpu.iq.FU_type_0::FloatCmp 7355119 1.89% 49.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 2800065 0.72% 50.29% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 16556449 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 1584163 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued @@ -465,22 +471,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99502948 25.57% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 75842088 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 48929897 12.57% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 31583157 8.11% 75.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 50573051 12.99% 88.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 44258931 11.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 389210637 # Type of FU issued system.cpu.iq.rate 3.028619 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18123623 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046565 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 592644502 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 19631071 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.050438 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 593561800 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 242185048 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 227933309 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332249256 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 332839406 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 166679024 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 158288157 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 234729597 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172571082 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 235646895 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 173161232 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 19364531 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 4980212 # Number of loads squashed @@ -559,7 +567,9 @@ system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Cl system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction @@ -581,8 +591,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 94754486 23.77% 81.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 46072297 11.56% 69.35% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 30396955 7.62% 76.97% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 48682189 12.21% 89.18% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 43123773 10.82% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 33645e09f..6d86d3450 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567393 # Nu sim_ticks 567392530500 # Number of ticks simulated final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 646502 # Simulator instruction rate (inst/s) -host_op_rate 646502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 920122456 # Simulator tick rate (ticks/s) -host_mem_usage 259072 # Number of bytes of host memory used -host_seconds 616.65 # Real time elapsed on the host +host_inst_rate 1833225 # Simulator instruction rate (inst/s) +host_op_rate 1833225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2609105944 # Simulator tick rate (ticks/s) +host_mem_usage 258692 # Number of bytes of host memory used +host_seconds 217.47 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -97,7 +97,9 @@ system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Cl system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction @@ -119,8 +121,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 94754511 23.77% 81.56% # Class of executed instruction -system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 46072316 11.56% 69.35% # Class of executed instruction +system.cpu.op_class::MemWrite 30396985 7.62% 76.97% # Class of executed instruction +system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index c3dd06017..d7f32d52d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225207 # Nu sim_ticks 225206521000 # Number of ticks simulated final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132189 # Simulator instruction rate (inst/s) -host_op_rate 158707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 109031633 # Simulator tick rate (ticks/s) -host_mem_usage 278744 # Number of bytes of host memory used -host_seconds 2065.52 # Real time elapsed on the host +host_inst_rate 284094 # Simulator instruction rate (inst/s) +host_op_rate 341086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 234325505 # Simulator tick rate (ticks/s) +host_mem_usage 279956 # Number of bytes of host memory used +host_seconds 961.08 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction @@ -437,8 +439,10 @@ system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction -system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 44185174 13.48% 62.20% # Class of committed instruction +system.cpu.op_class_0::MemWrite 55008381 16.78% 78.98% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 9802024db..fc2854304 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.122178 # Number of seconds simulated -sim_ticks 122177531500 # Number of ticks simulated -final_tick 122177531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.124291 # Number of seconds simulated +sim_ticks 124290972500 # Number of ticks simulated +final_tick 124290972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120262 # Simulator instruction rate (inst/s) -host_op_rate 144388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53814187 # Simulator tick rate (ticks/s) -host_mem_usage 292180 # Number of bytes of host memory used -host_seconds 2270.36 # Real time elapsed on the host +host_inst_rate 226846 # Simulator instruction rate (inst/s) +host_op_rate 272354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103264191 # Simulator tick rate (ticks/s) +host_mem_usage 292872 # Number of bytes of host memory used +host_seconds 1203.62 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1888192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14650048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169280 # Number of bytes read from this memory -system.physmem.bytes_read::total 16707520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1888192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1888192 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2645 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261055 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15454495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 119907874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1385525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136747893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15454495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15454495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15454495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 119907874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1385525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 136747893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261056 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1883840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14654016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 168640 # Number of bytes read from this memory +system.physmem.bytes_read::total 16706496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1883840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1883840 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2635 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261039 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15156692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117900888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1356816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134414396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15156692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15156692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15156692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117900888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1356816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134414396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261040 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261040 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16707584 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16706560 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16707584 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16706560 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1259 # Per bank write bursts -system.physmem.perBankRdBursts::1 69992 # Per bank write bursts -system.physmem.perBankRdBursts::2 1296 # Per bank write bursts -system.physmem.perBankRdBursts::3 10759 # Per bank write bursts +system.physmem.perBankRdBursts::1 69986 # Per bank write bursts +system.physmem.perBankRdBursts::2 1297 # Per bank write bursts +system.physmem.perBankRdBursts::3 10756 # Per bank write bursts system.physmem.perBankRdBursts::4 42908 # Per bank write bursts -system.physmem.perBankRdBursts::5 121819 # Per bank write bursts -system.physmem.perBankRdBursts::6 160 # Per bank write bursts -system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::5 121816 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 261 # Per bank write bursts system.physmem.perBankRdBursts::8 228 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts -system.physmem.perBankRdBursts::10 7776 # Per bank write bursts +system.physmem.perBankRdBursts::10 7773 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts system.physmem.perBankRdBursts::12 1213 # Per bank write bursts system.physmem.perBankRdBursts::13 743 # Per bank write bursts system.physmem.perBankRdBursts::14 662 # Per bank write bursts -system.physmem.perBankRdBursts::15 610 # Per bank write bursts +system.physmem.perBankRdBursts::15 611 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 122177522000 # Total gap between requests +system.physmem.totGap 124290963000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261056 # Read request sizes (log2) +system.physmem.readPktSize::6 261040 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43333 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,96 +191,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 248.480388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.727737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.056429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18253 27.15% 27.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21438 31.89% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11486 17.08% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6691 9.95% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4636 6.90% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2199 3.27% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1378 2.05% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 426 0.63% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 722 1.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67229 # Bytes accessed per row activation -system.physmem.totQLat 4621160381 # Total ticks spent queuing -system.physmem.totMemAccLat 9515960381 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17701.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.854084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.733686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.637928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18270 26.89% 26.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22179 32.64% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11425 16.82% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6866 10.11% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4751 6.99% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2068 3.04% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1319 1.94% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 392 0.58% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 673 0.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67943 # Bytes accessed per row activation +system.physmem.totQLat 4615275409 # Total ticks spent queuing +system.physmem.totMemAccLat 9509775409 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17680.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36451.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 136.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36430.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 136.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.41 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.07 # Data bus utilization in percentage -system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.05 # Data bus utilization in percentage +system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193817 # Number of row buffer hits during reads +system.physmem.readRowHits 193087 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 468012.69 # Average gap between requests -system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 445443180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 236747280 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773933000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 476137.61 # Average gap between requests +system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 450177000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239263365 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773833040 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9531222480.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4632019500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 224464800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45099806190 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3562907040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 919525950 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 66426265230 # Total energy per rank (pJ) -system.physmem_0.averagePower 543.686420 # Core power per rank (mW) -system.physmem_0.totalIdleTime 111434381144 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 154081000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4033332000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3253133750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9278182481 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6555604606 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 98903197663 # Time in different power states -system.physmem_1.actEnergy 34636140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18382980 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 89999700 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9685497120.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4649003790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227628000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45880019340 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3639028320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 957591945 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 67502066010 # Total energy per rank (pJ) +system.physmem_0.averagePower 543.097094 # Core power per rank (mW) +system.physmem_0.totalIdleTime 113501776163 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 155671000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4098592000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3412225500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9476337397 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6534800587 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 100613346016 # Time in different power states +system.physmem_1.actEnergy 35000280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18576525 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 89985420 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3038165520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 716380560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 121415040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10108537890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3723173760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 21583783695 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 39434924925 # Total energy per rank (pJ) -system.physmem_1.averagePower 322.767403 # Core power per rank (mW) -system.physmem_1.totalIdleTime 120289757500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 194586000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1289158000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 88425719250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9695988513 # Time in different power states -system.physmem_1.memoryStateTime::ACT 404030000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22168049737 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971486 # Number of BP lookups -system.cpu.branchPred.condPredicted 19267078 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984296 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894197 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923261 # Number of BTB hits +system.physmem_1.refreshEnergy 3070126800.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 722159790 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 122839680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10172185800 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3790789440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 22016840895 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 40039093920 # Total energy per rank (pJ) +system.physmem_1.averagePower 322.140000 # Core power per rank (mW) +system.physmem_1.totalIdleTime 122386077248 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 197400000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1302732000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 90206777750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9871788058 # Time in different power states +system.physmem_1.memoryStateTime::ACT 404763252 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22307511440 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35978086 # Number of BP lookups +system.cpu.branchPred.condPredicted 19268966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984583 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17896722 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923101 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.808806 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951889 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517219 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43864 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128904 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 77.796934 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6952398 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2517542 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473672 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43870 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 129186 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,234 +401,242 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 244355064 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 248581946 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12854090 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309386185 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348505 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 227028352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1990311 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1601 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3162 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82203694 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34298 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 240882453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.544883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12982171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309515100 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35978086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23349171 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 231243677 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1995433 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 3229 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82227465 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34636 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 245228486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.518257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300334 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 80675861 33.49% 33.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40201773 16.69% 50.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28081031 11.66% 61.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91923788 38.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 84781187 34.57% 34.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40505386 16.52% 51.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28011183 11.42% 62.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91930730 37.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 240882453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.147210 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.266134 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26812973 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 90710528 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98252382 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24245286 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 861284 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686689 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134210 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348538542 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3411137 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 861284 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43083632 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37000044 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289266 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105269732 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54378495 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344597413 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1451618 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7112089 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7460814 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27903739 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3277402 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394869828 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218091968 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335911643 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192912802 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 245228486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144733 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.245123 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27310570 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94773867 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 97190577 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25089647 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 863825 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6682147 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348416966 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3358743 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 863825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44033987 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38819082 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289712 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104520763 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56701117 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344543720 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1460141 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7869954 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94767 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 8436803 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28433094 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3429388 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394731046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217541719 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335903437 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192790757 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22639780 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11574 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57375410 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89984183 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84392474 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977179 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1898949 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343275804 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22622 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339466020 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 967573 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15486826 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37253539 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 502 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 240882453 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.409260 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.140571 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22500998 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11600 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11566 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 59469204 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89978957 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84398693 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2368147 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1979963 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343241150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22616 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339372334 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 953627 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15452166 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36722458 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 245228486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.383903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.138993 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60724616 25.21% 25.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76160793 31.62% 56.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59430978 24.67% 81.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34569007 14.35% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9283720 3.85% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 678664 0.28% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34675 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64185587 26.17% 26.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77296840 31.52% 57.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59648022 24.32% 82.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34412911 14.03% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 8897509 3.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 775021 0.32% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12596 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 240882453 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 245228486 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9218221 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7322 0.01% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 238834 0.20% 7.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 138891 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70679 0.06% 8.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68365 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 640804 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 296732 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 541759 0.46% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51504063 43.31% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56187426 47.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8796506 6.82% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7321 0.01% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 160578 0.12% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 165226 0.13% 7.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 81752 0.06% 7.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 59978 0.05% 7.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 823294 0.64% 7.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 313002 0.24% 8.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 382743 0.30% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27474499 21.29% 29.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41314471 32.01% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30691566 23.78% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 18785214 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108184064 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148340 0.63% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792701 2.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8634973 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210554 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20863316 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7179113 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141894 2.10% 48.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90024187 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518595 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108168622 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148105 0.63% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6799290 2.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8596304 2.53% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3207462 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592646 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20838335 6.14% 44.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175285 2.11% 46.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140600 2.10% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 46512146 13.71% 62.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 55971174 16.49% 79.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 43494368 12.82% 91.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 27552700 8.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339466020 # Type of FU issued -system.cpu.iq.rate 1.389233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 118913096 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350295 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756328552 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235151256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219171646 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283366610 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123646075 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116917582 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293624810 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164754306 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5408815 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339372334 # Type of FU issued +system.cpu.iq.rate 1.365233 # Inst issue rate +system.cpu.iq.fu_busy_cnt 129056150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.380279 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 765892553 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235176629 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219155615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 288090378 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123554179 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116971321 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 298827775 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169600709 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5587408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4251908 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7378 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2016857 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4246682 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7095 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14879 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2023076 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613330 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 158632 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537261 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 861284 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1350225 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1508994 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343299844 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 863825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1349614 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1747627 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343265167 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89984183 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84392474 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7652 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1502014 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 438026 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454508 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892534 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337437017 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89435625 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2029003 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89978957 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84398693 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11583 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6712 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1741146 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14879 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 437892 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454499 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892391 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337381646 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89446380 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1990688 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1418 # number of nop insts executed -system.cpu.iew.exec_refs 172563316 # number of memory reference insts executed -system.cpu.iew.exec_branches 31556143 # Number of branches executed -system.cpu.iew.exec_stores 83127691 # Number of stores executed -system.cpu.iew.exec_rate 1.380929 # Inst execution rate -system.cpu.iew.wb_sent 336235772 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336089228 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151786231 # num instructions producing a value -system.cpu.iew.wb_consumers 263562514 # num instructions consuming a value -system.cpu.iew.wb_rate 1.375413 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575902 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14164375 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1401 # number of nop insts executed +system.cpu.iew.exec_refs 172578078 # number of memory reference insts executed +system.cpu.iew.exec_branches 31542222 # Number of branches executed +system.cpu.iew.exec_stores 83131698 # Number of stores executed +system.cpu.iew.exec_rate 1.357225 # Inst execution rate +system.cpu.iew.wb_sent 336270787 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336126936 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153093104 # num instructions producing a value +system.cpu.iew.wb_consumers 267318257 # num instructions consuming a value +system.cpu.iew.wb_rate 1.352178 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572700 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14160521 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850425 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 238692959 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.373364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.035708 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 243036852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.044097 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 107534765 45.05% 45.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67583251 28.31% 73.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20880103 8.75% 82.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13256001 5.55% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8658859 3.63% 91.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4515867 1.89% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3014415 1.26% 94.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2598093 1.09% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10651605 4.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113296519 46.62% 46.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 65998128 27.16% 73.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21346559 8.78% 82.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13163754 5.42% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8182652 3.37% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4361649 1.79% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2983865 1.23% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2442147 1.00% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11261579 4.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 238692959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 243036852 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -647,7 +655,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction @@ -669,560 +679,563 @@ system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 44185201 13.48% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 55008399 16.78% 78.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 10651605 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 570015418 # The number of ROB reads -system.cpu.rob.rob_writes 686144847 # The number of ROB writes -system.cpu.timesIdled 39403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3472611 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 11261579 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 573745483 # The number of ROB reads +system.cpu.rob.rob_writes 686139464 # The number of ROB writes +system.cpu.timesIdled 39266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3353460 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.894951 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.894951 # CPI: Total CPI of All Threads -system.cpu.ipc 1.117379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.117379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325163205 # number of integer regfile reads -system.cpu.int_regfile_writes 134094196 # number of integer regfile writes -system.cpu.fp_regfile_reads 186638267 # number of floating regfile reads -system.cpu.fp_regfile_writes 131663703 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279409265 # number of cc regfile reads -system.cpu.cc_regfile_writes 80058845 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056731782 # number of misc regfile reads +system.cpu.cpi 0.910432 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.910432 # CPI: Total CPI of All Threads +system.cpu.ipc 1.098379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.098379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325197340 # number of integer regfile reads +system.cpu.int_regfile_writes 134110925 # number of integer regfile writes +system.cpu.fp_regfile_reads 186451715 # number of floating regfile reads +system.cpu.fp_regfile_writes 131763174 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279529156 # number of cc regfile reads +system.cpu.cc_regfile_writes 79965327 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056169060 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542799 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.841241 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162053309 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543311 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.003664 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542798 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161960642 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543310 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 104.943687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.841241 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999690 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333480485 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333480485 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81040424 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81040424 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921391 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921391 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69631 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69631 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 333233788 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333233788 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 80947765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 80947765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921307 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921307 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69703 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69703 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161961815 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161961815 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162031446 # number of overall hits -system.cpu.dcache.overall_hits::total 162031446 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2784008 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2784008 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131308 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131308 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161869072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161869072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161938775 # number of overall hits +system.cpu.dcache.overall_hits::total 161938775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2753247 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2753247 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131392 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131392 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915316 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915316 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915334 # number of overall misses -system.cpu.dcache.overall_misses::total 3915334 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47872980500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47872980500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9172353414 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9172353414 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3884639 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3884639 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3884657 # number of overall misses +system.cpu.dcache.overall_misses::total 3884657 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47533202500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47533202500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9194702918 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9194702918 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 57045333914 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 57045333914 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 57045333914 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 57045333914 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83824432 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83824432 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 56727905418 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56727905418 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56727905418 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56727905418 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83701012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83701012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69649 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69649 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69721 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69721 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165877131 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165877131 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165946780 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165946780 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165753711 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165753711 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165823432 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165823432 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032894 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032894 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013789 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013789 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.705077 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.705077 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8107.742024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8107.742024 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023436 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023436 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023426 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023426 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17264.416342 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17264.416342 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8126.894054 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8126.894054 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14569.790513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14569.790513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14569.723532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14569.723532 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14603.134401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14603.134401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14603.066736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14603.066736 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1090477 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1098365 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136210 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136254 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.005851 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542799 # number of writebacks -system.cpu.dcache.writebacks::total 1542799 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461435 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1461435 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910564 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910564 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.061158 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542798 # number of writebacks +system.cpu.dcache.writebacks::total 1542798 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1430654 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1430654 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910668 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910668 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2371999 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2371999 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2371999 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2371999 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322573 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322573 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2341322 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2341322 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2341322 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2341322 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322593 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322593 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845028694 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27108294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27108294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845527195 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845527195 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28987052694 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28987052694 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28988321694 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28988321694 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28953821695 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28953821695 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28955090695 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28955090695 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015801 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20522.136774 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20522.136774 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8358.228056 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8358.228056 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009311 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009311 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009307 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009307 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20496.323888 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20496.323888 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8361.243884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8361.243884 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115363.636364 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115363.636364 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18782.306353 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18782.306353 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18782.994732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18782.994732 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 725588 # number of replacements -system.cpu.icache.tags.tagsinuse 511.809147 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81470653 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726100 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.203075 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 346654500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.809147 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999627 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999627 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18760.774160 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18760.774160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18761.462693 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18761.462693 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 726144 # number of replacements +system.cpu.icache.tags.tagsinuse 511.811939 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81493663 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726656 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.148889 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 348619500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.811939 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999633 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999633 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165133459 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165133459 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81470653 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81470653 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81470653 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81470653 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81470653 # number of overall hits -system.cpu.icache.overall_hits::total 81470653 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 733019 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 733019 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 733019 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 733019 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 733019 # number of overall misses -system.cpu.icache.overall_misses::total 733019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8417582442 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8417582442 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8417582442 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8417582442 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8417582442 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8417582442 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82203672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82203672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82203672 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82203672 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82203672 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82203672 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008917 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008917 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008917 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008917 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008917 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.443733 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11483.443733 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11483.443733 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11483.443733 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 142274 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165181558 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165181558 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81493663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81493663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81493663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81493663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81493663 # number of overall hits +system.cpu.icache.overall_hits::total 81493663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 733780 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 733780 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 733780 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 733780 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 733780 # number of overall misses +system.cpu.icache.overall_misses::total 733780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8421387941 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8421387941 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8421387941 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8421387941 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8421387941 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8421387941 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82227443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82227443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82227443 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82227443 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82227443 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82227443 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008924 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008924 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008924 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008924 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008924 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008924 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11476.720463 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11476.720463 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11476.720463 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11476.720463 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 139290 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4376 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4412 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.512340 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.570716 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 725588 # number of writebacks -system.cpu.icache.writebacks::total 725588 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6903 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 6903 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 6903 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 6903 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 6903 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 6903 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726116 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726116 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726116 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726116 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726116 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726116 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7892899950 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7892899950 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7892899950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7892899950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7892899950 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7892899950 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10870.026208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10870.026208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 404432 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 404544 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue +system.cpu.icache.writebacks::writebacks 726144 # number of writebacks +system.cpu.icache.writebacks::total 726144 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7107 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7107 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7107 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7107 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7107 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7107 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726673 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726673 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726673 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726673 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726673 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726673 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7893866450 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7893866450 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7893866450 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7893866450 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7893866450 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7893866450 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008837 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008837 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008837 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008837 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10863.024290 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10863.024290 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10863.024290 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10863.024290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10863.024290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10863.024290 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 402240 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 402337 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 88 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28328 # 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Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 287.062738 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5152.962075 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 93.380354 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.314512 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005699 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.320211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 192 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 5156.372421 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 97.538128 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005953 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.320673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 189 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 103 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1140 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011719 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373596 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 70548166 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 70548166 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 968244 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 968244 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1045693 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2446651000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16670177500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19116828500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2446651000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16670177500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206290287 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19323118787 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172525 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172525 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113870 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172564 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172564 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113840 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137871 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3790.758771 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88424.657534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88424.657534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83022.895201 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83022.895201 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72903.283416 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72903.283416 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74102.534335 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61862.391277 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4537831 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268421 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51822 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51821 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137664 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3814.680406 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15470.588235 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15470.588235 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88102.165088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88102.165088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83117.645060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83117.645060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72755.860316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72755.860316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73980.102939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61837.344070 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4538943 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268977 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51443 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2048687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300143 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322572 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177738 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6807193 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92903808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290414848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55922 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2325285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131736 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338205 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2049252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726673 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179407 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629454 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6808861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92974976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197510912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290485888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55532 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2325451 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131557 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338010 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2018962 86.83% 86.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 306322 13.17% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2019523 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305927 13.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2325285 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4537302500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2325451 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4538413500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1089460423 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1090077361 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2314997455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2314996455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261072 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253753 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 261057 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260325 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 730 # Transaction distribution -system.membus.trans_dist::ReadExResp 730 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260326 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522127 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522127 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16707520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260300 # Transaction distribution +system.membus.trans_dist::UpgradeReq 17 # Transaction distribution +system.membus.trans_dist::ReadExReq 739 # Transaction distribution +system.membus.trans_dist::ReadExResp 739 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260301 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522096 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16706496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16706496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261072 # Request fanout histogram +system.membus.snoop_fanout::samples 261057 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261072 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261057 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261072 # Request fanout histogram -system.membus.reqLayer0.occupancy 329884354 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261057 # Request fanout histogram +system.membus.reqLayer0.occupancy 317283410 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1377672131 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1389540628 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index ec456bd8f..a62595a11 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 781022 # Simulator instruction rate (inst/s) -host_op_rate 937704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 577011080 # Simulator tick rate (ticks/s) -host_mem_usage 268872 # Number of bytes of host memory used -host_seconds 349.59 # Real time elapsed on the host +host_inst_rate 1476968 # Simulator instruction rate (inst/s) +host_op_rate 1773264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1091168515 # Simulator tick rate (ticks/s) +host_mem_usage 268416 # Number of bytes of host memory used +host_seconds 184.86 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 44185161 13.48% 62.20% # Class of executed instruction +system.cpu.op_class::MemWrite 55008376 16.78% 78.98% # Class of executed instruction +system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 81799693e..42d337cb5 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517298 # Nu sim_ticks 517297855500 # Number of ticks simulated final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 565388 # Simulator instruction rate (inst/s) -host_op_rate 678769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1072356714 # Simulator tick rate (ticks/s) -host_mem_usage 278352 # Number of bytes of host memory used -host_seconds 482.39 # Real time elapsed on the host +host_inst_rate 1075622 # Simulator instruction rate (inst/s) +host_op_rate 1291325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2040106124 # Simulator tick rate (ticks/s) +host_mem_usage 278152 # Number of bytes of host memory used +host_seconds 253.56 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -187,7 +187,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction @@ -209,8 +211,10 @@ system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 44185174 13.48% 62.20% # Class of executed instruction +system.cpu.op_class::MemWrite 55008381 16.78% 78.98% # Class of executed instruction +system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 40d44c1cb..42592acc9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.521167 # Nu sim_ticks 521167228000 # Number of ticks simulated final_tick 521167228000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258077 # Simulator instruction rate (inst/s) -host_op_rate 258077 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144813393 # Simulator tick rate (ticks/s) -host_mem_usage 260992 # Number of bytes of host memory used -host_seconds 3598.89 # Real time elapsed on the host +host_inst_rate 492017 # Simulator instruction rate (inst/s) +host_op_rate 492017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 276083455 # Simulator tick rate (ticks/s) +host_mem_usage 263220 # Number of bytes of host memory used +host_seconds 1887.72 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -351,7 +351,9 @@ system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Cl system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction @@ -373,8 +375,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction -system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 228135214 24.56% 88.39% # Class of committed instruction +system.cpu.op_class_0::MemWrite 94471145 10.17% 98.56% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 9570033 1.03% 99.59% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 3836926 0.41% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 928789150 # Class of committed instruction diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index d1e4abf0c..b479c4175 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.180965 # Nu sim_ticks 180964610500 # Number of ticks simulated final_tick 180964610500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216717 # Simulator instruction rate (inst/s) -host_op_rate 216717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46556270 # Simulator tick rate (ticks/s) -host_mem_usage 262532 # Number of bytes of host memory used -host_seconds 3887.01 # Real time elapsed on the host +host_inst_rate 431391 # Simulator instruction rate (inst/s) +host_op_rate 431391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92673550 # Simulator tick rate (ticks/s) +host_mem_usage 265016 # Number of bytes of host memory used +host_seconds 1952.71 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -429,37 +429,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 361665180 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3586644 19.39% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11792491 63.74% 83.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3122167 16.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3586644 18.56% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11632892 60.20% 78.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3008624 15.57% 94.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 913480 4.73% 99.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 182872 0.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued @@ -470,7 +474,9 @@ system.cpu.iq.FU_type_0::FloatAdd 13297886 1.53% 59.47% # Ty system.cpu.iq.FU_type_0::FloatCmp 3826557 0.44% 59.91% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued @@ -492,22 +498,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 244265808 28.02% 88.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 101807385 11.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 234518362 26.91% 87.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 97834915 11.22% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 9747446 1.12% 99.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 3972470 0.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 871651299 # Type of FU issued system.cpu.iq.rate 2.408347 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18501302 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2054197029 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 19324512 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2054837876 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 876768256 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 835988686 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69282679 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 69465042 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36778231 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 34166819 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855053167 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35098158 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 855694014 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35280521 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 65597237 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 7548743 # Number of loads squashed @@ -586,7 +594,9 @@ system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Cl system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction @@ -608,8 +618,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 237510597 25.58% 89.41% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 227943648 24.55% 88.38% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 94464282 10.17% 98.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 9566949 1.03% 99.59% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 3836918 0.41% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index efcf10ec9..fdd12f539 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1533629 # Simulator instruction rate (inst/s) -host_op_rate 1533629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 766980884 # Simulator tick rate (ticks/s) -host_mem_usage 251816 # Number of bytes of host memory used -host_seconds 605.48 # Real time elapsed on the host +host_inst_rate 2996785 # Simulator instruction rate (inst/s) +host_op_rate 2996785 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1498717563 # Simulator tick rate (ticks/s) +host_mem_usage 251436 # Number of bytes of host memory used +host_seconds 309.86 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Cl system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction @@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction -system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction +system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction +system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 7031d8335..b41b24d8c 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.288611 # Nu sim_ticks 1288611150500 # Number of ticks simulated final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1122029 # Simulator instruction rate (inst/s) -host_op_rate 1122029 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1557051854 # Simulator tick rate (ticks/s) -host_mem_usage 262324 # Number of bytes of host memory used -host_seconds 827.60 # Real time elapsed on the host +host_inst_rate 2016883 # Simulator instruction rate (inst/s) +host_op_rate 2016883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2798849858 # Simulator tick rate (ticks/s) +host_mem_usage 261432 # Number of bytes of host memory used +host_seconds 460.41 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,7 +104,9 @@ system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Cl system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction @@ -126,8 +128,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction -system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction +system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction +system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index d38edd9f8..7545f6451 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525654 # Nu sim_ticks 525654485500 # Number of ticks simulated final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213828 # Simulator instruction rate (inst/s) -host_op_rate 263250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 175444467 # Simulator tick rate (ticks/s) -host_mem_usage 278324 # Number of bytes of host memory used -host_seconds 2996.13 # Real time elapsed on the host +host_inst_rate 282925 # Simulator instruction rate (inst/s) +host_op_rate 348318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232138645 # Simulator tick rate (ticks/s) +host_mem_usage 279272 # Number of bytes of host memory used +host_seconds 2264.40 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -437,7 +437,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction @@ -459,8 +461,10 @@ system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction -system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction -system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction +system.cpu.op_class_0::MemWrite 125149823 15.87% 98.62% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 0a89473ad..8f8bc9d4d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.339013 # Nu sim_ticks 339012932000 # Number of ticks simulated final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140345 # Simulator instruction rate (inst/s) -host_op_rate 172783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74266222 # Simulator tick rate (ticks/s) -host_mem_usage 275384 # Number of bytes of host memory used -host_seconds 4564.83 # Real time elapsed on the host +host_inst_rate 218277 # Simulator instruction rate (inst/s) +host_op_rate 268728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115505586 # Simulator tick rate (ticks/s) +host_mem_usage 277356 # Number of bytes of host memory used +host_seconds 2935.04 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -538,37 +538,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66603323 24.62% 24.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 134116736 49.58% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69116750 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66603323 23.99% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18142 0.01% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 133475448 48.09% 72.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66440411 23.94% 96.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5100435 1.84% 98.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 5300037 1.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -579,7 +583,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued @@ -601,22 +607,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 266665907 31.01% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 157233466 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 259646740 30.19% 80.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153401509 17.84% 98.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 7019167 0.82% 99.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued system.cpu.iq.rate 1.268433 # Inst issue rate -system.cpu.iq.fu_busy_cnt 270491840 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2619781164 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 277574685 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.322750 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2622330507 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 57542493 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 62075995 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1098501615 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32020847 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 1101050958 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36554349 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed @@ -695,7 +703,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction @@ -717,8 +727,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index e76db2752..a0c974f67 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 969638 # Simulator instruction rate (inst/s) -host_op_rate 1193752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 598936996 # Simulator tick rate (ticks/s) -host_mem_usage 268708 # Number of bytes of host memory used -host_seconds 660.72 # Real time elapsed on the host +host_inst_rate 1825974 # Simulator instruction rate (inst/s) +host_op_rate 2248015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1127888505 # Simulator tick rate (ticks/s) +host_mem_usage 268260 # Number of bytes of host memory used +host_seconds 350.86 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Cl system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction -system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction +system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction +system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index c71a30606..8c0d9c5fc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.046047 # Nu sim_ticks 1046047111500 # Number of ticks simulated final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666714 # Simulator instruction rate (inst/s) -host_op_rate 819099 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1090788712 # Simulator tick rate (ticks/s) -host_mem_usage 278188 # Number of bytes of host memory used -host_seconds 958.98 # Real time elapsed on the host +host_inst_rate 1255251 # Simulator instruction rate (inst/s) +host_op_rate 1542152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2053674689 # Simulator tick rate (ticks/s) +host_mem_usage 277480 # Number of bytes of host memory used +host_seconds 509.35 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -194,7 +194,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Cl system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction @@ -216,8 +218,10 @@ system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction -system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction +system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction +system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 4a990b700..0d9a67eb8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061709 # Nu sim_ticks 61709224000 # Number of ticks simulated final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 242211 # Simulator instruction rate (inst/s) -host_op_rate 242211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 169006859 # Simulator tick rate (ticks/s) -host_mem_usage 262168 # Number of bytes of host memory used -host_seconds 365.13 # Real time elapsed on the host +host_inst_rate 484192 # Simulator instruction rate (inst/s) +host_op_rate 484192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 337853764 # Simulator tick rate (ticks/s) +host_mem_usage 263376 # Number of bytes of host memory used +host_seconds 182.65 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -353,7 +353,9 @@ system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Cl system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.40% # Class of committed instruction system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction @@ -375,8 +377,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::MemRead 20366786 23.03% 83.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 20366476 23.03% 83.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 14619024 16.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 310 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 6ed69f426..53a1c5599 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022820 # Nu sim_ticks 22819771500 # Number of ticks simulated final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186519 # Simulator instruction rate (inst/s) -host_op_rate 186519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53476835 # Simulator tick rate (ticks/s) -host_mem_usage 263708 # Number of bytes of host memory used -host_seconds 426.72 # Real time elapsed on the host +host_inst_rate 390933 # Simulator instruction rate (inst/s) +host_op_rate 390933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 112084385 # Simulator tick rate (ticks/s) +host_mem_usage 265424 # Number of bytes of host memory used +host_seconds 203.59 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -438,7 +438,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available @@ -460,8 +462,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168337 46.29% 55.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1114013 44.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168317 46.29% 55.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1113838 44.13% 99.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 25 0.00% 99.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 417 0.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -472,7 +476,9 @@ system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Ty system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 56.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -494,22 +500,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22887844 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15994084 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22887385 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15970151 18.03% 99.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 459 0.00% 99.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 23933 0.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued system.cpu.iq.rate 1.940728 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2523813 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028494 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223970382 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 2524060 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028497 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223970516 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611328 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 611441 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90791946 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305816 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 90792080 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305929 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed @@ -588,7 +596,9 @@ system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Cl system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.46% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction @@ -610,8 +620,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 20276331 22.95% 83.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 14611772 16.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 307 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index feef465f0..d9533629f 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.060131 # Nu sim_ticks 60130734500 # Number of ticks simulated final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142105 # Simulator instruction rate (inst/s) -host_op_rate 181732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120494644 # Simulator tick rate (ticks/s) -host_mem_usage 279144 # Number of bytes of host memory used -host_seconds 499.03 # Real time elapsed on the host +host_inst_rate 310652 # Simulator instruction rate (inst/s) +host_op_rate 397278 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 263409545 # Simulator tick rate (ticks/s) +host_mem_usage 281384 # Number of bytes of host memory used +host_seconds 228.28 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -441,7 +441,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction @@ -463,8 +465,10 @@ system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20555707 22.67% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6270a4a24..da2276c3c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.037982 # Nu sim_ticks 37982056000 # Number of ticks simulated final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105525 # Simulator instruction rate (inst/s) -host_op_rate 134954 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56525025 # Simulator tick rate (ticks/s) -host_mem_usage 282344 # Number of bytes of host memory used -host_seconds 671.95 # Real time elapsed on the host +host_inst_rate 220867 # Simulator instruction rate (inst/s) +host_op_rate 282464 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118308818 # Simulator tick rate (ticks/s) +host_mem_usage 284316 # Number of bytes of host memory used +host_seconds 321.04 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -527,7 +527,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available @@ -549,8 +551,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11088474 37.25% 59.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11940322 40.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11088448 37.25% 59.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11940306 40.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -561,7 +565,9 @@ system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.28% # Type of FU issued @@ -583,22 +589,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23958877 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21133721 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23958815 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21133689 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 62 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued system.cpu.iq.rate 1.243808 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29765517 # FU busy when requested +system.cpu.iq.fu_busy_cnt 29765526 # FU busy when requested system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 335 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 183 # Number of floating point alu accesses +system.cpu.iq.fp_alu_accesses 192 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed @@ -677,7 +685,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction @@ -699,8 +709,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20555706 22.67% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 5d202194f..d9427be27 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.241902 # Nu sim_ticks 1241902335500 # Number of ticks simulated final_tick 1241902335500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311711 # Simulator instruction rate (inst/s) -host_op_rate 311711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 211957790 # Simulator tick rate (ticks/s) -host_mem_usage 254092 # Number of bytes of host memory used -host_seconds 5859.20 # Real time elapsed on the host +host_inst_rate 473348 # Simulator instruction rate (inst/s) +host_op_rate 473348 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 321867657 # Simulator tick rate (ticks/s) +host_mem_usage 255296 # Number of bytes of host memory used +host_seconds 3858.43 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -366,7 +366,9 @@ system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Cl system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction @@ -388,8 +390,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::MemRead 449492741 24.61% 91.11% # Class of committed instruction -system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 449492662 24.61% 91.11% # Class of committed instruction +system.cpu.op_class_0::MemWrite 162429751 8.89% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 55 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1826378509 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index d6615dc1b..6249c394a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.684200 # Nu sim_ticks 684199968000 # Number of ticks simulated final_tick 684199968000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 209715 # Simulator instruction rate (inst/s) -host_op_rate 209715 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82651888 # Simulator tick rate (ticks/s) -host_mem_usage 254604 # Number of bytes of host memory used -host_seconds 8278.09 # Real time elapsed on the host +host_inst_rate 295566 # Simulator instruction rate (inst/s) +host_op_rate 295566 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 116486932 # Simulator tick rate (ticks/s) +host_mem_usage 257340 # Number of bytes of host memory used +host_seconds 5873.62 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,7 +449,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.86% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.86% # attempts to use FU when none available @@ -471,8 +473,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.86% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18955564 51.66% 87.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4577828 12.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18955559 51.65% 87.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4574949 12.47% 99.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 21 0.00% 99.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 8342 0.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -483,7 +487,9 @@ system.cpu.iq.FU_type_0::FloatAdd 895059 0.03% 65.56% # Ty system.cpu.iq.FU_type_0::FloatCmp 21 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued @@ -505,22 +511,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671607156 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230690638 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671606942 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230625627 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 214 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 65011 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 2620166340 # Type of FU issued system.cpu.iq.rate 1.914766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36691137 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014003 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6644947058 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 36696616 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014005 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6644950011 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 4031627633 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 2518705843 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1938210 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 1940736 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 1246935 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 885827 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655891113 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 966364 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 2655894066 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 968890 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69399237 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 272696697 # Number of loads squashed @@ -599,7 +607,9 @@ system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Cl system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction @@ -621,8 +631,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 444595584 24.43% 91.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 160728448 8.83% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 54 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 5f8a25a7f..9f7e15391 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1729437 # Simulator instruction rate (inst/s) -host_op_rate 1729437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 867853739 # Simulator tick rate (ticks/s) -host_mem_usage 243124 # Number of bytes of host memory used -host_seconds 1052.24 # Real time elapsed on the host +host_inst_rate 3052391 # Simulator instruction rate (inst/s) +host_op_rate 3052390 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1531729085 # Simulator tick rate (ticks/s) +host_mem_usage 242484 # Number of bytes of host memory used +host_seconds 596.18 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -103,7 +103,9 @@ system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Cl system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction @@ -125,8 +127,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction +system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 622e92943..6af37cfb2 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.639614 # Nu sim_ticks 2639613874500 # Number of ticks simulated final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1111155 # Simulator instruction rate (inst/s) -host_op_rate 1111155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1611744129 # Simulator tick rate (ticks/s) -host_mem_usage 254908 # Number of bytes of host memory used -host_seconds 1637.74 # Real time elapsed on the host +host_inst_rate 2013574 # Simulator instruction rate (inst/s) +host_op_rate 2013574 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2920714569 # Simulator tick rate (ticks/s) +host_mem_usage 253500 # Number of bytes of host memory used +host_seconds 903.76 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,7 +104,9 @@ system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Cl system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction @@ -126,8 +128,10 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction +system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 16fb45e1d..20e951f6a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.150226 # Nu sim_ticks 1150225722500 # Number of ticks simulated final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 267770 # Simulator instruction rate (inst/s) -host_op_rate 288482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 199406485 # Simulator tick rate (ticks/s) -host_mem_usage 271372 # Number of bytes of host memory used -host_seconds 5768.25 # Real time elapsed on the host +host_inst_rate 386915 # Simulator instruction rate (inst/s) +host_op_rate 416843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 288133243 # Simulator tick rate (ticks/s) +host_mem_usage 273608 # Number of bytes of host memory used +host_seconds 3991.99 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -448,7 +448,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction @@ -470,8 +472,10 @@ system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction -system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction +system.cpu.op_class_0::MemWrite 174847022 10.51% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index ea5c16164..3e40b495b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.787742 # Nu sim_ticks 787742202500 # Number of ticks simulated final_tick 787742202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201500 # Simulator instruction rate (inst/s) -host_op_rate 217086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 102767126 # Simulator tick rate (ticks/s) -host_mem_usage 327820 # Number of bytes of host memory used -host_seconds 7665.31 # Real time elapsed on the host +host_inst_rate 267668 # Simulator instruction rate (inst/s) +host_op_rate 288372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 136513298 # Simulator tick rate (ticks/s) +host_mem_usage 329792 # Number of bytes of host memory used +host_seconds 5770.44 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -539,7 +539,9 @@ system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # at system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available @@ -561,8 +563,10 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191460462 47.22% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47920671 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191460455 47.22% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47920650 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -573,7 +577,9 @@ system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued @@ -595,22 +601,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532139540 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186322827 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532139508 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186322803 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 32 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1857513748 # Type of FU issued system.cpu.iq.rate 1.179011 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405481908 # FU busy when requested +system.cpu.iq.fu_busy_cnt 405481927 # FU busy when requested system.cpu.iq.fu_busy_rate 0.218293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5709408399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 5709408400 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2231939413 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1805717250 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 255 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262995523 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 2262995524 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 151 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 17822173 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 84257734 # Number of loads squashed @@ -689,7 +697,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction @@ -711,8 +721,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index ddb5178a1..4d1539e1f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1176831 # Simulator instruction rate (inst/s) -host_op_rate 1267857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 633929666 # Simulator tick rate (ticks/s) -host_mem_usage 260476 # Number of bytes of host memory used -host_seconds 1312.48 # Real time elapsed on the host +host_inst_rate 2178592 # Simulator instruction rate (inst/s) +host_op_rate 2347103 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1173553065 # Simulator tick rate (ticks/s) +host_mem_usage 260024 # Number of bytes of host memory used +host_seconds 708.97 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Cl system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 02e32a48c..11abffe81 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.379922 # Nu sim_ticks 2379921906500 # Number of ticks simulated final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 802178 # Simulator instruction rate (inst/s) -host_op_rate 864460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1240688848 # Simulator tick rate (ticks/s) -host_mem_usage 272000 # Number of bytes of host memory used -host_seconds 1918.23 # Real time elapsed on the host +host_inst_rate 1526036 # Simulator instruction rate (inst/s) +host_op_rate 1644518 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2360243305 # Simulator tick rate (ticks/s) +host_mem_usage 271808 # Number of bytes of host memory used +host_seconds 1008.34 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -194,7 +194,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Cl system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction @@ -216,8 +218,10 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index e4956c5fa..86df30690 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 913315 # Simulator instruction rate (inst/s) -host_op_rate 1423027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 864105629 # Simulator tick rate (ticks/s) -host_mem_usage 264708 # Number of bytes of host memory used -host_seconds 3293.59 # Real time elapsed on the host +host_inst_rate 1654731 # Simulator instruction rate (inst/s) +host_op_rate 2578221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1565575242 # Simulator tick rate (ticks/s) +host_mem_usage 262288 # Number of bytes of host memory used +host_seconds 1817.87 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -77,7 +77,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Cl system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction @@ -101,6 +103,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 3b577baaf..037ceb011 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.898831 # Nu sim_ticks 5898831348500 # Number of ticks simulated final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 637466 # Simulator instruction rate (inst/s) -host_op_rate 993229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1250066735 # Simulator tick rate (ticks/s) -host_mem_usage 275724 # Number of bytes of host memory used -host_seconds 4718.81 # Real time elapsed on the host +host_inst_rate 1175665 # Simulator instruction rate (inst/s) +host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2305472192 # Simulator tick rate (ticks/s) +host_mem_usage 275096 # Number of bytes of host memory used +host_seconds 2558.62 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -78,7 +78,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Cl system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction @@ -102,6 +104,8 @@ system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Cl system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 2c8dfca63..40657583a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053438 # Nu sim_ticks 53437621500 # Number of ticks simulated final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 247892 # Simulator instruction rate (inst/s) -host_op_rate 247892 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144138078 # Simulator tick rate (ticks/s) -host_mem_usage 256712 # Number of bytes of host memory used -host_seconds 370.74 # Real time elapsed on the host +host_inst_rate 468238 # Simulator instruction rate (inst/s) +host_op_rate 468238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272260061 # Simulator tick rate (ticks/s) +host_mem_usage 257916 # Number of bytes of host memory used +host_seconds 196.27 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -327,7 +327,9 @@ system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Cl system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction @@ -349,8 +351,10 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 19433628 21.15% 92.31% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6424338 6.99% 99.30% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 76788 0.08% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 2ed297d74..bb93c695e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.021955 # Nu sim_ticks 21954917500 # Number of ticks simulated final_tick 21954917500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181107 # Simulator instruction rate (inst/s) -host_op_rate 181107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47234568 # Simulator tick rate (ticks/s) -host_mem_usage 257228 # Number of bytes of host memory used -host_seconds 464.81 # Real time elapsed on the host +host_inst_rate 353144 # Simulator instruction rate (inst/s) +host_op_rate 353144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92103562 # Simulator tick rate (ticks/s) +host_mem_usage 259964 # Number of bytes of host memory used +host_seconds 238.37 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -401,37 +401,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 43616730 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 484010 20.16% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1012503 42.17% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 694860 28.94% 93.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 162157 6.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 484010 20.07% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1012503 41.99% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 682717 28.32% 92.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160804 6.67% 99.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 21053 0.87% 99.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 2406 0.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued @@ -442,7 +446,9 @@ system.cpu.iq.FU_type_0::FloatAdd 2847523 2.85% 64.15% # Ty system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 2443321 2.45% 66.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 314198 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.03% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued @@ -464,22 +470,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24854622 24.91% 92.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7268455 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24115562 24.17% 91.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7190219 7.21% 99.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 739060 0.74% 99.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 78236 0.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 99762246 # Type of FU issued system.cpu.iq.rate 2.271979 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2401186 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024069 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229973015 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 2411149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024169 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229977416 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 129921960 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 89757276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15688832 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 15694394 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 9653681 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7189481 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93781523 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8381902 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 93785924 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8387464 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1923320 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 6908286 # Number of loads squashed @@ -558,7 +566,9 @@ system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Cl system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction @@ -580,8 +590,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 19996198 21.76% 92.93% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 19433618 21.15% 92.31% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6424318 6.99% 99.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 76785 0.08% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 26e7200e9..f4cf26547 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132539 # Nu sim_ticks 132538562500 # Number of ticks simulated final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171463 # Simulator instruction rate (inst/s) -host_op_rate 180750 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131881088 # Simulator tick rate (ticks/s) -host_mem_usage 273644 # Number of bytes of host memory used -host_seconds 1004.99 # Real time elapsed on the host +host_inst_rate 360845 # Simulator instruction rate (inst/s) +host_op_rate 380389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 277544932 # Simulator tick rate (ticks/s) +host_mem_usage 274852 # Number of bytes of host memory used +host_seconds 477.54 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction @@ -437,8 +439,10 @@ system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Cl system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction -system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction -system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction +system.cpu.op_class_0::MemWrite 12498389 6.88% 99.62% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 04ea23c2f..17a991711 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.086053 # Number of seconds simulated -sim_ticks 86053034000 # Number of ticks simulated -final_tick 86053034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.086155 # Number of seconds simulated +sim_ticks 86154694000 # Number of ticks simulated +final_tick 86154694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114393 # Simulator instruction rate (inst/s) -host_op_rate 120589 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57131119 # Simulator tick rate (ticks/s) -host_mem_usage 270696 # Number of bytes of host memory used -host_seconds 1506.24 # Real time elapsed on the host +host_inst_rate 235949 # Simulator instruction rate (inst/s) +host_op_rate 248729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 117978801 # Simulator tick rate (ticks/s) +host_mem_usage 272668 # Number of bytes of host memory used +host_seconds 730.26 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 652224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 193472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 70848 # Number of bytes read from this memory -system.physmem.bytes_read::total 916544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 652224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 652224 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10191 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1107 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14321 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7579326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2248288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 823306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10650920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7579326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7579326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7579326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2248288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 823306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10650920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14321 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 652480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 193344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 916864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 652480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 652480 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7573354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2244149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 824563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10642067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7573354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7573354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7573354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2244149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 824563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10642067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14326 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14321 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14326 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 916544 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916864 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 916544 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916864 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1378 # Per bank write bursts -system.physmem.perBankRdBursts::1 501 # Per bank write bursts -system.physmem.perBankRdBursts::2 5089 # Per bank write bursts -system.physmem.perBankRdBursts::3 804 # Per bank write bursts -system.physmem.perBankRdBursts::4 2285 # Per bank write bursts +system.physmem.perBankRdBursts::0 1380 # Per bank write bursts +system.physmem.perBankRdBursts::1 498 # Per bank write bursts +system.physmem.perBankRdBursts::2 5094 # Per bank write bursts +system.physmem.perBankRdBursts::3 810 # Per bank write bursts +system.physmem.perBankRdBursts::4 2279 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts system.physmem.perBankRdBursts::6 384 # Per bank write bursts system.physmem.perBankRdBursts::7 628 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts system.physmem.perBankRdBursts::9 231 # Per bank write bursts -system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 348 # Per bank write bursts -system.physmem.perBankRdBursts::12 321 # Per bank write bursts +system.physmem.perBankRdBursts::10 355 # Per bank write bursts +system.physmem.perBankRdBursts::11 347 # Per bank write bursts +system.physmem.perBankRdBursts::12 322 # Per bank write bursts system.physmem.perBankRdBursts::13 267 # Per bank write bursts system.physmem.perBankRdBursts::14 240 # Per bank write bursts system.physmem.perBankRdBursts::15 797 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 86052975500 # Total gap between requests +system.physmem.totGap 86154635500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14321 # Read request sizes (log2) +system.physmem.readPktSize::6 14326 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8480 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 108.022642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.441459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 123.287712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5899 69.56% 69.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2101 24.78% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 209 2.46% 96.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 89 1.05% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41 0.48% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 0.42% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15 0.18% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13 0.15% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 77 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8480 # Bytes accessed per row activation -system.physmem.totQLat 1499260235 # Total ticks spent queuing -system.physmem.totMemAccLat 1767778985 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 104689.63 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8486 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.983974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.597492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 122.302837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5884 69.34% 69.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2105 24.81% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 256 3.02% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 62 0.73% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 39 0.46% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 0.44% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 0.19% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9 0.11% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 78 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8486 # Bytes accessed per row activation +system.physmem.totQLat 1505073312 # Total ticks spent queuing +system.physmem.totMemAccLat 1773685812 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 105058.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 123439.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 10.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 123808.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 10.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.08 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 0.08 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5837 # Number of row buffer hits during reads +system.physmem.readRowHits 5836 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.76 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6008866.39 # Average gap between requests -system.physmem.pageHitRate 40.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 82060020 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6013865.38 # Average gap between requests +system.physmem.pageHitRate 40.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51536520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27380925 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 82088580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5180800560.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1120628550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 275264640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12259963560 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8345872320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9276913815 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 36622770765 # Total energy per rank (pJ) -system.physmem_0.averagePower 425.583720 # Core power per rank (mW) -system.physmem_0.totalIdleTime 82871785017 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 531109000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2203210000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34253599252 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21734056085 # Time in different power states -system.physmem_0.memoryStateTime::ACT 445220983 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 26885838680 # Time in different power states -system.physmem_1.actEnergy 9017820 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4789290 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20191920 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 5189405520.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1121826120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 276469440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12277996650 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8345487360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9295531755 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36669774810 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.627121 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82968376764 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 533443000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2206916000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34311542002 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21733088112 # Time in different power states +system.physmem_0.memoryStateTime::ACT 444281236 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26925423650 # Time in different power states +system.physmem_1.actEnergy 9082080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4823445 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20199060 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 882623040.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 198112620 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 50847360 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1971627720 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1393669440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18810725700 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23341907430 # Total energy per rank (pJ) -system.physmem_1.averagePower 271.250252 # Core power per rank (mW) -system.physmem_1.totalIdleTime 85485463257 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 101360000 # Time in different power states -system.physmem_1.memoryStateTime::REF 375610000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 77532398500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3629358146 # Time in different power states -system.physmem_1.memoryStateTime::ACT 90573993 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 4323733361 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85625838 # Number of BP lookups -system.cpu.branchPred.condPredicted 68176243 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5935432 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39943176 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38184524 # Number of BTB hits +system.physmem_1.refreshEnergy 885081600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198834810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 51009600 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1986610170 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1389476160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18829930140 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23375329815 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.318119 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85585158757 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 101660000 # Time in different power states +system.physmem_1.memoryStateTime::REF 376638000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77610163250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3618418671 # Time in different power states +system.physmem_1.memoryStateTime::ACT 91210493 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4356603586 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85641138 # Number of BP lookups +system.cpu.branchPred.condPredicted 68185958 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5937589 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39953535 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38189781 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.597115 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683485 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81916 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681521 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653387 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 28134 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40344 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.585487 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3685328 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81910 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681706 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653811 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27895 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40302 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,137 +401,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 172106069 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 172309389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5685351 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347171735 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85625838 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42521396 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158200265 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11884759 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 4307 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78326471 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18089 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169836333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.138878 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.056220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5689865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347272234 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85641138 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42528920 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158389740 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11889123 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 4192 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78352490 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18126 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 170032695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.057606 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18169241 10.70% 10.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30071574 17.71% 28.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31598899 18.61% 47.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89996619 52.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18322538 10.78% 10.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30071394 17.69% 28.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31619936 18.60% 47.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90018827 52.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169836333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.497518 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.017196 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17522714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17948295 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121866676 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6730979 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5767669 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11064280 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189793 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304996623 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27241409 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5767669 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37489750 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8834769 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 601523 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108355832 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8786790 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277419061 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13180458 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3061814 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 846087 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2626546 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 39334 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27085 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481448286 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187772528 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296460965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3003847 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 170032695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.497020 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.015399 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17554898 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18106153 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121828666 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6773205 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5769773 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11065170 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189895 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 305047176 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27240886 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5769773 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37541623 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8963730 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 601187 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108324902 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8831480 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277455959 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13183896 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3097230 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842604 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2610060 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 40707 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26842 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481461567 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187957820 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296507996 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005110 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188471357 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23624 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13352846 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33915531 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14406995 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2538352 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1801972 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263797881 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45980 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214410891 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5187410 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82207907 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216953193 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 764 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169836333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.262456 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.019138 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188484638 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23626 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23627 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13450862 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33923289 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14424821 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2554501 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1823311 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263831896 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45982 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214447255 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5189742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82241924 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216953797 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 766 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 170032695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.261212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018500 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53122752 31.28% 31.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35940807 21.16% 52.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65514665 38.58% 91.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13639448 8.03% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571104 0.93% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47348 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 209 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53222567 31.30% 31.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36044522 21.20% 52.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65538005 38.54% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13630055 8.02% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1551450 0.91% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45818 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 278 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169836333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 170032695 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35657368 66.16% 66.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153250 0.28% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35732 0.07% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 954 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34277 0.06% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14055726 26.08% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3956441 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35671912 66.13% 66.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153261 0.28% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35713 0.07% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 264 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 557 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 40113 0.07% 66.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13911271 25.79% 92.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3849843 7.14% 99.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 142059 0.26% 99.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 136275 0.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166991462 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919191 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167013253 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919503 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued @@ -544,91 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33016 0.02% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 165181 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245709 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460330 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206622 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245720 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460387 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206623 0.10% 78.86% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31869240 14.86% 93.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13372180 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31297547 14.59% 93.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13233764 6.17% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 576685 0.27% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 147618 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214410891 # Type of FU issued -system.cpu.iq.rate 1.245807 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53895257 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251364 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653788467 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344049655 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204252570 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2009022 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 214447255 # Type of FU issued +system.cpu.iq.rate 1.244548 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53942541 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251542 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654066032 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344116098 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204293302 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3993456 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2010644 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1806352 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266172688 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133460 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1598637 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 266215456 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2174340 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1590107 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6019387 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7380 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7051 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762361 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6027145 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7088 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1780187 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25560 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 770 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25576 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 767 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5767669 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5624657 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 173600 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263863986 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5769773 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5628686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 175497 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263897928 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33915531 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14406995 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23572 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 166551 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7051 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3148917 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246700 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395617 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207126816 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30634090 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7284075 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33923289 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14424821 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23574 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3848 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 168493 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7088 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3148569 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6396009 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207164807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30640004 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7282448 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20125 # number of nop insts executed -system.cpu.iew.exec_refs 43772682 # number of memory reference insts executed -system.cpu.iew.exec_branches 44853086 # Number of branches executed -system.cpu.iew.exec_stores 13138592 # Number of stores executed -system.cpu.iew.exec_rate 1.203484 # Inst execution rate -system.cpu.iew.wb_sent 206368979 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206058922 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129395738 # num instructions producing a value -system.cpu.iew.wb_consumers 221650226 # num instructions consuming a value -system.cpu.iew.wb_rate 1.197279 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583783 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68671574 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20050 # number of nop insts executed +system.cpu.iew.exec_refs 43787631 # number of memory reference insts executed +system.cpu.iew.exec_branches 44861497 # Number of branches executed +system.cpu.iew.exec_stores 13147627 # Number of stores executed +system.cpu.iew.exec_rate 1.202284 # Inst execution rate +system.cpu.iew.wb_sent 206408899 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206099654 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129383753 # num instructions producing a value +system.cpu.iew.wb_consumers 221651913 # num instructions consuming a value +system.cpu.iew.wb_rate 1.196102 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583725 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68705367 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5760722 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158539716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.145772 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.650496 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5762801 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158729167 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.144404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.650562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73944910 46.64% 46.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41143540 25.95% 72.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22534900 14.21% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9516225 6.00% 92.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3553894 2.24% 95.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2144247 1.35% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1327660 0.84% 97.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1009164 0.64% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3365176 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 74124112 46.70% 46.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41154034 25.93% 72.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22561648 14.21% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9505511 5.99% 92.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552884 2.24% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2129952 1.34% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1300201 0.82% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1012623 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3388202 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158539716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158729167 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -647,7 +655,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction @@ -669,40 +679,42 @@ system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 12498388 6.88% 99.62% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3365176 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 405491255 # The number of ROB reads -system.cpu.rob.rob_writes 511954468 # The number of ROB writes -system.cpu.timesIdled 10012 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2269736 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3388202 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405691473 # The number of ROB reads +system.cpu.rob.rob_writes 512028923 # The number of ROB writes +system.cpu.timesIdled 10004 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2276694 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.998857 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.998857 # CPI: Total CPI of All Threads -system.cpu.ipc 1.001144 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.001144 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218726711 # number of integer regfile reads -system.cpu.int_regfile_writes 114168819 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904003 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441695 # number of floating regfile writes -system.cpu.cc_regfile_reads 708199076 # number of cc regfile reads -system.cpu.cc_regfile_writes 229511616 # number of cc regfile writes -system.cpu.misc_regfile_reads 57440558 # number of misc regfile reads +system.cpu.cpi 1.000037 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.000037 # CPI: Total CPI of All Threads +system.cpu.ipc 0.999963 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.999963 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218765999 # number of integer regfile reads +system.cpu.int_regfile_writes 114196362 # number of integer regfile writes +system.cpu.fp_regfile_reads 2903942 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441736 # number of floating regfile writes +system.cpu.cc_regfile_reads 708332294 # number of cc regfile reads +system.cpu.cc_regfile_writes 229516818 # number of cc regfile writes +system.cpu.misc_regfile_reads 57457287 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72579 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.404028 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41032024 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73091 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.382715 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 516933500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.404028 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998836 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998836 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72598 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.401142 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41046057 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73110 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.428765 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 556160500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.401142 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998830 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998830 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id @@ -710,47 +722,47 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82362375 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82362375 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28645802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28645802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341304 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341304 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82390572 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82390572 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28659846 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28659846 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341293 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341293 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40987106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40987106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40987470 # number of overall hits -system.cpu.dcache.overall_hits::total 40987470 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89259 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89259 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22983 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22983 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 41001139 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41001139 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41001503 # number of overall hits +system.cpu.dcache.overall_hits::total 41001503 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89304 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89304 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22994 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22994 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112242 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112242 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112358 # number of overall misses -system.cpu.dcache.overall_misses::total 112358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1986737500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1986737500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 247540999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 247540999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2234278499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2234278499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2234278499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2234278499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28735061 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28735061 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112298 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112298 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112414 # number of overall misses +system.cpu.dcache.overall_misses::total 112414 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1992894500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1992894500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 247642499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 247642499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2317500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2317500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2240536999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2240536999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2240536999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2240536999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28749150 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28749150 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) @@ -759,14 +771,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41099348 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41099348 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41099828 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41099828 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41113437 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41113437 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41113917 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41113917 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses @@ -775,282 +787,282 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22258.119629 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22258.119629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10770.613018 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10770.613018 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19905.904198 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19905.904198 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19885.353059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19885.353059 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22315.848114 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22315.848114 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10769.874706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10769.874706 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8913.461538 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8913.461538 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19951.708837 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19951.708837 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19931.120670 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19931.120670 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11288 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11146 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 867 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.049711 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72579 # number of writebacks -system.cpu.dcache.writebacks::total 72579 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24837 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24837 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14427 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14427 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 12.855825 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72598 # number of writebacks +system.cpu.dcache.writebacks::total 72598 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24877 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24877 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14424 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14424 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39264 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39264 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39264 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39264 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64422 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64422 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8556 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8556 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 39301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64427 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64427 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8570 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8570 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72978 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72978 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73091 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73091 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87501999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 87501999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 72997 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72997 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73110 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73110 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062486000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062486000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88387499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88387499 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150345499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1150345499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151314499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1151314499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150873499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1150873499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151842499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1151842499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002241 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002241 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16498.145044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16498.145044 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10226.975105 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10226.975105 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16491.315753 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16491.315753 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10313.593816 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10313.593816 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15762.907986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15762.907986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15751.795693 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15751.795693 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53612 # number of replacements -system.cpu.icache.tags.tagsinuse 510.587809 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78268729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54124 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1446.100233 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 85282294500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.587809 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997242 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997242 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.038317 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.038317 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15754.924073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15754.924073 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53656 # number of replacements +system.cpu.icache.tags.tagsinuse 510.578461 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78294727 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1445.405535 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85384212500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.578461 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997224 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997224 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156706996 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156706996 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78268729 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78268729 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78268729 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78268729 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78268729 # number of overall hits -system.cpu.icache.overall_hits::total 78268729 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57707 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57707 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57707 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57707 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57707 # number of overall misses -system.cpu.icache.overall_misses::total 57707 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2245995927 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2245995927 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2245995927 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2245995927 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2245995927 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2245995927 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78326436 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78326436 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78326436 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78326436 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78326436 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78326436 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 156759076 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156759076 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 78294727 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78294727 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78294727 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78294727 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78294727 # number of overall hits +system.cpu.icache.overall_hits::total 78294727 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57727 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57727 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57727 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57727 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57727 # number of overall misses +system.cpu.icache.overall_misses::total 57727 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2248583426 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2248583426 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2248583426 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2248583426 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2248583426 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2248583426 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78352454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78352454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78352454 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78352454 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78352454 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78352454 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000737 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000737 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000737 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000737 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000737 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000737 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38920.684267 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38920.684267 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38920.684267 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38920.684267 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38920.684267 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38920.684267 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93822 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38952.022901 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38952.022901 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38952.022901 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38952.022901 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 93736 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3270 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3241 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.691743 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.921938 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 53612 # number of writebacks -system.cpu.icache.writebacks::total 53612 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3582 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3582 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3582 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3582 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3582 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3582 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54125 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54125 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54125 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54125 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54125 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54125 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2049967950 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2049967950 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2049967950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2049967950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2049967950 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2049967950 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 53656 # number of writebacks +system.cpu.icache.writebacks::total 53656 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3558 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3558 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3558 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3558 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3558 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3558 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54169 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54169 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54169 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54169 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54169 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54169 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2054126952 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2054126952 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2054126952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2054126952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2054126952 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2054126952 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37874.696536 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37874.696536 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37874.696536 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37874.696536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37874.696536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37874.696536 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9207 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9207 # number of prefetch candidates identified +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37920.710222 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37920.710222 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1345 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 1351 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1792.687270 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99060 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2834 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 34.954128 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1796.196657 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99029 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2833 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 34.955524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1727.437863 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 65.249406 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.105434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109417 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 128 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 1727.103732 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.092925 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.105414 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004217 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109631 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 127 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 60 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007812 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 958 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007751 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4003735 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4003735 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 64697 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 64697 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 51019 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 51019 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8384 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8384 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43929 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 43929 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61675 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 61675 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 43929 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 70059 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 113988 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 43929 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 70059 # number of overall hits -system.cpu.l2cache.overall_hits::total 113988 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 239 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 239 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10196 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10196 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2793 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2793 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10196 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3032 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 13228 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10196 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3032 # number of overall misses -system.cpu.l2cache.overall_misses::total 13228 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 20303000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 20303000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1707637000 # 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average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47408.177443 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78403.361345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78403.361345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161478.853891 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161478.853891 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194328.366248 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194328.366248 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166905.970940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161478.853891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185201.620906 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47408.177443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 150809.647109 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253407 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126211 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10475 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 949 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.119965 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 48423.580614 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82655.319149 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82655.319149 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161793.673369 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161793.673369 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194081.658291 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194081.658291 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167192.947942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151223.761281 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253533 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126274 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 943 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 942 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64697 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61494 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2394 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54125 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64468 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380622 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6895104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9322880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16217984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2394 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54169 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64474 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218818 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380811 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6900736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9325312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16226048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2391 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129610 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.088311 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088263 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283705 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118165 91.17% 91.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11444 8.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118226 91.17% 91.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11443 8.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129610 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252894500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129670 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 253020500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81192487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81260982 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109641490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109669990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14321 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10482 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14326 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10488 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 86053034000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14082 # Transaction distribution -system.membus.trans_dist::ReadExReq 238 # Transaction distribution -system.membus.trans_dist::ReadExResp 238 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14083 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28641 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28641 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 916480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14090 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14091 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28651 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14321 # Request fanout histogram +system.membus.snoop_fanout::samples 14326 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14321 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14326 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14321 # Request fanout histogram -system.membus.reqLayer0.occupancy 18093154 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14326 # Request fanout histogram +system.membus.reqLayer0.occupancy 18054137 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77218560 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77252283 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index f0c12dca0..ed017dd04 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103189 # Nu sim_ticks 103189362000 # Number of ticks simulated final_tick 103189362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73255 # Simulator instruction rate (inst/s) -host_op_rate 122783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57235650 # Simulator tick rate (ticks/s) -host_mem_usage 306480 # Number of bytes of host memory used -host_seconds 1802.89 # Real time elapsed on the host +host_inst_rate 113263 # Simulator instruction rate (inst/s) +host_op_rate 189839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88494148 # Simulator tick rate (ticks/s) +host_mem_usage 308956 # Number of bytes of host memory used +host_seconds 1166.06 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -373,37 +373,41 @@ system.cpu.iq.issued_per_cycle::min_value 0 # N system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 206138472 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 759085 19.35% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2731626 69.64% 88.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 432034 11.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 759085 19.25% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2706167 68.61% 87.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 429953 10.90% 98.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 45275 1.15% 99.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3569 0.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1211760 0.36% 0.36% # Type of FU issued @@ -414,7 +418,9 @@ system.cpu.iq.FU_type_0::FloatAdd 1809637 0.53% 67.20% # Ty system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued @@ -436,22 +442,24 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 84315938 24.93% 92.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26623181 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 82580981 24.41% 91.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26493050 7.83% 99.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1734957 0.51% 99.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 130131 0.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 338268196 # Type of FU issued system.cpu.iq.rate 1.639065 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3922745 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011597 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 879521716 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 3944049 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011660 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 879529534 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 744046350 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 315909602 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8181525 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_reads 8195011 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 15431147 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 3556535 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 336873543 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4105638 # Number of floating point alu accesses +system.cpu.iq.int_alu_accesses 336881361 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4119124 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 18155877 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 72027242 # Number of loads squashed @@ -530,7 +538,9 @@ system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction @@ -552,8 +562,10 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 55945136 25.27% 90.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20410230 9.22% 99.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 704451 0.32% 99.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction |