SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

381 files changed, 66146 insertions, 0 deletions

diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
new file mode 100644
index 000000000..6c1c0e974
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
@@ -0,0 +1,240 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
new file mode 100755
index 000000000..30b31a527
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 274500333500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
new file mode 100644
index 000000000..b5662ac02
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -0,0 +1,315 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.274500                       # Number of seconds simulated
+sim_ticks                                274500333500                       # Number of ticks simulated
+final_tick                               274500333500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 113367                       # Simulator instruction rate (inst/s)
+host_tick_rate                               51705325                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207980                       # Number of bytes of host memory used
+host_seconds                                  5308.94                       # Real time elapsed on the host
+sim_insts                                   601856964                       # Number of instructions simulated
+system.physmem.bytes_read                     5894016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  54720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3798080                       # Number of bytes written to this memory
+system.physmem.num_reads                        92094                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59345                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       21471799                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    199344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      13836340                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      35308139                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    114517568                       # DTB read hits
+system.cpu.dtb.read_misses                       2631                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                114520199                       # DTB read accesses
+system.cpu.dtb.write_hits                    39666597                       # DTB write hits
+system.cpu.dtb.write_misses                      2302                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                39668899                       # DTB write accesses
+system.cpu.dtb.data_hits                    154184165                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                154189098                       # DTB accesses
+system.cpu.itb.fetch_hits                    27986226                       # ITB hits
+system.cpu.itb.fetch_misses                        22                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                27986248                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                        549000668                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                     538772486                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                          412059                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59486579                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        489514089                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         89.164571                       # Percentage of cycles cpu is active
+system.cpu.comLoads                         114514042                       # Number of Load instructions committed
+system.cpu.comStores                         39451321                       # Number of Store instructions committed
+system.cpu.comBranches                       62547159                       # Number of Branches instructions committed
+system.cpu.comNops                           36304520                       # Number of Nop instructions committed
+system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                          349039879                       # Number of Integer instructions committed
+system.cpu.comFloats                               24                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                   601856964                       # Number of Instructions Simulated (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total             601856964                       # Number of Instructions Simulated (Total)
+system.cpu.cpi                               0.912178                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         0.912178                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.096277                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         1.096277                       # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups          86959577                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted     82118654                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect     36581334                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups       45689066                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits          35726566                       # Number of BTB hits
+system.cpu.branch_predictor.usedRAS           1197609                       # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct       78.195002                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken     38245021                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken     48714556                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads    540577865                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites    463854846                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses   1004432711                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads          162                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites           42                       # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses          204                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      255585026                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  154582342                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect     35142167                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect      1434180                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted       36576347                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          25971564                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     58.477328                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions        411886396                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies              6482                       # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.stage0.idleCycles                209828742                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                 339171926                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               61.779875                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                238624991                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 310375677                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               56.534663                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                207052073                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 341948595                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               62.285643                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                437467887                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 111532781                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               20.315600                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                201947249                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                 347053419                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               63.215482                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                     30                       # number of replacements
+system.cpu.icache.tagsinuse                728.259897                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 27985205                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    855                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               32731.233918                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            728.259897                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.355596                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               27985205                       # number of ReadReq hits
+system.cpu.icache.demand_hits                27985205                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               27985205                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1019                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1019                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1019                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       56646500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        56646500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       56646500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           27986224                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            27986224                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           27986224                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000036                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000036                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000036                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55590.284593                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55590.284593                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55590.284593                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets        43500                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets        21750                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               164                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                164                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               164                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             855                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              855                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             855                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     45774000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     45774000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     45774000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000031                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000031                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000031                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 451299                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.126386                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                152394244                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 334.641891                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              267624000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.126386                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999543                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              114120509                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              38273735                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               152394244                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              152394244                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               393533                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1177586                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1571119                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1571119                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     8150453500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   25245531000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     33395984500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    33395984500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.003437                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.029849                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.010204                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.010204                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 21256.177603                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 21256.177603                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     12016500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   3424460500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2770                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          216245                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4338.086643                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   408188                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            192301                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           923423                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1115724                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1115724                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          455395                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3562138000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5466740000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   9028878000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   9028878000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001757                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 73797                       # number of replacements
+system.cpu.l2cache.tagsinuse             17695.095192                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  445688                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89683                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.969593                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1638.137841                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16056.957351                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.049992                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.490019                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                170051                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              408188                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              194105                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 364156                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                364156                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32019                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             60075                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                92094                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               92094                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1674917000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3134446000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4809363000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4809363000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            202070                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          408188                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          254180                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             456250                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            456250                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.158455                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.236348                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.201850                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.201850                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52222.327187                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52222.327187                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs      1295000                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              127                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   59345                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          32019                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        60075                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           92094                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          92094                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1281026000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2406899500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   3687925500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   3687925500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.158455                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.236348                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.201850                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.201850                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..cc9b0c683
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..ad1c408b1
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 144450185500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..8681db468
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,517 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.144450                       # Number of seconds simulated
+sim_ticks                                144450185500                       # Number of ticks simulated
+final_tick                               144450185500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 205040                       # Simulator instruction rate (inst/s)
+host_tick_rate                               52370107                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208620                       # Number of bytes of host memory used
+host_seconds                                  2758.26                       # Real time elapsed on the host
+sim_insts                                   565552443                       # Number of instructions simulated
+system.physmem.bytes_read                     5936768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  60416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3797120                       # Number of bytes written to this memory
+system.physmem.num_reads                        92762                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59330                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       41099068                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    418248                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      26286709                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      67385777                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    125584378                       # DTB read hits
+system.cpu.dtb.read_misses                      26780                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                125611158                       # DTB read accesses
+system.cpu.dtb.write_hits                    41433696                       # DTB write hits
+system.cpu.dtb.write_misses                     32002                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                41465698                       # DTB write accesses
+system.cpu.dtb.data_hits                    167018074                       # DTB hits
+system.cpu.dtb.data_misses                      58782                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                167076856                       # DTB accesses
+system.cpu.itb.fetch_hits                    70952399                       # ITB hits
+system.cpu.itb.fetch_misses                        40                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                70952439                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                        288900372                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 81329377                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           74804974                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            4133006                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              77032590                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 69317648                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1953991                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 213                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           73654881                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      736311086                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    81329377                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           71271639                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     138478958                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                16551941                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               64286783                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   31                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           957                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  70952399                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1183706                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          288831482                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.549276                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.199825                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                150352524     52.06%     52.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 11670569      4.04%     56.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 15804098      5.47%     61.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 15798949      5.47%     67.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 13114109      4.54%     71.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 15608541      5.40%     76.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  6620136      2.29%     79.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3484931      1.21%     80.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 56377625     19.52%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            288831482                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.281514                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.548668                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 89767727                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              50572891                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 125759213                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              10322601                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               12409050                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4445174                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   884                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              724769065                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  3300                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               12409050                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 98007088                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12678191                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            619                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 122576240                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              43160294                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              711155131                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   265                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               33840558                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3866582                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           542435988                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             934956599                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        934954553                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2046                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             463854889                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 78581099                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 37                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             37                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  84659517                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            130961315                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            43800509                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          14632120                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         10811841                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  641773186                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  30                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 620620587                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            312645                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        75146534                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     39896926                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     288831482                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.148729                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.863512                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            69246295     23.97%     23.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            56834943     19.68%     43.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            56336980     19.51%     63.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            34937865     12.10%     75.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            31450731     10.89%     86.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            24967668      8.64%     94.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            10438059      3.61%     98.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3923057      1.36%     99.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              695884      0.24%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       288831482                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 3711133     78.36%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     47      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     78.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 592679     12.51%     90.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                432117      9.12%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             450541493     72.60%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7929      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  32      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   6      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   5      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  5      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            127924018     20.61%     93.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            42147099      6.79%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              620620587                       # Type of FU issued
+system.cpu.iq.rate                           2.148217                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4735976                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007631                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1535117897                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         716922572                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    608986825                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                3380                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1870                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         1597                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              625354857                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    1706                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         11780563                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     16447273                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       150139                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         4778                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4349188                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         5903                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         50771                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               12409050                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1537752                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                101062                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           686807741                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2379158                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             130961315                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             43800509                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 30                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  40948                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 13806                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           4778                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4044271                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       603642                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              4647913                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             613128186                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             125611295                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7492401                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                      45034525                       # number of nop insts executed
+system.cpu.iew.exec_refs                    167096489                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 68658345                       # Number of branches executed
+system.cpu.iew.exec_stores                   41485194                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.122282                       # Inst execution rate
+system.cpu.iew.wb_sent                      610318268                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     608988422                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 420036286                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 531421352                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       2.107953                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.790402                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      601856963                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        84796787                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           4132184                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    276422432                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.177309                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.603924                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     90291943     32.66%     32.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     75645741     27.37%     60.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     32420379     11.73%     71.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8741969      3.16%     74.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     10320203      3.73%     78.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     19633028      7.10%     85.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      6964693      2.52%     88.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5325361      1.93%     90.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     27079115      9.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    276422432                       # Number of insts commited each cycle
+system.cpu.commit.count                     601856963                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      153965363                       # Number of memory references committed
+system.cpu.commit.loads                     114514042                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   62547159                       # Number of branches committed
+system.cpu.commit.fp_insts                       1520                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 563954763                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1197610                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              27079115                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    935932678                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1385724156                       # The number of ROB writes
+system.cpu.timesIdled                            2221                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           68890                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   565552443                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             565552443                       # Number of Instructions Simulated
+system.cpu.cpi                               0.510829                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.510829                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.957604                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.957604                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                863490102                       # number of integer regfile reads
+system.cpu.int_regfile_writes               500818441                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       272                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       54                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
+system.cpu.icache.replacements                     36                       # number of replacements
+system.cpu.icache.tagsinuse                801.236568                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 70951127                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    944                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               75160.092161                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            801.236568                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.391229                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               70951127                       # number of ReadReq hits
+system.cpu.icache.demand_hits                70951127                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               70951127                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1272                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1272                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1272                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       45919500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        45919500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       45919500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           70952399                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            70952399                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           70952399                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000018                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000018                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36100.235849                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36100.235849                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36100.235849                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               328                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                328                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               328                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             944                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              944                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             944                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     33676000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     33676000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     33676000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000013                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000013                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000013                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35673.728814                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35673.728814                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35673.728814                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 470690                       # number of replacements
+system.cpu.dcache.tagsinuse               4093.940031                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                151212527                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 474786                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 318.485648                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              126051000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4093.940031                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999497                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              113064898                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              38147626                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits                3                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits               151212524                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              151212524                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               732041                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1303695                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               2035736                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2035736                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    11783533000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   19632740219                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     31416273219                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    31416273219                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          113796939                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           153248260                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          153248260                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.006433                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.033046                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.013284                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.013284                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 16096.821080                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 15059.304683                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 15432.390653                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 15432.390653                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       804496                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       236500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               116                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  6935.310345                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   423044                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            513277                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1047673                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1560950                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1560950                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          218764                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         256022                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           474786                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          474786                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1640072500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3027658494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4667730994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4667730994                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001922                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006490                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.003098                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.003098                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7496.994478                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.774715                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  9831.231321                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  9831.231321                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 74463                       # number of replacements
+system.cpu.l2cache.tagsinuse             17661.712037                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  478021                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 90363                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.290008                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1743.919943                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15917.792095                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.053220                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.485772                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                186750                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              423044                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              196218                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 382968                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                382968                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32958                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             59804                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                92762                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               92762                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1133680000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2065878500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3199558500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3199558500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            219708                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          423044                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          256022                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             475730                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            475730                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.150008                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.233589                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.194989                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.194989                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34492.125008                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34492.125008                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs       370500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               72                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5145.833333                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   59330                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          32958                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        59804                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           92762                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          92762                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1022345000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1877543500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2899888500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2899888500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.150008                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.233589                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.194989                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.194989                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..282141772
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..1dc402141
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 300930958000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..ad4f39b85
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.300931                       # Number of seconds simulated
+sim_ticks                                300930958000                       # Number of ticks simulated
+final_tick                               300930958000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                4527143                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2263589972                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 198960                       # Number of bytes of host memory used
+host_seconds                                   132.94                       # Real time elapsed on the host
+sim_insts                                   601856964                       # Number of instructions simulated
+system.physmem.bytes_read                  2782990928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             2407447588                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                152669504                       # Number of bytes written to this memory
+system.physmem.num_reads                    716375939                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    39451321                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9247938286                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999999747                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     507324022                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9755262308                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    114514042                       # DTB read hits
+system.cpu.dtb.read_misses                       2631                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
+system.cpu.dtb.write_hits                    39451321                       # DTB write hits
+system.cpu.dtb.write_misses                      2302                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                39453623                       # DTB write accesses
+system.cpu.dtb.data_hits                    153965363                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                153970296                       # DTB accesses
+system.cpu.itb.fetch_hits                   601861897                       # ITB hits
+system.cpu.itb.fetch_misses                        20                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               601861917                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                        601861917                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        601856964                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
+system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    563959696                       # number of integer instructions
+system.cpu.num_fp_insts                          1520                       # number of float instructions
+system.cpu.num_int_register_reads           801088993                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          463854847                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     153970296                       # number of memory refs
+system.cpu.num_load_insts                   114516673                       # Number of load instructions
+system.cpu.num_store_insts                   39453623                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  601861917                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..0bc5277c7
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..36bd68fb7
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 765623032000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..4d7850adf
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,266 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.765623                       # Number of seconds simulated
+sim_ticks                                765623032000                       # Number of ticks simulated
+final_tick                               765623032000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2199350                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2797795440                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207676                       # Number of bytes of host memory used
+host_seconds                                   273.65                       # Real time elapsed on the host
+sim_insts                                   601856964                       # Number of instructions simulated
+system.physmem.bytes_read                     5889984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  50880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3797824                       # Number of bytes written to this memory
+system.physmem.num_reads                        92031                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59341                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        7693060                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     66456                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       4960436                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      12653496                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    114514042                       # DTB read hits
+system.cpu.dtb.read_misses                       2631                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
+system.cpu.dtb.write_hits                    39451321                       # DTB write hits
+system.cpu.dtb.write_misses                      2302                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                39453623                       # DTB write accesses
+system.cpu.dtb.data_hits                    153965363                       # DTB hits
+system.cpu.dtb.data_misses                       4933                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                153970296                       # DTB accesses
+system.cpu.itb.fetch_hits                   601861898                       # ITB hits
+system.cpu.itb.fetch_misses                        20                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               601861918                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                       1531246064                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        601856964                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
+system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    563959696                       # number of integer instructions
+system.cpu.num_fp_insts                          1520                       # number of float instructions
+system.cpu.num_int_register_reads           801088993                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          463854847                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     153970296                       # number of memory refs
+system.cpu.num_load_insts                   114516673                       # Number of load instructions
+system.cpu.num_store_insts                   39453623                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1531246064                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     24                       # number of replacements
+system.cpu.icache.tagsinuse                673.337154                       # Cycle average of tags in use
+system.cpu.icache.total_refs                601861103                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    795                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               757057.991195                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            673.337154                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.328778                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              601861103                       # number of ReadReq hits
+system.cpu.icache.demand_hits               601861103                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              601861103                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  795                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   795                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  795                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       44520000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        44520000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       44520000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          601861898                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           601861898                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          601861898                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             795                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              795                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             795                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     42135000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     42135000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     42135000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 451299                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.170317                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                153509968                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 337.091905                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              578392000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.170317                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999553                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              114312810                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              39197158                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               153509968                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              153509968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               201232                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              254163                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                455395                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               455395                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     4126262000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    6081180000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     10207442000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    10207442000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001757                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.006442                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.002958                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002958                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22414.479737                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22414.479737                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   408190                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          455395                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3522566000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5318691000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   8841257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   8841257000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001757                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 73734                       # number of replacements
+system.cpu.l2cache.tagsinuse             17823.514890                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  445709                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89622                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.973210                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1722.436058                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16101.078831                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.052565                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.491366                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                170065                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              408190                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              194094                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 364159                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                364159                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               31962                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             60069                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                92031                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               92031                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1662024000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3123588000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4785612000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4785612000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            202027                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          408190                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          254163                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             456190                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            456190                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.158207                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.236340                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.201738                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.201738                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   59341                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          31962                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        60069                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           92031                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          92031                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1278480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2402760000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   3681240000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   3681240000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.158207                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.236340                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.201738                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.201738                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..9f24d0367
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..d3786fda6
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,41 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:31:06
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 177098873000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..5022d17a1
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,535 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.177099                       # Number of seconds simulated
+sim_ticks                                177098873000                       # Number of ticks simulated
+final_tick                               177098873000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 154897                       # Simulator instruction rate (inst/s)
+host_tick_rate                               45541130                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220436                       # Number of bytes of host memory used
+host_seconds                                  3888.77                       # Real time elapsed on the host
+sim_insts                                   602359805                       # Number of instructions simulated
+system.physmem.bytes_read                     5833856                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  46976                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3720192                       # Number of bytes written to this memory
+system.physmem.num_reads                        91154                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       58128                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       32941237                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    265253                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      21006300                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      53947537                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                        354197747                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 91137531                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           84224367                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            4001637                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              86284566                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 80014553                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1704311                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1605                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           76786839                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      703787736                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    91137531                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           81718864                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     159146597                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                18455506                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              103039518                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   28                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           620                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  74412736                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1337820                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          353350911                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.128080                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.980798                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                194204457     54.96%     54.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25620928      7.25%     62.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 19248235      5.45%     67.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 24404617      6.91%     74.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 11778472      3.33%     77.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 13409998      3.80%     81.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4602257      1.30%     83.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7805373      2.21%     85.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 52276574     14.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            353350911                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.257307                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.986991                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 98877750                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              83515155                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 137076269                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              19506954                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               14374783                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6301291                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  2551                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              740114896                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  7230                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               14374783                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                111843103                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 9537973                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         119731                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 143514381                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              73960940                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              727174418                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   286                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               59845789                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              10289393                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              334                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           752889395                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3380302991                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3380302863                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               128                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             627417394                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                125472001                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              13297                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          13294                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 132095966                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            179744866                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            82855502                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          19180586                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         24795671                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  702443112                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                9504                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 663038146                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            743101                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        99536301                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    237037166                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3158                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     353350911                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.876430                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.733239                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            85428360     24.18%     24.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            90441308     25.60%     49.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            76153703     21.55%     71.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            42544702     12.04%     83.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            25577763      7.24%     90.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            18033700      5.10%     95.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             7283699      2.06%     97.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6627828      1.88%     99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1259848      0.36%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       353350911                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  202982      4.88%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2990868     71.85%     76.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                968637     23.27%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             412586864     62.23%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 6565      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            172485012     26.01%     88.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            77959702     11.76%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              663038146                       # Type of FU issued
+system.cpu.iq.rate                           1.871943                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4162487                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006278                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1684332755                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         802000478                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    650204091                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              667200613                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         29662170                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     30792271                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       224606                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11800                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     12634488                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads        13695                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         12640                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               14374783                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  826341                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 58736                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           702522112                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1853549                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             179744866                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             82855502                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               8175                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  13020                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  5275                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11800                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4156328                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       497844                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              4654172                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             656067860                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             169121282                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6970286                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         69496                       # number of nop insts executed
+system.cpu.iew.exec_refs                    245806937                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 76463124                       # Number of branches executed
+system.cpu.iew.exec_stores                   76685655                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.852264                       # Inst execution rate
+system.cpu.iew.wb_sent                      652210228                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     650204107                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 423315850                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 657380921                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.835709                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.643943                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      602359856                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       100172226                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls            6346                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           4060978                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    338976129                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.776998                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.152747                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    108154848     31.91%     31.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    106518775     31.42%     63.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     49308103     14.55%     77.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9862304      2.91%     80.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     23329668      6.88%     87.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14306268      4.22%     91.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7919036      2.34%     94.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1343281      0.40%     94.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     18233846      5.38%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    338976129                       # Number of insts commited each cycle
+system.cpu.commit.count                     602359856                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      219173609                       # Number of memory references committed
+system.cpu.commit.loads                     148952595                       # Number of loads committed
+system.cpu.commit.membars                        1328                       # Number of memory barriers committed
+system.cpu.commit.branches                   70828602                       # Number of branches committed
+system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 533522643                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               997573                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              18233846                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   1023273753                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1419480895                       # The number of ROB writes
+system.cpu.timesIdled                           37084                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          846836                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   602359805                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             602359805                       # Number of Instructions Simulated
+system.cpu.cpi                               0.588017                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.588017                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.700631                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.700631                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3275893571                       # number of integer regfile reads
+system.cpu.int_regfile_writes               675997918                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               943643021                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                   2658                       # number of misc regfile writes
+system.cpu.icache.replacements                     41                       # number of replacements
+system.cpu.icache.tagsinuse                657.503073                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 74411745                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    766                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               97143.270235                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            657.503073                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.321046                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               74411745                       # number of ReadReq hits
+system.cpu.icache.demand_hits                74411745                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               74411745                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  991                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   991                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  991                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       34848500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        34848500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       34848500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           74412736                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            74412736                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           74412736                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000013                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000013                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000013                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35164.984864                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35164.984864                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35164.984864                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               225                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                225                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               225                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             766                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              766                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             766                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     26233500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     26233500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     26233500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000010                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000010                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34247.389034                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34247.389034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34247.389034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 441233                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.750739                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                205781738                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 445329                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 462.089237                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               87973000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.750739                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999695                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              137926945                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              67852137                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             1328                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              1328                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               205779082                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              205779082                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               249074                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1565394                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses             11                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               1814468                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1814468                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     3282849000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   27038418025                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       203000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     30321267025                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    30321267025                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          138176019                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         1339                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          1328                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           207593550                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          207593550                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001803                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.022550                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.008215                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.008740                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.008740                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 13180.215518                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 17272.595925                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 18454.545455                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 16710.830406                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 16710.830406                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      9583027                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2185                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4385.824714                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   395275                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             51126                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1318013                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits           11                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1369139                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1369139                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          197948                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         247381                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           445329                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          445329                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1625134500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2544872027                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4170006527                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4170006527                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001433                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003564                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002145                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002145                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8209.906137                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10287.257417                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  9363.878227                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  9363.878227                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 72960                       # number of replacements
+system.cpu.l2cache.tagsinuse             17805.724339                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  422235                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 88493                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.771394                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1879.670498                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15926.053841                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.057363                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.486025                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                165899                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              395275                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              189031                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 354930                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                354930                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32812                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             58353                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                91165                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               91165                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1126662000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2003366500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3130028500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3130028500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            198711                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          395275                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          247384                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             446095                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            446095                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.165124                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.235880                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.204362                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.204362                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34336.888943                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.850976                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34333.664235                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34333.664235                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs      2057500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              352                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5845.170455                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   58128                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               11                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                11                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               11                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          32801                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58353                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           91154                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          91154                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1019608000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1822407000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2842015000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2842015000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165069                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235880                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.204338                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.204338                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31084.662053                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31230.733638                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31178.171007                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31178.171007                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..8c7671d34
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..95da0efca
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,41 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:36:54
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 301191370000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..f48dc3640
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.301191                       # Number of seconds simulated
+sim_ticks                                301191370000                       # Number of ticks simulated
+final_tick                               301191370000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2998309                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1499211130                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210136                       # Number of bytes of host memory used
+host_seconds                                   200.90                       # Real time elapsed on the host
+sim_insts                                   602359851                       # Number of instructions simulated
+system.physmem.bytes_read                  2680160157                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             2280298136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                236359611                       # Number of bytes written to this memory
+system.physmem.num_reads                    717867713                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    69418858                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8898529055                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7570927866                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     784748949                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9683278004                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                        602382741                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        602359851                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                     1993546                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     67017827                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    533522639                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_int_register_reads          2770243005                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          614470985                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     219173607                       # number of memory refs
+system.cpu.num_load_insts                   148952594                       # Number of load instructions
+system.cpu.num_store_insts                   70221013                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  602382741                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..6a1e2b970
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..589b03862
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,41 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:40:26
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 796762926000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..3846f97fb
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.796763                       # Number of seconds simulated
+sim_ticks                                796762926000                       # Number of ticks simulated
+final_tick                               796762926000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1450316                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1924652930                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219100                       # Number of bytes of host memory used
+host_seconds                                   413.98                       # Real time elapsed on the host
+sim_insts                                   600398281                       # Number of instructions simulated
+system.physmem.bytes_read                     5759488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  39424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3704704                       # Number of bytes written to this memory
+system.physmem.num_reads                        89992                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       57886                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        7228609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     49480                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       4649694                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      11878304                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                       1593525852                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        600398281                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                     1993546                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     67017827                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    533522639                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_int_register_reads          3212467108                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          614470985                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     219173607                       # number of memory refs
+system.cpu.num_load_insts                   148952594                       # Number of load instructions
+system.cpu.num_store_insts                   70221013                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1593525852                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     12                       # number of replacements
+system.cpu.icache.tagsinuse                577.728532                       # Cycle average of tags in use
+system.cpu.icache.total_refs                570073892                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    643                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               886584.590980                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            577.728532                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.282094                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              570073892                       # number of ReadReq hits
+system.cpu.icache.demand_hits               570073892                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              570073892                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  643                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   643                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  643                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       34874000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        34874000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       34874000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          570074535                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           570074535                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          570074535                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54236.391913                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54236.391913                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54236.391913                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             643                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              643                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             643                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     32945000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     32945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     32945000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 433468                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.222434                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                216774473                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 437564                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 495.412038                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              537031000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.222434                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999566                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              147602036                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              69169783                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             1327                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              1327                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               216771819                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              216771819                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               189816                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              247748                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                437564                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               437564                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     3956274000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    5923414000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency      9879688000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     9879688000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          147791852                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         1327                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          1327                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           217209383                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          217209383                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001284                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.003569                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.002014                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002014                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22578.841038                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22578.841038                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   392392                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          189816                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         247748                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           437564                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          437564                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3386826000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5180170000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   8566996000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   8566996000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001284                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003569                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002014                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002014                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 71804                       # number of replacements
+system.cpu.l2cache.tagsinuse             17904.014680                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  411836                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 87286                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.718237                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1762.179345                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16141.835335                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.053777                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.492610                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                158918                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              392392                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              189297                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 348215                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                348215                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               31541                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             58451                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                89992                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               89992                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1640132000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3039452000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4679584000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4679584000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            190459                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          392392                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          247748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             438207                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            438207                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.165605                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.235929                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.205364                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.205364                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   57886                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          31541                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58451                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           89992                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          89992                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1261640000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2338040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   3599680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   3599680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165605                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235929                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.205364                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.205364                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
new file mode 100644
index 000000000..dcba73ec2
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
new file mode 100755
index 000000000..a835cbd79
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -0,0 +1,41 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:17:40
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 408816360000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..e4d9fca07
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -0,0 +1,491 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.408816                       # Number of seconds simulated
+sim_ticks                                408816360000                       # Number of ticks simulated
+final_tick                               408816360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 175830                       # Simulator instruction rate (inst/s)
+host_tick_rate                               51139829                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215728                       # Number of bytes of host memory used
+host_seconds                                  7994.10                       # Real time elapsed on the host
+sim_insts                                  1405604152                       # Number of instructions simulated
+system.physmem.bytes_read                     6021376                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  81792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3792448                       # Number of bytes written to this memory
+system.physmem.num_reads                        94084                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59257                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       14728804                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    200070                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       9276654                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      24005458                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                   49                       # Number of system calls
+system.cpu.numCycles                        817632721                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                103174324                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           92051331                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            5438120                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             100325127                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 99277633                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                     1230                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 220                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          175005792                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1720391035                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   103174324                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           99278863                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     370286255                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                31094297                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              246539947                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   21                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1680                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 170773896                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                991956                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          817274934                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.110623                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.012258                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                446988679     54.69%     54.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 82419688     10.08%     64.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 45028734      5.51%     70.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 23714407      2.90%     73.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 33177153      4.06%     77.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 33877408      4.15%     81.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 14961867      1.83%     83.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7384305      0.90%     84.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                129722693     15.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            817274934                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.126187                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.104112                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                224321388                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             200349407                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 337624010                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              29538890                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               25441239                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             1710162106                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               25441239                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                255728945                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                34334751                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       55175561                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 334633255                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             111961183                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1694040603                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     8                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               27905496                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              64677715                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents          3154928                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1413596061                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2861791975                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2827818793                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          33973182                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1244770452                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                168825609                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            3228150                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        3270628                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 258968806                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            454536844                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           185491805                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         260927641                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         90896258                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1566773345                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3062819                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1493172729                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            111198                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       163655037                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    180232812                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         819148                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     817274934                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.827014                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.412188                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           168134039     20.57%     20.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           190992211     23.37%     43.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           210117454     25.71%     69.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           154482053     18.90%     88.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            65263213      7.99%     96.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            16377311      2.00%     98.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             7979086      0.98%     99.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3751008      0.46%     99.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              178559      0.02%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       817274934                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  154618      7.33%      7.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                176227      8.36%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     15.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1421289     67.40%     83.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                356622     16.91%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             886609078     59.38%     59.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     59.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     59.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2623677      0.18%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            430399729     28.82%     88.38% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           173540245     11.62%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1493172729                       # Type of FU issued
+system.cpu.iq.rate                           1.826214                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2108756                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001412                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3787980335                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1724526520                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1473498966                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            17860011                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9206634                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      8523998                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1486074999                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 9206486                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        205830187                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     52024000                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       213849                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       253991                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     18643663                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads          681                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         45180                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               25441239                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2526766                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                145081                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1668881823                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           4258646                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             454536844                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            185491805                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2961001                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  59126                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  7519                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         253991                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5294422                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       459505                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              5753927                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1485801812                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             427360543                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7370917                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                      99045659                       # number of nop insts executed
+system.cpu.iew.exec_refs                    599531836                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 90620288                       # Number of branches executed
+system.cpu.iew.exec_stores                  172171293                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.817200                       # Inst execution rate
+system.cpu.iew.wb_sent                     1483493878                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1482022964                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1178273779                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1228157747                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.812578                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.959383                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1489523295                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       179255835                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           5438120                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    791834306                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.881105                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.451655                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    260467018     32.89%     32.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    288028220     36.37%     69.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     45072234      5.69%     74.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     56206737      7.10%     82.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     24021941      3.03%     85.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8787658      1.11%     86.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     30300633      3.83%     90.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10698376      1.35%     91.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     68251489      8.62%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    791834306                       # Number of insts commited each cycle
+system.cpu.commit.count                    1489523295                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      569360986                       # Number of memory references committed
+system.cpu.commit.loads                     402512844                       # Number of loads committed
+system.cpu.commit.membars                       51356                       # Number of memory barriers committed
+system.cpu.commit.branches                   86248929                       # Number of branches committed
+system.cpu.commit.fp_insts                    8452036                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1319476388                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1206914                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              68251489                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   2392297077                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3363039880                       # The number of ROB writes
+system.cpu.timesIdled                           11286                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          357787                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1405604152                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1405604152                       # Number of Instructions Simulated
+system.cpu.cpi                               0.581695                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.581695                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.719114                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.719114                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2016058791                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1303867666                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  16986540                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 10452290                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               605383822                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                2190883                       # number of misc regfile writes
+system.cpu.icache.replacements                    166                       # number of replacements
+system.cpu.icache.tagsinuse               1031.400456                       # Cycle average of tags in use
+system.cpu.icache.total_refs                170772098                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1298                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               131565.560863                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1031.400456                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.503614                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              170772098                       # number of ReadReq hits
+system.cpu.icache.demand_hits               170772098                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              170772098                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1798                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1798                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1798                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       62741500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        62741500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       62741500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          170773896                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           170773896                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          170773896                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000011                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000011                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000011                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 34895.161290                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 34895.161290                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 34895.161290                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               499                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                499                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               499                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            1299                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             1299                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            1299                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     45206000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     45206000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     45206000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000008                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000008                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34800.615858                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34800.615858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34800.615858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 475353                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.165283                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                385593109                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 479449                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 804.242180                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              131001000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.165283                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999796                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              220654856                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             164936934                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
+system.cpu.dcache.demand_hits               385591790                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              385591790                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               815916                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1909882                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
+system.cpu.dcache.demand_misses               2725798                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2725798                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    11966603000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   29861651909                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency         268000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency     41828254909                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    41828254909                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          221470772                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           388317588                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          388317588                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.003684                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.011447                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate           0.007020                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.007020                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14666.464440                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 15635.338680                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 15345.324528                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 15345.324528                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        28000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         3000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2153.846154                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets         3000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   426654                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            603731                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1642625                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            2246356                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           2246356                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          212185                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         267257                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           479442                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          479442                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1589383500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3625603341                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency       247000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   5214986841                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   5214986841                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000958                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001602                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.001235                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001235                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7490.555412                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13565.980839                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 10877.200665                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 10877.200665                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 75859                       # number of replacements
+system.cpu.l2cache.tagsinuse             17814.801426                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  464590                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 91380                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.084154                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2079.678027                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15735.123399                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.063467                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.480198                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                179822                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              426654                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              206842                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 386664                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                386664                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               33662                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             60422                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                94084                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               94084                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1145731000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2079178500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3224909500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3224909500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            213484                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          426654                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          267264                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             480748                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            480748                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.157679                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.226076                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.195703                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.195703                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34036.331769                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.951309                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34276.917435                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34276.917435                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   59257                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          33662                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        60422                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           94084                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          94084                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1043686000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1892150500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2935836500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2935836500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.157679                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.226076                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.195703                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.195703                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871962                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.588693                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.418392                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.418392                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..b52495d06
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
new file mode 100755
index 000000000..d2df5cc09
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -0,0 +1,41 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:18:03
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 744764119000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..afe2bae4f
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.744764                       # Number of seconds simulated
+sim_ticks                                744764119000                       # Number of ticks simulated
+final_tick                               744764119000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3773289                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1886650577                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 205844                       # Number of bytes of host memory used
+host_seconds                                   394.75                       # Real time elapsed on the host
+sim_insts                                  1489523295                       # Number of instructions simulated
+system.physmem.bytes_read                  7326269637                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             5940452044                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                614672063                       # Number of bytes written to this memory
+system.physmem.num_reads                   1887625855                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   166846816                       # Number of write requests responded to by this memory
+system.physmem.num_other                         1326                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9837033566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7976286575                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     825324485                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   10662358051                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                   49                       # Number of system calls
+system.cpu.numCycles                       1489528239                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1489523295                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1319481298                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                8454127                       # Number of float alu accesses
+system.cpu.num_func_calls                     1207835                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     78161763                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1319481298                       # number of integer instructions
+system.cpu.num_fp_insts                       8454127                       # number of float instructions
+system.cpu.num_int_register_reads          2499743582                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1234343158                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             16769332                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            10359244                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     569365767                       # number of memory refs
+system.cpu.num_load_insts                   402515346                       # Number of load instructions
+system.cpu.num_store_insts                  166850421                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1489528239                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
new file mode 100644
index 000000000..ea98a23a1
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
new file mode 100755
index 000000000..b26fb3f41
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -0,0 +1,41 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:19:05
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2064258667000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..059312926
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -0,0 +1,244 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.064259                       # Number of seconds simulated
+sim_ticks                                2064258667000                       # Number of ticks simulated
+final_tick                               2064258667000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1766930                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2448703239                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214556                       # Number of bytes of host memory used
+host_seconds                                   843.00                       # Real time elapsed on the host
+sim_insts                                  1489523295                       # Number of instructions simulated
+system.physmem.bytes_read                     5909952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  70592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3778240                       # Number of bytes written to this memory
+system.physmem.num_reads                        92343                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       59035                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2862990                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     34197                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       1830313                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       4693303                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                   49                       # Number of system calls
+system.cpu.numCycles                       4128517334                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1489523295                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1319481298                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                8454127                       # Number of float alu accesses
+system.cpu.num_func_calls                     1207835                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     78161763                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1319481298                       # number of integer instructions
+system.cpu.num_fp_insts                       8454127                       # number of float instructions
+system.cpu.num_int_register_reads          2499743582                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1234343157                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             16769332                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            10359244                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     569365767                       # number of memory refs
+system.cpu.num_load_insts                   402515346                       # Number of load instructions
+system.cpu.num_store_insts                  166850421                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 4128517334                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                    118                       # number of replacements
+system.cpu.icache.tagsinuse                906.450625                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1485111905                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1107                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               1341564.503162                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            906.450625                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.442603                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits             1485111905                       # number of ReadReq hits
+system.cpu.icache.demand_hits              1485111905                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             1485111905                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1107                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1107                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1107                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       61824000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        61824000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       61824000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         1485113012                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          1485113012                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         1485113012                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55848.238482                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55848.238482                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55848.238482                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            1107                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             1107                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            1107                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     58503000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     58503000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     58503000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 449125                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.226955                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                568907765                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 453221                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                1255.254644                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              566994000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.226955                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999811                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              402319358                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             166587088                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
+system.cpu.dcache.demand_hits               568906446                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              568906446                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               193486                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              259728                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
+system.cpu.dcache.demand_misses                453214                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               453214                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     4019834000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    6156948000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency         392000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency     10176782000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    10176782000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          402512844                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           569359660                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          569359660                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000481                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.001557                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate           0.000796                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000796                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22454.694692                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22454.694692                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   407009                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          193486                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         259728                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           453214                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          453214                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3439376000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5377764000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency       371000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   8817140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   8817140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000481                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001557                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000796                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000796                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 74112                       # number of replacements
+system.cpu.l2cache.tagsinuse             17723.305524                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  427085                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89611                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.765989                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1873.919591                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15849.385934                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.057187                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.483685                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                162275                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              407009                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              199710                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 361985                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                361985                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32318                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             60025                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                92343                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               92343                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1680536000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3121300000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4801836000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4801836000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            194593                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          407009                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          259735                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             454328                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            454328                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.166080                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.231101                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.203252                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.203252                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   59035                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          32318                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        60025                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           92343                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          92343                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1292720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2401000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   3693720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   3693720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.166080                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.231101                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.203252                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.203252                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
new file mode 100644
index 000000000..42f7aa66f
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
new file mode 100755
index 000000000..48ae315a0
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
@@ -0,0 +1,1065 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:28:24
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 586294224000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..802bd6f5d
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -0,0 +1,478 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.586294                       # Number of seconds simulated
+sim_ticks                                586294224000                       # Number of ticks simulated
+final_tick                               586294224000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 145094                       # Simulator instruction rate (inst/s)
+host_tick_rate                               52462700                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215548                       # Number of bytes of host memory used
+host_seconds                                 11175.48                       # Real time elapsed on the host
+sim_insts                                  1621493982                       # Number of instructions simulated
+system.physmem.bytes_read                     5880640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  56960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3744192                       # Number of bytes written to this memory
+system.physmem.num_reads                        91885                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       58503                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       10030186                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     97153                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       6386200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      16416386                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                       1172588449                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                142448982                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          142448982                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            7804844                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             134509888                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                133615988                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          143149229                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1143761054                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   142448982                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          133615988                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     330199440                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                57554993                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              649541012                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   52                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           331                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 137027209                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                996742                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1172439660                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.784546                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.109877                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                845244296     72.09%     72.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 17110181      1.46%     73.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 18043141      1.54%     75.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 16408368      1.40%     76.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 23340182      1.99%     78.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 16629602      1.42%     79.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 21855680      1.86%     81.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 28257046      2.41%     84.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                185551164     15.83%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total           1172439660                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.121483                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.975416                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                240695556                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             558473143                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 228947071                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              94774294                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               49549596                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2070409567                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               49549596                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                290323713                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               132525789                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           3175                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 256725592                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             443311795                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2043122328                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  2634                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              278313629                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             129499394                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2031527322                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4954653611                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4954649391                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              4220                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1617994650                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                413532672                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 91                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             91                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 793190427                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            519090632                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           226808407                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         354951645                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        148937436                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1986583516                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 218                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1781630004                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            180825                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       364939190                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    670712329                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            168                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1172439660                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.519592                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.333662                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           271921709     23.19%     23.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           416937499     35.56%     58.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           234725234     20.02%     78.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           156776493     13.37%     92.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            54385701      4.64%     96.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            21203892      1.81%     98.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            14378982      1.23%     99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1804798      0.15%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              305352      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1172439660                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  179772      6.92%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2269895     87.35%     94.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                148998      5.73%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass          26894248      1.51%      1.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1102052869     61.86%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            457985397     25.71%     89.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           194697490     10.93%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1781630004                       # Type of FU issued
+system.cpu.iq.rate                           1.519399                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2598665                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001459                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4738479063                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2351732069                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1760053765                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  95                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                542                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           12                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1757334381                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      40                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        205665909                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    100048507                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        60622                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       216417                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     38622350                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads          849                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         34395                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               49549596                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1308890                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                133908                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1986583734                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            659432                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             519090632                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            226808407                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 86                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  64911                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    28                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         216417                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4603219                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3388875                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7992094                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1768232808                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             452047218                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          13397196                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                    645919458                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                112169596                       # Number of branches executed
+system.cpu.iew.exec_stores                  193872240                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.507974                       # Inst execution rate
+system.cpu.iew.wb_sent                     1766226829                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1760053777                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1336567337                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2003494286                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.500999                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.667118                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1621493982                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       365103312                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           7804888                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1122890064                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.444036                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.662985                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    346724877     30.88%     30.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    438665808     39.07%     69.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     94902960      8.45%     78.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    133728922     11.91%     90.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     36854784      3.28%     93.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26115374      2.33%     95.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     22565758      2.01%     97.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8207714      0.73%     98.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15123867      1.35%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1122890064                       # Number of insts commited each cycle
+system.cpu.commit.count                    1621493982                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      607228182                       # Number of memory references committed
+system.cpu.commit.loads                     419042125                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                  107161579                       # Number of branches committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              15123867                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   3094363491                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4022764791                       # The number of ROB writes
+system.cpu.timesIdled                           43542                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          148789                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1621493982                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1621493982                       # Number of Instructions Simulated
+system.cpu.cpi                               0.723153                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.723153                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.382833                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.382833                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3273039620                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1756091292                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        12                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               908871445                       # number of misc regfile reads
+system.cpu.icache.replacements                     12                       # number of replacements
+system.cpu.icache.tagsinuse                810.394392                       # Cycle average of tags in use
+system.cpu.icache.total_refs                137025977                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    893                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               153444.543113                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            810.394392                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.395700                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              137025977                       # number of ReadReq hits
+system.cpu.icache.demand_hits               137025977                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              137025977                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1232                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1232                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1232                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       43328500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        43328500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       43328500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          137027209                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           137027209                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          137027209                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35169.237013                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35169.237013                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35169.237013                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               339                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                339                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               339                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             893                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              893                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             893                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     31560500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     31560500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     31560500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000007                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000007                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000007                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35342.105263                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35342.105263                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35342.105263                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 459077                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.907333                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                433034493                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 463173                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 934.930346                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              317767000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.907333                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999733                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              246142702                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             186891791                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               433034493                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              433034493                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               217277                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1294266                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1511543                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1511543                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     2206130500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   25062764496                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     27268894996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    27268894996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          246359979                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           434546036                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          434546036                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000882                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.006878                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.003478                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.003478                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 10153.539031                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 19364.461785                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 18040.436161                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 18040.436161                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      1883000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets    482947000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               482                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           32670                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3906.639004                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 14782.583410                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   410037                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              3648                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1044720                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1048368                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1048368                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          213629                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         249546                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           463175                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          463175                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1533480500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2506697000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4040177500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4040177500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000867                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001326                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.001066                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001066                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7178.241250                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10045.029774                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  8722.788363                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  8722.788363                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 73618                       # number of replacements
+system.cpu.l2cache.tagsinuse             17964.500601                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  452679                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89237                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.072773                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1976.098849                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15988.401752                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.060306                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.487927                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                181359                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              410037                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              190824                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 372183                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                372183                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               33163                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             58722                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                91885                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               91885                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1130840000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2017374000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3148214000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3148214000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            214522                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          410037                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          249546                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             464068                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            464068                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.154590                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.235315                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.197999                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.197999                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34099.448180                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34354.654133                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34262.545573                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34262.545573                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs       202000                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              122                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  1655.737705                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   58503                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          33163                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           91885                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          91885                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1028236500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1828595500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2856832000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2856832000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.154590                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235315                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.197999                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.197999                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.533275                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31139.870917                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31091.385972                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31091.385972                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..393d71365
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
new file mode 100755
index 000000000..3da3c7641
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:33:19
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+info: Increasing stack size by one page.
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 963992704000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..3a54bb2c8
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.963993                       # Number of seconds simulated
+sim_ticks                                963992704000                       # Number of ticks simulated
+final_tick                               963992704000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2202720                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1309536712                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204800                       # Number of bytes of host memory used
+host_seconds                                   736.13                       # Real time elapsed on the host
+sim_insts                                  1621493983                       # Number of instructions simulated
+system.physmem.bytes_read                 11334586825                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             9492133912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                864451000                       # Number of bytes written to this memory
+system.physmem.num_reads                   1605558864                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   188186057                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    11757959140                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                9846686466                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     896740189                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   12654699330                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                       1927985409                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1621493983                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1621354493                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     99478861                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1621354493                       # number of integer instructions
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_int_register_reads          3953866002                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1617994650                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     607228182                       # number of memory refs
+system.cpu.num_load_insts                   419042125                       # Number of load instructions
+system.cpu.num_store_insts                  188186057                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1927985409                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
new file mode 100644
index 000000000..f841786ec
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
new file mode 100755
index 000000000..c3d33da65
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
@@ -0,0 +1,42 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:37:10
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+info: Increasing stack size by one page.
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 1803258587000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..8e512b7b9
--- /dev/null
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -0,0 +1,234 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  1.803259                       # Number of seconds simulated
+sim_ticks                                1803258587000                       # Number of ticks simulated
+final_tick                               1803258587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1279975                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1423455894                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213784                       # Number of bytes of host memory used
+host_seconds                                  1266.82                       # Real time elapsed on the host
+sim_insts                                  1621493983                       # Number of instructions simulated
+system.physmem.bytes_read                     5725952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  46208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3712448                       # Number of bytes written to this memory
+system.physmem.num_reads                        89468                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       58007                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        3175336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     25625                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       2058744                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       5234080                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                       3606517174                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1621493983                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1621354493                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     99478861                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1621354493                       # number of integer instructions
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_int_register_reads          3953866002                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1617994650                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     607228182                       # number of memory refs
+system.cpu.num_load_insts                   419042125                       # Number of load instructions
+system.cpu.num_store_insts                  188186057                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 3606517174                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      4                       # number of replacements
+system.cpu.icache.tagsinuse                660.186297                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1186516018                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               1643373.986150                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            660.186297                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.322357                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits             1186516018                       # number of ReadReq hits
+system.cpu.icache.demand_hits              1186516018                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             1186516018                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  722                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   722                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  722                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       40432000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        40432000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       40432000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         1186516740                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          1186516740                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         1186516740                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             722                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             722                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     38266000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     38266000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     38266000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 437952                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.896939                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                606786134                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 442048                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                1372.670239                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              778540000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.896939                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999731                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              418844799                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             187941335                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               606786134                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              606786134                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               197326                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              244722                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                442048                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               442048                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     4043270000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    5872734000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency      9916004000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     9916004000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          419042125                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           607228182                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          607228182                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000471                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.001300                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000728                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000728                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22431.962140                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22431.962140                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   396372                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          197326                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         244722                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           442048                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          442048                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3451292000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5138568000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   8589860000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   8589860000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000471                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001300                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000728                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000728                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 71208                       # number of replacements
+system.cpu.l2cache.tagsinuse             18056.923092                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  423014                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 86793                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.873826                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1869.199731                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16187.723361                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.057043                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.494010                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                166833                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              396372                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              186469                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 353302                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                353302                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               31215                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             58253                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                89468                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               89468                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1623180000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3029156000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4652336000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4652336000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            198048                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          396372                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          244722                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             442770                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            442770                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.157613                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.238037                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.202064                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.202064                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   58007                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          31215                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58253                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           89468                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          89468                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1248600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2330120000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   3578720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   3578720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.157613                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.238037                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.202064                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.202064                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/test.py b/tests/long/se/00.gzip/test.py
new file mode 100644
index 000000000..7acce6e81
--- /dev/null
+++ b/tests/long/se/00.gzip/test.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import gzip_log
+
+workload = gzip_log(isa, opsys, 'smred')
+root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
new file mode 100644
index 000000000..9ac19076f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
@@ -0,0 +1,4 @@
+P6
+15 15
+255
+


			   !!!   !!!$$$&&&'''&&&%%%


!!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))'''   """%%%&&&'''&&&%%%%%%      !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..bec9490f3
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
@@ -0,0 +1,999 @@
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..db74d3d24
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:43:41
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 33080569000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..190781128
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,536 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.033081                       # Number of seconds simulated
+sim_ticks                                 33080569000                       # Number of ticks simulated
+final_tick                                33080569000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 140676                       # Simulator instruction rate (inst/s)
+host_tick_rate                               50998874                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 353196                       # Number of bytes of host memory used
+host_seconds                                   648.65                       # Real time elapsed on the host
+sim_insts                                    91249885                       # Number of instructions simulated
+system.physmem.bytes_read                      997440                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  44864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
+system.physmem.num_reads                        15585                       # Number of read requests responded to by this memory
+system.physmem.num_writes                          32                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       30151839                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1356204                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                         61909                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      30213749                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                         66161139                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 27503856                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           21975755                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1408867                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              24498145                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 23511296                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                   109835                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               10070                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           15373276                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      131330352                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    27503856                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           23621131                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      32575580                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5466802                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               14146451                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            14                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  14744728                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                369535                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           66131343                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.004854                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.741973                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 33609066     50.82%     50.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  6636464     10.04%     60.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5762437      8.71%     69.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4857984      7.35%     76.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2814891      4.26%     81.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1640731      2.48%     83.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1559267      2.36%     86.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2974436      4.50%     90.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  6276067      9.49%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total             66131343                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.415710                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.985007                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17946396                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              12652276                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  30529024                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                996648                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4006999                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4433202                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 29411                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              129091755                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 32642                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4006999                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 19654600                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1107804                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        8424491                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  29777332                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3160117                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              124853414                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    19                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 254616                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1879605                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents                6                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           145685583                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             543523067                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        543516086                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              6981                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             107429439                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 38256144                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             662187                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         664355                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   7619533                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29336350                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5741000                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1194254                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           692979                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  117270516                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              648807                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 106162042                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             30561                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        26211084                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     62748223                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          93963                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      66131343                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.605321                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.761707                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            24322507     36.78%     36.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14238727     21.53%     58.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             9857796     14.91%     73.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             8080873     12.22%     85.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4216462      6.38%     91.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2267133      3.43%     95.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2478028      3.75%     98.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              463113      0.70%     99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              206704      0.31%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        66131343                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   52363     10.31%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     27      0.01%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 192834     37.95%     48.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                262907     51.74%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              74696384     70.36%     70.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11141      0.01%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt             159      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            260      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26155378     24.64%     95.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5298717      4.99%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              106162042                       # Type of FU issued
+system.cpu.iq.rate                           1.604598                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      508131                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.004786                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          278993219                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         144129610                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    102521129                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 900                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1354                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          412                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              106669721                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     452                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           366276                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      6760478                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        42465                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation          731                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       994251                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         30282                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                4006999                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  182542                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 28701                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           117958129                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            810273                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29336350                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5741000                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             643936                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   9429                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  1050                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents            731                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1288873                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       210071                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1498944                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             104530426                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25743276                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1631616                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         38806                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30946109                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 21214083                       # Number of branches executed
+system.cpu.iew.exec_stores                    5202833                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.579937                       # Inst execution rate
+system.cpu.iew.wb_sent                      102941811                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     102521541                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  60312663                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  96996327                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.549573                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.621804                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       91262494                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        26696986                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          554844                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1392644                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     62124345                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.469029                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.224973                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     28387912     45.70%     45.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16565318     26.66%     72.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      5280655      8.50%     80.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3908699      6.29%     87.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2045216      3.29%     90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       660602      1.06%     91.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       536847      0.86%     92.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       207955      0.33%     92.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4531141      7.29%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     62124345                       # Number of insts commited each cycle
+system.cpu.commit.count                      91262494                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       27322621                       # Number of memory references committed
+system.cpu.commit.loads                      22575872                       # Number of loads committed
+system.cpu.commit.membars                        3888                       # Number of memory barriers committed
+system.cpu.commit.branches                   18722466                       # Number of branches committed
+system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  72533302                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                56148                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               4531141                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    175546950                       # The number of ROB reads
+system.cpu.rob.rob_writes                   239939834                       # The number of ROB writes
+system.cpu.timesIdled                            1543                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           29796                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    91249885                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              91249885                       # Number of Instructions Simulated
+system.cpu.cpi                               0.725054                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.725054                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.379207                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.379207                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                496902731                       # number of integer regfile reads
+system.cpu.int_regfile_writes               120936097                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       197                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      534                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               184886725                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  11594                       # number of misc regfile writes
+system.cpu.icache.replacements                      2                       # number of replacements
+system.cpu.icache.tagsinuse                611.587678                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 14743812                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               20420.792244                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            611.587678                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.298627                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               14743812                       # number of ReadReq hits
+system.cpu.icache.demand_hits                14743812                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               14743812                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  916                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   916                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  916                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       32376000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        32376000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       32376000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           14744728                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            14744728                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           14744728                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000062                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000062                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000062                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35344.978166                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35344.978166                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35344.978166                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               194                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                194                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               194                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             722                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             722                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     24887000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     24887000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     24887000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000049                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000049                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000049                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 943456                       # number of replacements
+system.cpu.dcache.tagsinuse               3558.808717                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 28819274                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 947552                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  30.414451                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            12353041000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3558.808717                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.868850                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               24247443                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               4559242                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             6797                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              5792                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                28806685                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               28806685                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               989267                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              175739                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              7                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               1165006                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1165006                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     5475542500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    4498706928                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       124500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency      9974249428                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     9974249428                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           25236710                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         6804                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          5792                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            29971691                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           29971691                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.039200                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.037115                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.001029                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.038870                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.038870                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency  5534.949109                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 25598.796670                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency  8561.543398                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency  8561.543398                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     23239503                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              8123                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2860.950757                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   942907                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             86240                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           131213                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            7                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             217453                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            217453                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          903027                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          44526                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           947553                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          947553                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   2253075000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1081062556                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   3334137556                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   3334137556                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.035782                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009404                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.031615                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.031615                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2495.025066                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.354894                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3518.681864                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3518.681864                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                   744                       # number of replacements
+system.cpu.l2cache.tagsinuse              9229.669539                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1596774                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15569                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                102.561115                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           392.792284                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8836.877255                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.011987                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.269680                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                901413                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              942907                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               31267                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 932680                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                932680                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                1057                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             14538                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                15595                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               15595                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      36209000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    498763000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      534972000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     534972000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            902470                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          942907                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           45805                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             948275                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            948275                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.001171                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.317389                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.016446                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.016446                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34304.071818                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34304.071818                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                      32                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               10                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           1047                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        14538                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           15585                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          15585                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     32560500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    451777500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    484338000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    484338000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001160                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.317389                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.016435                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.016435                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
new file mode 100644
index 000000000..9ac19076f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
@@ -0,0 +1,4 @@
+P6
+15 15
+255
+


			   !!!   !!!$$$&&&'''&&&%%%


!!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))'''   """%%%&&&'''&&&%%%%%%      !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..67a5d19a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
@@ -0,0 +1,999 @@
+()
+500
+()
+499
+()
+498
+()
+496
+()
+495
+()
+494
+()
+493
+()
+492
+()
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+()
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+()
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+()
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+()
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+()
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+()
+484
+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
+475
+()
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+()
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+()
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+()
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+()
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+()
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+()
+467
+()
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+()
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+()
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+()
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+()
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+()
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+()
+460
+()
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+()
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+()
+457
+()
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+()
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+()
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+()
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+()
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+()
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+()
+448
+()
+446
+()
+445
+()
+444
+()
+443
+()
+442
+()
+440
+()
+439
+()
+438
+()
+436
+()
+435
+()
+433
+()
+432
+()
+431
+()
+428
+()
+427
+()
+425
+()
+424
+()
+423
+()
+420
+()
+419
+()
+416
+()
+414
+()
+413
+()
+412
+()
+407
+()
+406
+()
+405
+()
+404
+()
+403
+()
+402
+()
+401
+()
+400
+()
+399
+()
+398
+()
+396
+()
+395
+()
+393
+()
+392
+()
+390
+()
+389
+()
+388
+()
+387
+()
+386
+()
+385
+()
+384
+()
+383
+()
+382
+()
+381
+()
+380
+()
+379
+()
+377
+()
+375
+()
+374
+()
+373
+()
+372
+()
+371
+()
+370
+()
+369
+()
+368
+()
+366
+()
+365
+()
+364
+()
+362
+()
+361
+()
+360
+()
+359
+()
+358
+()
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+()
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+()
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+()
+354
+()
+352
+()
+350
+()
+347
+()
+344
+()
+342
+()
+341
+()
+340
+()
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+()
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+()
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+()
+9
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+150
+()
+8
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+67
+()
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+()
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+()
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+()
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diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..902784594
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:47:31
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 54240666000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..66ab48bd5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.054241                       # Number of seconds simulated
+sim_ticks                                 54240666000                       # Number of ticks simulated
+final_tick                                54240666000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2777644                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1651027932                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 342980                       # Number of bytes of host memory used
+host_seconds                                    32.85                       # Real time elapsed on the host
+sim_insts                                    91252969                       # Number of instructions simulated
+system.physmem.bytes_read                   521339715                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              431323116                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 18908138                       # Number of bytes written to this memory
+system.physmem.num_reads                    130384074                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     4738868                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9611602391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7952024704                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     348597084                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9960199475                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                        108481333                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         91252969                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
+system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15127614                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     72525682                       # number of integer instructions
+system.cpu.num_fp_insts                            48                       # number of float instructions
+system.cpu.num_int_register_reads           396912516                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      27318811                       # number of memory refs
+system.cpu.num_load_insts                    22573967                       # Number of load instructions
+system.cpu.num_store_insts                    4744844                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  108481333                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
new file mode 100644
index 000000000..9ac19076f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
@@ -0,0 +1,4 @@
+P6
+15 15
+255
+


			   !!!   !!!$$$&&&'''&&&%%%


!!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))'''   """%%%&&&'''&&&%%%%%%      !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW
\ No newline at end of file
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..2f73411a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
@@ -0,0 +1,999 @@
+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+72
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+***
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diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..959967602
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:48:15
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 148086239000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..d6f3be234
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.148086                       # Number of seconds simulated
+sim_ticks                                148086239000                       # Number of ticks simulated
+final_tick                               148086239000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1300672                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2111359212                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 351948                       # Number of bytes of host memory used
+host_seconds                                    70.14                       # Real time elapsed on the host
+sim_insts                                    91226321                       # Number of instructions simulated
+system.physmem.bytes_read                      986112                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  36992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
+system.physmem.num_reads                        15408                       # Number of read requests responded to by this memory
+system.physmem.num_writes                          32                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        6659039                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    249800                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                         13830                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       6672869                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                        296172478                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         91226321                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
+system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15127614                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     72525682                       # number of integer instructions
+system.cpu.num_fp_insts                            48                       # number of float instructions
+system.cpu.num_int_register_reads           464563396                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          106840370                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   54                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  30                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      27318811                       # number of memory refs
+system.cpu.num_load_insts                    22573967                       # Number of load instructions
+system.cpu.num_store_insts                    4744844                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  296172478                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      2                       # number of replacements
+system.cpu.icache.tagsinuse                510.335448                       # Cycle average of tags in use
+system.cpu.icache.total_refs                107830181                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               180016.996661                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            510.335448                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              107830181                       # number of ReadReq hits
+system.cpu.icache.demand_hits               107830181                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              107830181                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  599                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   599                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  599                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       32662000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        32662000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       32662000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          107830780                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           107830780                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          107830780                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54527.545910                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54527.545910                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             599                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              599                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             599                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     30865000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     30865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000006                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000006                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 942702                       # number of replacements
+system.cpu.dcache.tagsinuse               3568.549501                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26345365                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  27.825751                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            54479156000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3568.549501                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               21649219                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               4688372                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             3887                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              3887                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                26337591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               26337591                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               900189                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               46609                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                946798                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               946798                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    13878032000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.039921                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.009844                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.034701                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.034701                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 14657.859438                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 14657.859438                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   942309                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          946798                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.039921                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009844                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.034701                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.034701                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                   634                       # number of replacements
+system.cpu.l2cache.tagsinuse              9235.307693                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1594542                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                103.595504                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           325.097811                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8910.209882                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.009921                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.271918                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                899928                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              942309                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               32061                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 931989                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                931989                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                 860                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             14548                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                15408                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               15408                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      44720000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      801216000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     801216000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            900788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          942309                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             947397                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            947397                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.000955                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.016264                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.016264                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                      32                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses            860                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           15408                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          15408                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     34400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    581920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    616320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    616320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000955                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312129                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.016264                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.016264                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..77055bd16
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
@@ -0,0 +1,999 @@
+()
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diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
new file mode 100755
index 000000000..18a19b6d7
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:20:13
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 122215830000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..e3ffceab4
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.122216                       # Number of seconds simulated
+sim_ticks                                122215830000                       # Number of ticks simulated
+final_tick                               122215830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3409932                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1709135687                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 338176                       # Number of bytes of host memory used
+host_seconds                                    71.51                       # Real time elapsed on the host
+sim_insts                                   243835278                       # Number of instructions simulated
+system.physmem.bytes_read                  1306360053                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              977686044                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 91606089                       # Number of bytes written to this memory
+system.physmem.num_reads                    326641945                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    22901951                       # Number of write requests responded to by this memory
+system.physmem.num_other                         3886                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10688959466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999667834                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     749543566                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11438503032                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  443                       # Number of system calls
+system.cpu.numCycles                        244431661                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        243835278                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
+system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_fp_insts                         11630                       # number of float instructions
+system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451567                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     105711442                       # number of memory refs
+system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_store_insts                   22907920                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  244431661                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
new file mode 100644
index 000000000..acd41b2d5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
@@ -0,0 +1,999 @@
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diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
new file mode 100755
index 000000000..ca44a686d
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:21:35
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 362430887000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..7dc591cfe
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -0,0 +1,244 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.362431                       # Number of seconds simulated
+sim_ticks                                362430887000                       # Number of ticks simulated
+final_tick                               362430887000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1587659                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2359857170                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 346888                       # Number of bytes of host memory used
+host_seconds                                   153.58                       # Real time elapsed on the host
+sim_insts                                   243835278                       # Number of instructions simulated
+system.physmem.bytes_read                     1001472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  56256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     2560                       # Number of bytes written to this memory
+system.physmem.num_reads                        15648                       # Number of read requests responded to by this memory
+system.physmem.num_writes                          40                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2763208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    155219                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                          7063                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       2770272                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  443                       # Number of system calls
+system.cpu.numCycles                        724861774                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        243835278                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
+system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_fp_insts                         11630                       # number of float instructions
+system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451566                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     105711442                       # number of memory refs
+system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_store_insts                   22907920                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  724861774                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     25                       # number of replacements
+system.cpu.icache.tagsinuse                725.567632                       # Cycle average of tags in use
+system.cpu.icache.total_refs                244420630                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               277120.895692                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            725.567632                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.354281                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              244420630                       # number of ReadReq hits
+system.cpu.icache.demand_hits               244420630                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              244420630                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  882                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   882                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  882                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       49266000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        49266000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       49266000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          244421512                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           244421512                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          244421512                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55857.142857                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55857.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55857.142857                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             882                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              882                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             882                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     46620000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     46620000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     46620000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 935475                       # number of replacements
+system.cpu.dcache.tagsinuse               3563.824259                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           134373316000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3563.824259                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.870074                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               81327577                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              22855241                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits                   3882                       # number of SwapReq hits
+system.cpu.dcache.demand_hits               104182818                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              104182818                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               892857                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               46710                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses                    4                       # number of SwapReq misses
+system.cpu.dcache.demand_misses                939567                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               939567                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    12508482000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    1265712000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency          98000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency     13774194000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    13774194000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           82220434                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          22901951                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses               3886                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           105122385                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          105122385                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.010859                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.002040                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate          0.001029                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate           0.008938                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.008938                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency        24500                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 14660.150899                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 14660.150899                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   935237                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          892857                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          46710                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses               4                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           939567                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          939567                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   9829911000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1125582000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency        86000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  10955493000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  10955493000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.010859                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.002040                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.001029                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.008938                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.008938                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        21500                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                   865                       # number of replacements
+system.cpu.l2cache.tagsinuse              9236.752232                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1585884                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15631                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                101.457616                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           375.506440                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8861.245791                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.011460                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.270424                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                892658                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              935237                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               32147                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 924805                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                924805                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                1081                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             14567                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                15648                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               15648                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      56212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    757484000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      813696000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     813696000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            893739                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          935237                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           46714                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             940453                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            940453                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.001210                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.311834                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.016639                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.016639                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                      40                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           1081                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        14567                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           15648                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          15648                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     43240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    582680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    625920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    625920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.311834                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.016639                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.016639                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
new file mode 100644
index 000000000..cfda7ba22
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
@@ -0,0 +1,999 @@
+()
+500
+()
+499
+()
+498
+()
+496
+()
+495
+()
+494
+()
+493
+()
+492
+()
+491
+()
+490
+()
+489
+()
+488
+()
+487
+()
+486
+()
+484
+()
+482
+()
+481
+()
+480
+()
+479
+()
+478
+()
+477
+()
+476
+()
+475
+()
+474
+()
+473
+()
+472
+()
+471
+()
+469
+()
+468
+()
+467
+()
+466
+()
+465
+()
+464
+()
+463
+()
+462
+()
+461
+()
+460
+()
+459
+()
+458
+()
+457
+()
+455
+()
+454
+()
+452
+()
+451
+()
+450
+()
+449
+()
+448
+()
+446
+()
+445
+()
+444
+()
+443
+()
+442
+()
+440
+()
+439
+()
+438
+()
+436
+()
+435
+()
+433
+()
+432
+()
+431
+()
+428
+()
+427
+()
+425
+()
+424
+()
+423
+()
+420
+()
+419
+()
+416
+()
+414
+()
+413
+()
+412
+()
+407
+()
+406
+()
+405
+()
+404
+()
+403
+()
+402
+()
+401
+()
+400
+()
+399
+()
+398
+()
+396
+()
+395
+()
+393
+()
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+()
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diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
new file mode 100755
index 000000000..426afea0c
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:45:46
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 70312944500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..f9c970889
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -0,0 +1,486 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.070313                       # Number of seconds simulated
+sim_ticks                                 70312944500                       # Number of ticks simulated
+final_tick                                70312944500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 168126                       # Simulator instruction rate (inst/s)
+host_tick_rate                               42493747                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 349904                       # Number of bytes of host memory used
+host_seconds                                  1654.67                       # Real time elapsed on the host
+sim_insts                                   278192519                       # Number of instructions simulated
+system.physmem.bytes_read                     4896576                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  65344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  1867840                       # Number of bytes written to this memory
+system.physmem.num_reads                        76509                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       29185                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       69639752                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    929331                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      26564668                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      96204419                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
+system.cpu.numCycles                        140625890                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 37833804                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           37833804                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1322933                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              33591925                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 33081589                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           29087381                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      203627812                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37833804                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33081589                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      63297987                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                10276298                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               38195582                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   21                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            95                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  28266291                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                204981                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          139497150                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.574262                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.291399                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 78673130     56.40%     56.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3606277      2.59%     58.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2810090      2.01%     61.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4532102      3.25%     64.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  6824412      4.89%     69.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5279008      3.78%     72.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  7637539      5.48%     78.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4315201      3.09%     81.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 25819391     18.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            139497150                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.269039                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.448011                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 41917744                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              28560060                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  52643719                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7459543                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                8916084                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              354657218                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                8916084                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 48823983                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4469241                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           6888                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  53004642                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              24276312                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              350176569                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 101342                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              20289844                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           314446851                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             861231533                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        861227904                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              3629                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 66102659                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                479                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            472                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  56104077                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            112666461                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37647255                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          48253520                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8188094                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  343455788                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2295                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 316242386                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             89834                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        65098177                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     92870721                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1849                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     139497150                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.267017                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.750973                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            31795649     22.79%     22.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            18418675     13.20%     36.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25717845     18.44%     54.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            29872112     21.41%     75.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            18507796     13.27%     89.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            10200782      7.31%     96.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3199934      2.29%     98.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1737869      1.25%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               46488      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       139497150                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   25785      1.36%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1795857     94.47%     95.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                 79349      4.17%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass             16711      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             180262574     57.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 195      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            101451147     32.08%     89.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34511759     10.91%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              316242386                       # Type of FU issued
+system.cpu.iq.rate                           2.248821                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1900991                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006011                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          773971833                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         408587092                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    312537049                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 914                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               2332                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          382                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              318126211                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     455                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         45906656                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     21887073                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       122159                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        33758                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6207504                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         2763                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         15488                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                8916084                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  901068                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 88602                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           343458083                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             26305                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             112666461                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37647255                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1597                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 48733                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          33758                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1219939                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       230098                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1450037                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             314144155                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             100864248                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2098231                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                    134973322                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31810521                       # Number of branches executed
+system.cpu.iew.exec_stores                   34109074                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.233900                       # Inst execution rate
+system.cpu.iew.wb_sent                      313190495                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     312537431                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 232392592                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 318468890                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       2.222474                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.729718                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        65270328                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1322946                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    130581066                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.130420                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.663472                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     50414718     38.61%     38.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     24339651     18.64%     57.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     16499074     12.64%     69.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12376450      9.48%     79.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3696747      2.83%     82.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3466084      2.65%     84.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2761727      2.11%     86.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1175320      0.90%     87.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15851295     12.14%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    130581066                       # Number of insts commited each cycle
+system.cpu.commit.count                     278192519                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      122219139                       # Number of memory references committed
+system.cpu.commit.loads                      90779388                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   29309710                       # Number of branches committed
+system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              15851295                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    458192618                       # The number of ROB reads
+system.cpu.rob.rob_writes                   695856607                       # The number of ROB writes
+system.cpu.timesIdled                           33615                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1128740                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   278192519                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             278192519                       # Number of Instructions Simulated
+system.cpu.cpi                               0.505498                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.505498                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.978245                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.978245                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                554794614                       # number of integer regfile reads
+system.cpu.int_regfile_writes               279836675                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       437                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      335                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               201195947                       # number of misc regfile reads
+system.cpu.icache.replacements                     68                       # number of replacements
+system.cpu.icache.tagsinuse                824.679926                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 28264985                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1027                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               27521.893866                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            824.679926                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.402676                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               28264985                       # number of ReadReq hits
+system.cpu.icache.demand_hits                28264985                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               28264985                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1306                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1306                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1306                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       47073500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        47073500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       47073500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           28266291                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            28266291                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           28266291                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000046                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000046                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000046                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36044.027565                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36044.027565                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36044.027565                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               278                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                278                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               278                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            1028                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             1028                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            1028                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     36154500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     36154500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     36154500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000036                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000036                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000036                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35169.747082                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35169.747082                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35169.747082                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2073066                       # number of replacements
+system.cpu.dcache.tagsinuse               4076.005888                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 83808707                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2077162                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  40.347699                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            23845092000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4076.005888                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995119                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               52611944                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              31196754                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                83808698                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               83808698                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              2262875                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              242997                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               2505872                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2505872                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    14629803500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    4394648436                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     19024451936                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    19024451936                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           54874819                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            86314570                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           86314570                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.041237                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.007729                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.029032                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.029032                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency  6465.139922                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 18085.196262                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency  7591.948805                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency  7591.948805                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       289000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                92                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3141.304348                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  1447147                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            291175                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           137531                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             428706                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            428706                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1971700                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         105466                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2077166                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2077166                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   5609142000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1870309936                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   7479451936                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   7479451936                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.035931                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003355                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.024065                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.024065                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2844.825278                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17733.771414                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3600.796439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3600.796439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 49057                       # number of replacements
+system.cpu.l2cache.tagsinuse             18859.305089                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3318010                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 77063                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 43.055811                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          6747.919367                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         12111.385721                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.205930                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.369610                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1938157                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1447147                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               63526                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                2001683                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               2001683                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               34474                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses             42035                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                76509                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               76509                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1179443000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   1438838000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     2618281000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    2618281000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1972631                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1447147                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          105561                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2078192                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2078192                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.017476                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.398206                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.036815                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.036815                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34212.536984                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.523017                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34221.869323                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34221.869323                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs        37500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               14                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  2678.571429                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   29185                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          34474                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        42035                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           76509                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          76509                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1069429500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1307209000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2376638500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2376638500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017476                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.398206                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.036815                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.036815                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.334919                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.108719                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.515403                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.515403                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..96706c5cc
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
@@ -0,0 +1,999 @@
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+***
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+()
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+205
+()
+1
+***
+39
+***
+95
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
new file mode 100755
index 000000000..eb189c10a
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:52:52
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 168950072000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..e99e16cd0
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.168950                       # Number of seconds simulated
+sim_ticks                                168950072000                       # Number of ticks simulated
+final_tick                               168950072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2042288                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1240309006                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 339312                       # Number of bytes of host memory used
+host_seconds                                   136.22                       # Real time elapsed on the host
+sim_insts                                   278192520                       # Number of instructions simulated
+system.physmem.bytes_read                  2458815679                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             1741569664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                243173115                       # Number of bytes written to this memory
+system.physmem.num_reads                    308475658                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    31439751                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    14553504772                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read               10308191310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1439319393                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   15992824164                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
+system.cpu.numCycles                        337900145                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        278192520                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    278186228                       # number of integer instructions
+system.cpu.num_fp_insts                            40                       # number of float instructions
+system.cpu.num_int_register_reads           685043114                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          248344166                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     122219139                       # number of memory refs
+system.cpu.num_load_insts                    90779388                       # Number of load instructions
+system.cpu.num_store_insts                   31439751                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  337900145                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
new file mode 100644
index 000000000..008adeebb
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
@@ -0,0 +1,999 @@
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+***
+95
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
new file mode 100755
index 000000000..e89b51a20
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:55:19
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+MCF SPEC version 1.6.I
+by  Andreas Loebel
+Copyright (c) 1998,1999   ZIB Berlin
+All Rights Reserved.
+
+nodes                      : 500
+active arcs                : 1905
+simplex iterations         : 1502
+flow value                 : 4990014995
+new implicit arcs          : 23867
+active arcs                : 25772
+simplex iterations         : 2663
+flow value                 : 3080014995
+checksum                   : 68389
+optimal
+Exiting @ tick 370010840000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..59ae818d2
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -0,0 +1,234 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.370011                       # Number of seconds simulated
+sim_ticks                                370010840000                       # Number of ticks simulated
+final_tick                               370010840000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1163147                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1547047043                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 348152                       # Number of bytes of host memory used
+host_seconds                                   239.17                       # Real time elapsed on the host
+sim_insts                                   278192520                       # Number of instructions simulated
+system.physmem.bytes_read                     4900800                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  51712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  1885440                       # Number of bytes written to this memory
+system.physmem.num_reads                        76575                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       29460                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       13245017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    139758                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5095634                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      18340652                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
+system.cpu.numCycles                        740021680                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        278192520                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    278186228                       # number of integer instructions
+system.cpu.num_fp_insts                            40                       # number of float instructions
+system.cpu.num_int_register_reads           685043114                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          248344166                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     122219139                       # number of memory refs
+system.cpu.num_load_insts                    90779388                       # Number of load instructions
+system.cpu.num_store_insts                   31439751                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  740021680                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     24                       # number of replacements
+system.cpu.icache.tagsinuse                666.191948                       # Cycle average of tags in use
+system.cpu.icache.total_refs                217695401                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               269425.001238                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            666.191948                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.325289                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              217695401                       # number of ReadReq hits
+system.cpu.icache.demand_hits               217695401                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              217695401                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  808                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   808                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  808                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       45248000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        45248000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       45248000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          217696209                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           217696209                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          217696209                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             808                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             808                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     42824000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     42824000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     42824000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2062733                       # number of replacements
+system.cpu.dcache.tagsinuse               4076.661903                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                120152372                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2066829                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  58.133678                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           126200130000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4076.661903                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               88818730                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              31333642                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               120152372                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              120152372                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1960720                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              106109                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               2066829                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2066829                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    28849058000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    3268793000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     32117851000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    32117851000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           90779450                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           122219201                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          122219201                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.021599                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.003375                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.016911                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.016911                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 15539.675029                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 15539.675029                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  1437080                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1960720                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         106109                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2066829                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2066829                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  22966898000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2950464500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  25917362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  25917362500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.021599                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003375                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.016911                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.016911                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 49212                       # number of replacements
+system.cpu.l2cache.tagsinuse             18614.603260                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3296079                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 77127                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 42.735735                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          6551.798271                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         12062.804989                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.199945                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.368128                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1927411                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1437080                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               63651                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                1991062                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               1991062                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               34117                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             42458                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                76575                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               76575                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1774084000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2207845500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3981929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3981929500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1961528                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1437080                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          106109                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2067637                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2067637                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.017393                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.400136                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.037035                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.037035                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000.385243                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000.385243                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   29460                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          34117                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        42458                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           76575                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          76575                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1364680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1698320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   3063000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   3063000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017393                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.400136                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.037035                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.037035                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/test.py b/tests/long/se/10.mcf/test.py
new file mode 100644
index 000000000..9bd18a83f
--- /dev/null
+++ b/tests/long/se/10.mcf/test.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import mcf
+
+workload = mcf(isa, opsys, 'smred')
+root.system.cpu.workload = workload.makeLiveProcess()
+root.system.physmem.range=AddrRange('256MB')
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/NOTE b/tests/long/se/20.parser/ref/alpha/tru64/NOTE
new file mode 100644
index 000000000..5e7d8c358
--- /dev/null
+++ b/tests/long/se/20.parser/ref/alpha/tru64/NOTE
@@ -0,0 +1,6 @@
+I removed the reference outputs for this program because it's taking
+way too long... over an hour for simple-atomic and over 19 hrs for
+o3-timing.  We need to find a shorter input if we want to keep this
+in the regressions.
+
+Steve
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..e2c071016
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=parser 2.1.dict -batch
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+gid=100
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=114600000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..c61c0591a
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,70 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:49:36
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+ Reading the dictionary files: *************************************************
+
+
+Welcome to the Link Parser -- Version 2.1
+
+          Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+info: Increasing stack size by one page.
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success 
+* do you know where John 's 
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+info: Increasing stack size by one page.
+* how fast the program is it 
+* I am wondering whether to invite to the party 
+* I gave him for his birthday it 
+* I thought terrible after our discussion 
+* I wonder how much money have you earned 
+* Janet who is an expert on dogs helped me choose one 
+* she interviewed more programmers than was hired 
+* such flowers are found chiefly particularly in Europe 
+* the dogs some of which were very large ran after the man 
+* the man whom I play tennis is here 
+* there is going to be an important meeting January 
+* to pretend that our program is usable in its current form would be happy 
+* we're thinking about going to a movie this theater 
+* which dog you said you chased 
+- also invited to the meeting were several prominent scientists 
+- he ran home so quickly that his mother could hardly believe he had called from school 
+- so many people attended that they spilled over into several neighboring fields 
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats 
+: Grace may not be possible to fix the problem 
+  any program as good as ours should be useful 
+  biochemically , I think the experiment has a lot of problems 
+  Fred has had five years of experience as a programmer 
+  he is looking for another job 
+  how did John do it 
+  how many more people do you think will come 
+  how much more spilled 
+  I have more money than John has time 
+  I made it clear that I was angry 
+  I wonder how John did it 
+  I wonder how much more quickly he ran 
+  invite John and whoever else you want to invite 
+  it is easier to ignore the problem than it is to solve it 
+  many who initially supported Thomas later changed their minds 
+  neither Mary nor Louise are coming to the party 
+  she interviewed more programmers than were hired 
+  telling Joe that Sue was coming to the party would create a real problem 
+  the man with whom I play tennis is here 
+  there is a dog in the park 
+  this is not the man we know and love 
+  we like to eat at restaurants , usually on weekends 
+  what did John say he thought you should do 
+  about 2 million people attended 
+  the five best costumes got prizes 
+No errors!
+Exiting @ tick 274198757500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..0cc2b2b8d
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,545 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.274199                       # Number of seconds simulated
+sim_ticks                                274198757500                       # Number of ticks simulated
+final_tick                               274198757500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 114096                       # Simulator instruction rate (inst/s)
+host_tick_rate                               54566255                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225172                       # Number of bytes of host memory used
+host_seconds                                  5025.06                       # Real time elapsed on the host
+sim_insts                                   573341162                       # Number of instructions simulated
+system.physmem.bytes_read                    15248640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 230400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 10960192                       # Number of bytes written to this memory
+system.physmem.num_reads                       238260                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      171253                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       55611631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    840266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      39971706                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      95583336                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.numCycles                        548397516                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                225101784                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          179007547                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           18307036                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             189868979                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                156087931                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 11743928                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect             2589266                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          154237973                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      996342059                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225101784                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          167831859                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     251951083                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                70115496                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               88916227                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   76                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         27190                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 141601056                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               4591339                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          544609039                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.120756                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.818747                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                292670234     53.74%     53.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 22602609      4.15%     57.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 39324759      7.22%     65.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 38673680      7.10%     72.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 44132407      8.10%     80.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 15219761      2.79%     83.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 18468380      3.39%     86.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 13866800      2.55%     89.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 59650409     10.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            544609039                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.410472                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.816825                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                173360184                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              84631968                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 232819510                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4407510                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               49389867                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33096702                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 88546                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1070717063                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                220828                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               49389867                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                189439670                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 6246457                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       67211324                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 221002512                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              11319209                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              984442373                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1013                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2966416                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               5236155                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               73                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1176369692                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4273292331                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4273289228                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              3103                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             672199296                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                504170396                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            6164964                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        6164681                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  63358237                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            196378247                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            77986326                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          17967729                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         12612066                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  870602735                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             7830625                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 735457773                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1536942                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       302215535                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    751654986                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        3952431                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     544609039                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.350433                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.595771                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           241479375     44.34%     44.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            95418106     17.52%     61.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            86231703     15.83%     77.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            59231990     10.88%     88.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            36938301      6.78%     95.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            14710122      2.70%     98.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             6373652      1.17%     99.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3471755      0.64%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              754035      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       544609039                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  133367      1.38%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                6658147     68.82%     70.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2883419     29.80%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             497367446     67.63%     67.63% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               380524      0.05%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 142      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            170820646     23.23%     90.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            66889012      9.09%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              735457773                       # Type of FU issued
+system.cpu.iq.rate                           1.341103                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     9674933                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013155                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2026736140                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1180706061                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    693772826                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 320                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                454                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              745132544                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     162                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          8466293                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     69605317                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        50613                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        61790                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     20382475                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads        28472                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           334                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               49389867                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2700739                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                121924                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           887765924                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          12225511                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             196378247                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             77986326                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            6083275                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  46564                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  7422                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          61790                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       18530018                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5460534                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             23990552                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             711163338                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             161856987                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          24294435                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                       9332564                       # number of nop insts executed
+system.cpu.iew.exec_refs                    226770071                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                147519559                       # Number of branches executed
+system.cpu.iew.exec_stores                   64913084                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.296803                       # Inst execution rate
+system.cpu.iew.wb_sent                      699318417                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     693772842                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 395045304                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 663504976                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.265091                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.595392                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      574685046                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       313100037                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         3878194                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          20503761                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    495219173                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.160466                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.863525                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    259975062     52.50%     52.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    116222276     23.47%     75.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     44533135      8.99%     84.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     21295357      4.30%     89.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     19840150      4.01%     93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7283820      1.47%     94.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7518006      1.52%     96.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3788243      0.76%     97.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     14763124      2.98%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    495219173                       # Number of insts commited each cycle
+system.cpu.commit.count                     574685046                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      184376781                       # Number of memory references committed
+system.cpu.commit.loads                     126772930                       # Number of loads committed
+system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
+system.cpu.commit.branches                  120192115                       # Number of branches committed
+system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 473701197                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              14763124                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   1368233994                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1825140894                       # The number of ROB writes
+system.cpu.timesIdled                           96084                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         3788477                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   573341162                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             573341162                       # Number of Instructions Simulated
+system.cpu.cpi                               0.956494                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.956494                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.045485                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.045485                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3291621496                       # number of integer regfile reads
+system.cpu.int_regfile_writes               815258640                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
+system.cpu.misc_regfile_reads              1231509968                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                4463832                       # number of misc regfile writes
+system.cpu.icache.replacements                  12844                       # number of replacements
+system.cpu.icache.tagsinuse               1060.855578                       # Cycle average of tags in use
+system.cpu.icache.total_refs                141584558                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  14688                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                9639.471541                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1060.855578                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.517996                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              141584561                       # number of ReadReq hits
+system.cpu.icache.demand_hits               141584561                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              141584561                       # number of overall hits
+system.cpu.icache.ReadReq_misses                16495                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 16495                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                16495                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      235861500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       235861500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      235861500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          141601056                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           141601056                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          141601056                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000116                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000116                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000116                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 14298.969385                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 14298.969385                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 14298.969385                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        1                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1651                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1651                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1651                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           14844                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            14844                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           14844                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    154845500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    154845500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    154845500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000105                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000105                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000105                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 10431.521153                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 10431.521153                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 10431.521153                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1212341                       # number of replacements
+system.cpu.dcache.tagsinuse               4058.230538                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                204314278                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1216437                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 167.961249                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             5623770000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4058.230538                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.990779                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              146820758                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              52766592                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits          2494784                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits           2231915                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               199587350                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              199587350                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1243424                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1472714                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses             59                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               2716138                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2716138                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    14347379500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   25015184497                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       557000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     39362563997                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    39362563997                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          148064182                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses      2494843                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses       2231915                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           202303488                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          202303488                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.008398                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.027152                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000024                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.013426                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.013426                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 11538.605898                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 16985.772185                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency  9440.677966                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 14492.107543                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 14492.107543                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       502000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              64                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets  7843.750000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  1079461                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            367349                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1132203                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits           59                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1499552                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1499552                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          876075                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         340511                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1216586                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1216586                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   6316165000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   4359865500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  10676030500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  10676030500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.005917                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006278                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.006014                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.006014                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7209.616757                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12803.890330                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  8775.401410                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  8775.401410                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                219133                       # number of replacements
+system.cpu.l2cache.tagsinuse             21061.116186                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1567440                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                239478                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.545236                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          204357736000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          7517.812526                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13543.303660                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.229425                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.413309                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                760340                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1079462                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits                116                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits              232507                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 992847                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                992847                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              130056                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses               33                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            108226                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               238282                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              238282                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    4448635000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency        68000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3706374500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     8155009500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    8155009500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            890396                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1079462                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses            149                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          340733                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1231129                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1231129                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.146065                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.221477                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.317627                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.193548                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.193548                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency  2060.606061                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34224.194442                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34224.194442                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                  171253                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               19                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                19                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               19                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses         130037                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses           33                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       108226                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          238263                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         238263                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4037689500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency      1023000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   3355622000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   7393311500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   7393311500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.146044                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.221477                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.317627                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.193532                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.193532                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..cbe7d05b4
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=parser 2.1.dict -batch
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+gid=100
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=114600000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..e26a927e8
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,70 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:54:41
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+ Reading the dictionary files: *************************************************
+
+
+Welcome to the Link Parser -- Version 2.1
+
+          Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+info: Increasing stack size by one page.
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success 
+* do you know where John 's 
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+info: Increasing stack size by one page.
+* how fast the program is it 
+* I am wondering whether to invite to the party 
+* I gave him for his birthday it 
+* I thought terrible after our discussion 
+* I wonder how much money have you earned 
+* Janet who is an expert on dogs helped me choose one 
+* she interviewed more programmers than was hired 
+* such flowers are found chiefly particularly in Europe 
+* the dogs some of which were very large ran after the man 
+* the man whom I play tennis is here 
+* there is going to be an important meeting January 
+* to pretend that our program is usable in its current form would be happy 
+* we're thinking about going to a movie this theater 
+* which dog you said you chased 
+- also invited to the meeting were several prominent scientists 
+- he ran home so quickly that his mother could hardly believe he had called from school 
+- so many people attended that they spilled over into several neighboring fields 
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats 
+: Grace may not be possible to fix the problem 
+  any program as good as ours should be useful 
+  biochemically , I think the experiment has a lot of problems 
+  Fred has had five years of experience as a programmer 
+  he is looking for another job 
+  how did John do it 
+  how many more people do you think will come 
+  how much more spilled 
+  I have more money than John has time 
+  I made it clear that I was angry 
+  I wonder how John did it 
+  I wonder how much more quickly he ran 
+  invite John and whoever else you want to invite 
+  it is easier to ignore the problem than it is to solve it 
+  many who initially supported Thomas later changed their minds 
+  neither Mary nor Louise are coming to the party 
+  she interviewed more programmers than were hired 
+  telling Joe that Sue was coming to the party would create a real problem 
+  the man with whom I play tennis is here 
+  there is a dog in the park 
+  this is not the man we know and love 
+  we like to eat at restaurants , usually on weekends 
+  what did John say he thought you should do 
+  about 2 million people attended 
+  the five best costumes got prizes 
+No errors!
+Exiting @ tick 290498972000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..12a51d6fd
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.290499                       # Number of seconds simulated
+sim_ticks                                290498972000                       # Number of ticks simulated
+final_tick                               290498972000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3123764                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1589318228                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213568                       # Number of bytes of host memory used
+host_seconds                                   182.78                       # Real time elapsed on the host
+sim_insts                                   570968176                       # Number of instructions simulated
+system.physmem.bytes_read                  2489298238                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             2066445536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                216067624                       # Number of bytes written to this memory
+system.physmem.num_reads                    641840242                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    55727847                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8569043191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7113434935                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     743781028                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9312824219                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.numCycles                        580997945                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        570968176                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     95872736                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    470727703                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_int_register_reads          2465023721                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          646169365                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     182890035                       # number of memory refs
+system.cpu.num_load_insts                   126029556                       # Number of load instructions
+system.cpu.num_store_insts                   56860479                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  580997945                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..5a2d86232
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=parser 2.1.dict -batch
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+gid=100
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=114600000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..8c1353073
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,70 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:54:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+ Reading the dictionary files: *************************************************
+
+
+Welcome to the Link Parser -- Version 2.1
+
+          Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+info: Increasing stack size by one page.
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success 
+* do you know where John 's 
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+info: Increasing stack size by one page.
+* how fast the program is it 
+* I am wondering whether to invite to the party 
+* I gave him for his birthday it 
+* I thought terrible after our discussion 
+* I wonder how much money have you earned 
+* Janet who is an expert on dogs helped me choose one 
+* she interviewed more programmers than was hired 
+* such flowers are found chiefly particularly in Europe 
+* the dogs some of which were very large ran after the man 
+* the man whom I play tennis is here 
+* there is going to be an important meeting January 
+* to pretend that our program is usable in its current form would be happy 
+* we're thinking about going to a movie this theater 
+* which dog you said you chased 
+- also invited to the meeting were several prominent scientists 
+- he ran home so quickly that his mother could hardly believe he had called from school 
+- so many people attended that they spilled over into several neighboring fields 
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats 
+: Grace may not be possible to fix the problem 
+  any program as good as ours should be useful 
+  biochemically , I think the experiment has a lot of problems 
+  Fred has had five years of experience as a programmer 
+  he is looking for another job 
+  how did John do it 
+  how many more people do you think will come 
+  how much more spilled 
+  I have more money than John has time 
+  I made it clear that I was angry 
+  I wonder how John did it 
+  I wonder how much more quickly he ran 
+  invite John and whoever else you want to invite 
+  it is easier to ignore the problem than it is to solve it 
+  many who initially supported Thomas later changed their minds 
+  neither Mary nor Louise are coming to the party 
+  she interviewed more programmers than were hired 
+  telling Joe that Sue was coming to the party would create a real problem 
+  the man with whom I play tennis is here 
+  there is a dog in the park 
+  this is not the man we know and love 
+  we like to eat at restaurants , usually on weekends 
+  what did John say he thought you should do 
+  about 2 million people attended 
+  the five best costumes got prizes 
+No errors!
+Exiting @ tick 722234364000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..f9d747bd5
--- /dev/null
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.722234                       # Number of seconds simulated
+sim_ticks                                722234364000                       # Number of ticks simulated
+final_tick                               722234364000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1518630                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1927485562                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222536                       # Number of bytes of host memory used
+host_seconds                                   374.70                       # Real time elapsed on the host
+sim_insts                                   569034848                       # Number of instructions simulated
+system.physmem.bytes_read                    14797056                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 188608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 11027328                       # Number of bytes written to this memory
+system.physmem.num_reads                       231204                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      172302                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       20487887                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    261145                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      15268351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      35756238                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.numCycles                       1444468728                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        569034848                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     95872736                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    470727703                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_int_register_reads          2844375220                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          646169365                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     182890035                       # number of memory refs
+system.cpu.num_load_insts                   126029556                       # Number of load instructions
+system.cpu.num_store_insts                   56860479                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1444468728                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   9788                       # number of replacements
+system.cpu.icache.tagsinuse                984.426148                       # Cycle average of tags in use
+system.cpu.icache.total_refs                516599864                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               44839.845847                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            984.426148                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.480677                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              516599864                       # number of ReadReq hits
+system.cpu.icache.demand_hits               516599864                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              516599864                       # number of overall hits
+system.cpu.icache.ReadReq_misses                11521                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 11521                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                11521                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      285068000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       285068000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      285068000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          516611385                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           516611385                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          516611385                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000022                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000022                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000022                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 24743.338252                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 24743.338252                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 24743.338252                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           11521                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            11521                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           11521                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    250505000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    250505000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    250505000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000022                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000022                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000022                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1134822                       # number of replacements
+system.cpu.dcache.tagsinuse               4065.490059                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                179817787                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1138918                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 157.884753                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            11889987000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4065.490059                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.992551                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              122957659                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              53883046                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits          1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits           1488541                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               176840705                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              176840705                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               782658                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              356260                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1138918                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1138918                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    15502704000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   10028942000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     25531646000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    25531646000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          123740317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses       1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           177979623                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          177979623                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.006325                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.006568                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.006399                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.006399                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22417.457622                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22417.457622                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  1025440                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          782658                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         356260                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1138918                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1138918                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  13154730000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   8960162000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  22114892000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  22114892000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.006325                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006568                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.006399                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.006399                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                212089                       # number of replacements
+system.cpu.l2cache.tagsinuse             20443.163614                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1426644                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                232128                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.145937                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          513135223000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          5849.157602                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14594.006011                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.178502                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.445374                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                683006                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1025440                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              236229                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 919235                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                919235                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              111173                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            120031                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               231204                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              231204                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    5780996000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   6241612000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    12022608000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   12022608000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            794179                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1025440                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          356260                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1150439                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1150439                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.139985                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.336920                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.200970                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.200970                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                  172302                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses         111173                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       120031                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          231204                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         231204                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4446920000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4801240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   9248160000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   9248160000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.139985                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.336920                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.200970                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.200970                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
new file mode 100644
index 000000000..9cc27361f
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
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+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
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+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
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+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
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+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
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+
+[system.cpu.fuPool.FUList5.opList03]
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+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
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+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
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+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
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+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=parser 2.1.dict -batch
+cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+gid=100
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=114600000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
new file mode 100755
index 000000000..de72d963a
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -0,0 +1,82 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:58:28
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+ Reading the dictionary files: ***********************info: Increasing stack size by one page.
+**************************
+ 58924 words stored in 3784810 bytes
+
+
+Welcome to the Link Parser -- Version 2.1
+
+          Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success 
+info: Increasing stack size by one page.
+* do you know where John 's 
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+info: Increasing stack size by one page.
+* how fast the program is it 
+* I am wondering whether to invite to the party 
+* I gave him for his birthday it 
+* I thought terrible after our discussion 
+* I wonder how much money have you earned 
+* Janet who is an expert on dogs helped me choose one 
+* she interviewed more programmers than was hired 
+* such flowers are found chiefly particularly in Europe 
+* the dogs some of which were very large ran after the man 
+* the man whom I play tennis is here 
+* there is going to be an important meeting January 
+* to pretend that our program is usable in its current form would be happy 
+* we're thinking about going to a movie this theater 
+* which dog you said you chased 
+- also invited to the meeting were several prominent scientists 
+- he ran home so quickly that his mother could hardly believe he had called from school 
+- so many people attended that they spilled over into several neighboring fields 
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats 
+: Grace may not be possible to fix the problem 
+  any program as good as ours should be useful 
+  biochemically , I think the experiment has a lot of problems 
+  Fred has had five years of experience as a programmer 
+  he is looking for another job 
+  how did John do it 
+  how many more people do you think will come 
+  how much more spilled 
+  I have more money than John has time 
+  I made it clear that I was angry 
+  I wonder how John did it 
+  I wonder how much more quickly he ran 
+  invite John and whoever else you want to invite 
+  it is easier to ignore the problem than it is to solve it 
+  many who initially supported Thomas later changed their minds 
+  neither Mary nor Louise are coming to the party 
+  she interviewed more programmers than were hired 
+  telling Joe that Sue was coming to the party would create a real problem 
+  the man with whom I play tennis is here 
+  there is a dog in the park 
+  this is not the man we know and love 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+  we like to eat at restaurants , usually on weekends 
+  what did John say he thought you should do 
+  about 2 million people attended 
+  the five best costumes got prizes 
+No errors!
+Exiting @ tick 493912286000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..92ece0bed
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -0,0 +1,491 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.493912                       # Number of seconds simulated
+sim_ticks                                493912286000                       # Number of ticks simulated
+final_tick                               493912286000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 145271                       # Simulator instruction rate (inst/s)
+host_tick_rate                               46927205                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251468                       # Number of bytes of host memory used
+host_seconds                                 10525.07                       # Real time elapsed on the host
+sim_insts                                  1528988756                       # Number of instructions simulated
+system.physmem.bytes_read                    37487424                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 347584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 26320960                       # Number of bytes written to this memory
+system.physmem.num_reads                       585741                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      411265                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       75898950                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    703736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      53290758                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     129189708                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  551                       # Number of system calls
+system.cpu.numCycles                        987824573                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                245766486                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          245766486                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           16576996                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             236474058                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                218464201                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          205503020                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1343384866                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   245766486                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          218464201                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     436676837                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               119986236                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              218554807                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                32387                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        341323                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 194710374                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               4099618                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          964252463                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.599701                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.317490                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                531629837     55.13%     55.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 32377332      3.36%     58.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 38827894      4.03%     62.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 32536894      3.37%     65.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 21844251      2.27%     68.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 36448993      3.78%     71.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 49128972      5.10%     77.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 36937786      3.83%     80.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                184520504     19.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            964252463                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.248796                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.359943                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                264509435                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             174554141                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 373011587                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              49033211                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              103144089                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2445932072                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              103144089                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                301738657                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                40282868                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          12225                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 383467875                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             135606749                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2393375507                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  2559                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               25131978                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              92224846                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents                8                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2227188673                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5629907069                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       5629667957                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            239112                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                799889646                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1309                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1288                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 318947403                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            577879232                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           226530900                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         227222440                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         65937432                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2286709085                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               12489                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1922370305                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1306641                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       755226802                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1190125426                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          11936                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     964252463                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.993638                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.811521                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           282911384     29.34%     29.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           160280603     16.62%     45.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           162550496     16.86%     62.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           148847741     15.44%     78.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           109081156     11.31%     89.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            60080329      6.23%     95.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            30822605      3.20%     99.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             8641604      0.90%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1036545      0.11%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       964252463                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2246339     14.60%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               10026447     65.19%     79.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3108042     20.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass           2420122      0.13%      0.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1274712167     66.31%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            463703127     24.12%     90.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           181534884      9.44%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1922370305                       # Type of FU issued
+system.cpu.iq.rate                           1.946064                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    15380828                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008001                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4825675637                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3042139517                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1874661917                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                4905                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              81824                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          136                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1935329448                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    1563                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        158391521                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    193777072                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       372742                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       283642                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     77371112                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         2379                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles              103144089                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 9045659                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1404502                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2286721574                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1118432                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             577879232                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            226531297                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6081                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1006586                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 29974                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         283642                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15693422                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2344063                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18037485                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1889150749                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             454748002                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          33219556                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                    629271939                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                176719729                       # Number of branches executed
+system.cpu.iew.exec_stores                  174523937                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.912435                       # Inst execution rate
+system.cpu.iew.wb_sent                     1882531239                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1874662053                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1440606287                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2134778201                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.897768                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.674827                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1528988756                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       757743569                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          16604349                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    861108374                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.775605                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.288022                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    338327816     39.29%     39.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    210551706     24.45%     63.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     75360819      8.75%     72.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     92562974     10.75%     83.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     34054041      3.95%     87.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27955182      3.25%     90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     16032820      1.86%     92.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     12266632      1.42%     93.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     53996384      6.27%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    861108374                       # Number of insts commited each cycle
+system.cpu.commit.count                    1528988756                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      533262345                       # Number of memory references committed
+system.cpu.commit.loads                     384102160                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                  149758588                       # Number of branches committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              53996384                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   3093844315                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4676786954                       # The number of ROB writes
+system.cpu.timesIdled                          606516                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        23572110                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1528988756                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1528988756                       # Number of Instructions Simulated
+system.cpu.cpi                               0.646064                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.646064                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.547834                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.547834                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3179044858                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1744829680                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       145                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        5                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1039286160                       # number of misc regfile reads
+system.cpu.icache.replacements                  10045                       # number of replacements
+system.cpu.icache.tagsinuse                976.337758                       # Cycle average of tags in use
+system.cpu.icache.total_refs                194480398                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  11548                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               16841.045895                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            976.337758                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.476727                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              194486608                       # number of ReadReq hits
+system.cpu.icache.demand_hits               194486608                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              194486608                       # number of overall hits
+system.cpu.icache.ReadReq_misses               223766                       # number of ReadReq misses
+system.cpu.icache.demand_misses                223766                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses               223766                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     1539723000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      1539723000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     1539723000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          194710374                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           194710374                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          194710374                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.001149                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.001149                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.001149                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  6880.951530                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  6880.951530                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  6880.951530                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        6                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              2071                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               2071                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              2071                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          221695                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           221695                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          221695                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    824417000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    824417000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    824417000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.001139                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.001139                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.001139                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  3718.699114                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  3718.699114                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  3718.699114                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2527930                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.566272                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                440586260                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2532026                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 174.005425                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             2135798000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4087.566272                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997941                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              291836002                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             147579227                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               439415229                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              439415229                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              3119681                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1580974                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               4700655                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              4700655                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    52079313500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   37355392500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     89434706000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    89434706000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          294955683                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           444115884                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          444115884                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.010577                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.010599                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.010584                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.010584                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 16693.794494                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23628.087812                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 19026.009354                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 19026.009354                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        14500                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  2229595                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           1359154                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           607660                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1966814                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1966814                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1760527                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         973314                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2733841                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2733841                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  14908482500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  17169522000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  32078004500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  32078004500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.005969                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006525                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.006156                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.006156                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8468.193047                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17640.270252                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11733.675989                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11733.675989                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                574945                       # number of replacements
+system.cpu.l2cache.tagsinuse             21597.257673                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3194359                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                594122                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.376604                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          271429089000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          7797.131828                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13800.125845                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.237950                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.421146                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1433279                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             2229601                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits               1240                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits              524400                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                1957679                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               1957679                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              338611                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses           208876                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            247152                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               585763                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              585763                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   11564612500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency      9756500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   8478074500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    20042687000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   20042687000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1771890                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         2229601                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses         210116                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          771552                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2543442                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2543442                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.191102                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.994098                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.320331                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.230303                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.230303                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34153.091601                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency    46.709531                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34303.078672                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34216.375906                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34216.375906                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                  411265                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses         338611                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses       208876                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       247152                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          585763                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         585763                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  10503665500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency   6475353000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   7666739500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  18170405000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  18170405000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191102                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994098                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.320331                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.230303                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.230303                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.859071                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.943143                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.341733                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31020.062722                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31020.062722                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..b1057156b
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=parser 2.1.dict -batch
+cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+gid=100
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=114600000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
new file mode 100755
index 000000000..b86175ab2
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
@@ -0,0 +1,72 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:59:28
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+ Reading the dictionary files: *****************************info: Increasing stack size by one page.
+********************
+ 58924 words stored in 3784810 bytes
+
+
+Welcome to the Link Parser -- Version 2.1
+
+          Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success 
+* do you know where John 's 
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+* how fast the program is it 
+* I am wondering whether to invite to the party 
+* I gave him for his birthday it 
+* I thought terrible after our discussion 
+* I wonder how much money have you earned 
+* Janet who is an expert on dogs helped me choose one 
+* she interviewed more programmers than was hired 
+* such flowers are found chiefly particularly in Europe 
+* the dogs some of which were very large ran after the man 
+* the man whom I play tennis is here 
+* there is going to be an important meeting January 
+* to pretend that our program is usable in its current form would be happy 
+* we're thinking about going to a movie this theater 
+* which dog you said you chased 
+- also invited to the meeting were several prominent scientists 
+- he ran home so quickly that his mother could hardly believe he had called from school 
+- so many people attended that they spilled over into several neighboring fields 
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats 
+: Grace may not be possible to fix the problem 
+  any program as good as ours should be useful 
+  biochemically , I think the experiment has a lot of problems 
+  Fred has had five years of experience as a programmer 
+  he is looking for another job 
+  how did John do it 
+  how many more people do you think will come 
+  how much more spilled 
+  I have more money than John has time 
+  I made it clear that I was angry 
+  I wonder how John did it 
+  I wonder how much more quickly he ran 
+  invite John and whoever else you want to invite 
+  it is easier to ignore the problem than it is to solve it 
+  many who initially supported Thomas later changed their minds 
+  neither Mary nor Louise are coming to the party 
+  she interviewed more programmers than were hired 
+  telling Joe that Sue was coming to the party would create a real problem 
+  the man with whom I play tennis is here 
+  there is a dog in the park 
+  this is not the man we know and love 
+  we like to eat at restaurants , usually on weekends 
+  what did John say he thought you should do 
+  about 2 million people attended 
+  the five best costumes got prizes 
+No errors!
+Exiting @ tick 885229360000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..4e0a10e13
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.885229                       # Number of seconds simulated
+sim_ticks                                885229360000                       # Number of ticks simulated
+final_tick                               885229360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2258239                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1307438877                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208528                       # Number of bytes of host memory used
+host_seconds                                   677.07                       # Real time elapsed on the host
+sim_insts                                  1528988757                       # Number of instructions simulated
+system.physmem.bytes_read                 10832432532                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             8546776872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                991849460                       # Number of bytes written to this memory
+system.physmem.num_reads                   1452449298                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   149160201                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    12236865406                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                9654872803                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1120443475                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13357308881                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  551                       # Number of system calls
+system.cpu.numCycles                       1770458721                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1528988757                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1528317615                       # number of integer instructions
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_int_register_reads          3581460239                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1427299027                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     533262345                       # number of memory refs
+system.cpu.num_load_insts                   384102160                       # Number of load instructions
+system.cpu.num_store_insts                  149160185                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1770458721                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
new file mode 100644
index 000000000..c570a48d2
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=parser 2.1.dict -batch
+cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+gid=100
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=114600000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
new file mode 100755
index 000000000..a297c4bc8
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -0,0 +1,72 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:10:56
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+ Reading the dictionary files: *****************************info: Increasing stack size by one page.
+********************
+ 58924 words stored in 3784810 bytes
+
+
+Welcome to the Link Parser -- Version 2.1
+
+          Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success 
+* do you know where John 's 
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+* how fast the program is it 
+* I am wondering whether to invite to the party 
+* I gave him for his birthday it 
+* I thought terrible after our discussion 
+* I wonder how much money have you earned 
+* Janet who is an expert on dogs helped me choose one 
+* she interviewed more programmers than was hired 
+* such flowers are found chiefly particularly in Europe 
+* the dogs some of which were very large ran after the man 
+* the man whom I play tennis is here 
+* there is going to be an important meeting January 
+* to pretend that our program is usable in its current form would be happy 
+* we're thinking about going to a movie this theater 
+* which dog you said you chased 
+- also invited to the meeting were several prominent scientists 
+- he ran home so quickly that his mother could hardly believe he had called from school 
+- so many people attended that they spilled over into several neighboring fields 
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats 
+: Grace may not be possible to fix the problem 
+  any program as good as ours should be useful 
+  biochemically , I think the experiment has a lot of problems 
+  Fred has had five years of experience as a programmer 
+  he is looking for another job 
+  how did John do it 
+  how many more people do you think will come 
+  how much more spilled 
+  I have more money than John has time 
+  I made it clear that I was angry 
+  I wonder how John did it 
+  I wonder how much more quickly he ran 
+  invite John and whoever else you want to invite 
+  it is easier to ignore the problem than it is to solve it 
+  many who initially supported Thomas later changed their minds 
+  neither Mary nor Louise are coming to the party 
+  she interviewed more programmers than were hired 
+  telling Joe that Sue was coming to the party would create a real problem 
+  the man with whom I play tennis is here 
+  there is a dog in the park 
+  this is not the man we know and love 
+  we like to eat at restaurants , usually on weekends 
+  what did John say he thought you should do 
+  about 2 million people attended 
+  the five best costumes got prizes 
+No errors!
+Exiting @ tick 1658729604000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..28d09902a
--- /dev/null
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -0,0 +1,234 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  1.658730                       # Number of seconds simulated
+sim_ticks                                1658729604000                       # Number of ticks simulated
+final_tick                               1658729604000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1326745                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1439324936                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217512                       # Number of bytes of host memory used
+host_seconds                                  1152.44                       # Real time elapsed on the host
+sim_insts                                  1528988757                       # Number of instructions simulated
+system.physmem.bytes_read                    37094976                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 148544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 26349376                       # Number of bytes written to this memory
+system.physmem.num_reads                       579609                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      411709                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       22363486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     89553                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      15885275                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      38248761                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  551                       # Number of system calls
+system.cpu.numCycles                       3317459208                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1528988757                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1528317615                       # number of integer instructions
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_int_register_reads          3581460239                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1427299027                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     533262345                       # number of memory refs
+system.cpu.num_load_insts                   384102160                       # Number of load instructions
+system.cpu.num_store_insts                  149160185                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 3317459208                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   1253                       # number of replacements
+system.cpu.icache.tagsinuse                882.231489                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1068344296                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               379653.267946                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            882.231489                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.430777                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits             1068344296                       # number of ReadReq hits
+system.cpu.icache.demand_hits              1068344296                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             1068344296                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 2814                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  2814                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 2814                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      136878000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       136878000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      136878000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         1068347110                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          1068347110                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         1068347110                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 48641.791045                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 48641.791045                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 48641.791045                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            2814                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             2814                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            2814                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    128436000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    128436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    128436000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2514362                       # number of replacements
+system.cpu.dcache.tagsinuse               4086.472055                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                530743932                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 210.741625                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             8216675000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4086.472055                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997674                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              382374775                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             148369157                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               530743932                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              530743932                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1727414                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              791044                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               2518458                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2518458                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    38012508000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   21492013500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     59504521500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    59504521500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          384102189                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           533262390                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          533262390                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.004497                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.005303                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.004723                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.004723                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 23627.363053                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 23627.363053                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  2223170                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1727414                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         791044                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2518458                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2518458                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  32830264000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  19118876000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  51949140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  51949140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.004497                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005303                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.004723                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.004723                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                568906                       # number of replacements
+system.cpu.l2cache.tagsinuse             21228.193311                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3146531                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                587958                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.351625                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          896565143000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          7549.128601                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13679.064710                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.230381                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.417452                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1398652                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             2223170                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              543011                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                1941663                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               1941663                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              331576                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            248033                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               579609                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              579609                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   17241952000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  12897722000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    30139674000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   30139674000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1730228                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         2223170                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          791044                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2521272                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2521272                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.191637                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.313551                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.229888                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.229888                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000.010352                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000.010352                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                  411709                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses         331576                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       248033                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          579609                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         579609                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  13263040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   9921320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  23184360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  23184360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191637                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.313551                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.229888                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.229888                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/test.py b/tests/long/se/20.parser/test.py
new file mode 100644
index 000000000..c96a46e60
--- /dev/null
+++ b/tests/long/se/20.parser/test.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import parser
+
+workload = parser(isa, opsys, 'mdred')
+root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
new file mode 100644
index 000000000..16e4d1756
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -0,0 +1,240 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
new file mode 100755
index 000000000..860580eeb
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
@@ -0,0 +1,52 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0  8  14
+1  8  14
+2  8  14
+3  8  14
+4  8  14
+5  8  14
+6  8  14
+7  8  14
+8  8  14
+9  8  14
+10  8  14
+11  8  14
+12  8  14
+13  8  14
+14  8  14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
new file mode 100755
index 000000000..1c2a18294
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.133333
+Exiting @ tick 139995113500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
new file mode 100644
index 000000000..a04efd18a
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -0,0 +1,314 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.139995                       # Number of seconds simulated
+sim_ticks                                139995113500                       # Number of ticks simulated
+final_tick                               139995113500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 118986                       # Simulator instruction rate (inst/s)
+host_tick_rate                               41783300                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214012                       # Number of bytes of host memory used
+host_seconds                                  3350.50                       # Real time elapsed on the host
+sim_insts                                   398664595                       # Number of instructions simulated
+system.physmem.bytes_read                      469184                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 214784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         7331                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        3351431                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1534225                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       3351431                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     94755013                       # DTB read hits
+system.cpu.dtb.read_misses                         21                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 94755034                       # DTB read accesses
+system.cpu.dtb.write_hits                    73522045                       # DTB write hits
+system.cpu.dtb.write_misses                        35                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                73522080                       # DTB write accesses
+system.cpu.dtb.data_hits                    168277058                       # DTB hits
+system.cpu.dtb.data_misses                         56                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                168277114                       # DTB accesses
+system.cpu.itb.fetch_hits                    48859849                       # ITB hits
+system.cpu.itb.fetch_misses                     44521                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                48904370                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
+system.cpu.numCycles                        279990228                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                     279561038                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                            6809                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        13513618                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        266476610                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         95.173539                       # Percentage of cycles cpu is active
+system.cpu.comLoads                          94754489                       # Number of Load instructions committed
+system.cpu.comStores                         73520729                       # Number of Store instructions committed
+system.cpu.comBranches                       44587532                       # Number of Branches instructions committed
+system.cpu.comNops                           23089775                       # Number of Nop instructions committed
+system.cpu.comNonSpec                             215                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                          112239074                       # Number of Integer instructions committed
+system.cpu.comFloats                         50439198                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                   398664595                       # Number of Instructions Simulated (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total             398664595                       # Number of Instructions Simulated (Total)
+system.cpu.cpi                               0.702320                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         0.702320                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.423852                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         1.423852                       # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups          53456377                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted     30648707                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect     15206922                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups       35068414                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits          15659516                       # Number of BTB hits
+system.cpu.branch_predictor.usedRAS           8007516                       # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect           20                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct       44.654189                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken     29689183                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken     23767194                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads    280275252                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites    159335859                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses    439611111                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads    119572386                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites    100196481                       # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses    219768867                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      100597400                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  168369236                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect     14604498                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect       601765                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted       15206263                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          29381288                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     34.104279                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions        205417549                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies           2124324                       # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.stage0.idleCycles                 78021134                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                 201969094                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               72.134337                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                107567321                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 172422907                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               61.581759                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                102759298                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 177230930                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               63.298970                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                181219893                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  98770335                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               35.276351                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 90498113                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                 189492115                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               67.678117                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                   1970                       # number of replacements
+system.cpu.icache.tagsinuse               1829.847469                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 48855472                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3897                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               12536.687708                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1829.847469                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.893480                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               48855472                       # number of ReadReq hits
+system.cpu.icache.demand_hits                48855472                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               48855472                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 4376                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  4376                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 4376                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      214318500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       214318500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      214318500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           48859848                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            48859848                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           48859848                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000090                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000090                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000090                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 48975.891225                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 48975.891225                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 48975.891225                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets        45000                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets        45000                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               479                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                479                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               479                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3897                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3897                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3897                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    185285000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    185285000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    185285000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000080                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000080                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000080                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                    764                       # number of replacements
+system.cpu.dcache.tagsinuse               3284.892021                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                168261959                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               40525.519990                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3284.892021                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.801976                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               94753265                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              73508694                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               168261959                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              168261959                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1224                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               12035                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                 13259                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                13259                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       63830500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     626731500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       690562000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      690562000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           94754489                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          73520729                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           168275218                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          168275218                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000013                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000164                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000079                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000079                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 52082.509993                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 52082.509993                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets     82468500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            1848                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      649                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits               274                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             8833                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               9107                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              9107                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4152                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     46185000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    169537500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    215722500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    215722500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                    13                       # number of replacements
+system.cpu.l2cache.tagsinuse              3900.004949                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     729                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4720                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.154449                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3529.472340                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           370.532609                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.107711                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011308                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                   658                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 649                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  60                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                    718                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                   718                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4186                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              3145                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 7331                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                7331                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     219209500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    164966000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      384175500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     384175500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              4844                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses             649                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            3205                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               8049                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              8049                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.864162                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.981279                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.910796                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.910796                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52404.242259                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52404.242259                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           4186                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         3145                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            7331                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           7331                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    168226500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    126764000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    294990500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    294990500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.864162                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.981279                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.910796                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.910796                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..0fce2844b
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..860580eeb
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,52 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0  8  14
+1  8  14
+2  8  14
+3  8  14
+4  8  14
+5  8  14
+6  8  14
+7  8  14
+8  8  14
+9  8  14
+10  8  14
+11  8  14
+12  8  14
+13  8  14
+14  8  14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..137fd0ee8
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.083333
+Exiting @ tick 89480174500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..28785f469
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,516 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.089480                       # Number of seconds simulated
+sim_ticks                                 89480174500                       # Number of ticks simulated
+final_tick                                89480174500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 190161                       # Simulator instruction rate (inst/s)
+host_tick_rate                               45305657                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214676                       # Number of bytes of host memory used
+host_seconds                                  1975.03                       # Real time elapsed on the host
+sim_insts                                   375574794                       # Number of instructions simulated
+system.physmem.bytes_read                      475840                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 219968                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         7435                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        5317826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   2458288                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       5317826                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    105444914                       # DTB read hits
+system.cpu.dtb.read_misses                      94699                       # DTB read misses
+system.cpu.dtb.read_acv                         48617                       # DTB read access violations
+system.cpu.dtb.read_accesses                105539613                       # DTB read accesses
+system.cpu.dtb.write_hits                    79763652                       # DTB write hits
+system.cpu.dtb.write_misses                      1536                       # DTB write misses
+system.cpu.dtb.write_acv                            1                       # DTB write access violations
+system.cpu.dtb.write_accesses                79765188                       # DTB write accesses
+system.cpu.dtb.data_hits                    185208566                       # DTB hits
+system.cpu.dtb.data_misses                      96235                       # DTB misses
+system.cpu.dtb.data_acv                         48618                       # DTB access violations
+system.cpu.dtb.data_accesses                185304801                       # DTB accesses
+system.cpu.itb.fetch_hits                    57904086                       # ITB hits
+system.cpu.itb.fetch_misses                       346                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                57904432                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
+system.cpu.numCycles                        178960351                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 56765606                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           33143039                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3552012                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              40427205                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 32022628                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 10686505                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1330                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           59866357                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      502938652                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    56765606                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42709133                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      93526616                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                12701088                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               16326839                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  180                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          7643                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  57904086                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1110763                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          178838548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.812250                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.245901                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 85311932     47.70%     47.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8035871      4.49%     52.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9868460      5.52%     57.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6372149      3.56%     61.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 13508487      7.55%     68.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  9517347      5.32%     74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5905302      3.30%     77.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3555081      1.99%     79.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 36763919     20.56%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            178838548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.317197                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.810336                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 65738845                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              12641259                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  87702735                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3649079                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9106630                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             10252982                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4580                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              491283130                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 12139                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9106630                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 70077435                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4396073                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         392991                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  87026850                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               7838569                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              478183111                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  34338                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               6474620                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           310467420                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             626927534                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        331115388                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         295812146                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             259532319                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 50935101                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              38371                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            296                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  21811876                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            110641644                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            85552281                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           8662202                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5906832                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  433013718                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 258                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 418626838                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           2003473                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        56038444                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     32198216                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             43                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     178838548                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.340809                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.008173                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            44336411     24.79%     24.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            29007268     16.22%     41.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            27775406     15.53%     56.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            26238037     14.67%     71.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            22251353     12.44%     83.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15664112      8.76%     92.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8263195      4.62%     97.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3972623      2.22%     99.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1330143      0.74%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       178838548                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  135690      1.14%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                 41926      0.35%      1.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                  2442      0.02%      1.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  8992      0.08%      1.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              1877041     15.76%     17.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1762283     14.79%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5120089     42.98%     75.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2964035     24.88%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             164031789     39.18%     39.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2126165      0.51%     39.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            33716465      8.05%     47.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7893369      1.89%     49.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2899949      0.69%     50.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16711518      3.99%     54.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1573138      0.38%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            108174365     25.84%     80.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            81466499     19.46%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              418626838                       # Type of FU issued
+system.cpu.iq.rate                           2.339216                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    11912498                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.028456                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          681277012                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         289109429                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    241633599                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           348731183                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          199993522                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    164553982                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              252486483                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               178019272                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         13980098                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     15887158                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       143607                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        50570                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     12031553                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads       233419                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             5                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                9106630                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2382208                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                372749                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           458676643                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2278358                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             110641644                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             85552281                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                258                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    129                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    14                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          50570                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3441219                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       544657                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3985876                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             409944817                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             105588265                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           8682021                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                      25662667                       # number of nop insts executed
+system.cpu.iew.exec_refs                    185353481                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 48120403                       # Number of branches executed
+system.cpu.iew.exec_stores                   79765216                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.290702                       # Inst execution rate
+system.cpu.iew.wb_sent                      407421919                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     406187581                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 197894075                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 277422150                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       2.269707                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.713332                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      398664569                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        60016815                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           3547729                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    169731918                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.348790                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.858024                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     70140218     41.32%     41.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     25651558     15.11%     56.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     14667534      8.64%     65.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12267165      7.23%     72.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      9098146      5.36%     77.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      6161287      3.63%     81.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5543706      3.27%     84.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3203239      1.89%     86.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22999065     13.55%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    169731918                       # Number of insts commited each cycle
+system.cpu.commit.count                     398664569                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      168275214                       # Number of memory references committed
+system.cpu.commit.loads                      94754486                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   44587530                       # Number of branches committed
+system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 316365825                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              22999065                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    605411260                       # The number of ROB reads
+system.cpu.rob.rob_writes                   926487800                       # The number of ROB writes
+system.cpu.timesIdled                            2712                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          121803                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   375574794                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             375574794                       # Number of Instructions Simulated
+system.cpu.cpi                               0.476497                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.476497                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.098648                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.098648                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                409675274                       # number of integer regfile reads
+system.cpu.int_regfile_writes               175727060                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 159328411                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                105866122                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
+system.cpu.icache.replacements                   2110                       # number of replacements
+system.cpu.icache.tagsinuse               1834.326922                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 57898804                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   4037                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               14342.037156                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1834.326922                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.895667                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               57898804                       # number of ReadReq hits
+system.cpu.icache.demand_hits                57898804                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               57898804                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 5282                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  5282                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 5282                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      167914000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       167914000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      167914000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           57904086                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            57904086                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           57904086                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000091                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000091                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000091                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 31789.852329                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 31789.852329                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 31789.852329                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1245                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1245                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1245                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            4037                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             4037                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            4037                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    123459000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    123459000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    123459000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000070                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000070                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000070                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                    793                       # number of replacements
+system.cpu.dcache.tagsinuse               3296.196945                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                164730953                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4193                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               39287.134033                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3296.196945                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.804736                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               91229707                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              73501239                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits                7                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits               164730946                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              164730946                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1678                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               19489                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                 21167                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                21167                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       55919500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     568883000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       624802500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      624802500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           91231385                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          73520728                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses            7                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           164752113                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          164752113                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000265                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000128                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000128                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 29517.763500                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 29517.763500                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        13000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs         2600                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      671                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits               680                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits            16294                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits              16974                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits             16974                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             998                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           3195                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4193                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4193                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     31703500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    113133500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    144837000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    144837000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000011                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000043                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                    10                       # number of replacements
+system.cpu.l2cache.tagsinuse              4007.455925                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     810                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4847                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.167114                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3629.785283                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           377.670641                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.110772                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011526                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                   730                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 671                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  65                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                    795                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                   795                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4305                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              3130                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 7435                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                7435                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     148163500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    108392000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      256555500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     256555500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              5035                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses             671                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            3195                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               8230                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              8230                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.855015                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.979656                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.903402                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.903402                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34506.455952                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34506.455952                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           4305                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         3130                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            7435                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           7435                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    134314000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     98534000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    232848000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    232848000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.855015                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.979656                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.903402                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.903402                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..8310ba9e4
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..860580eeb
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,52 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0  8  14
+1  8  14
+2  8  14
+3  8  14
+4  8  14
+5  8  14
+6  8  14
+7  8  14
+8  8  14
+9  8  14
+10  8  14
+11  8  14
+12  8  14
+13  8  14
+14  8  14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..3a628f576
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.183333
+Exiting @ tick 199332411500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..3ed2b47f1
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.199332                       # Number of seconds simulated
+sim_ticks                                199332411500                       # Number of ticks simulated
+final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3927016                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1963508553                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204908                       # Number of bytes of host memory used
+host_seconds                                   101.52                       # Real time elapsed on the host
+sim_insts                                   398664595                       # Number of instructions simulated
+system.physmem.bytes_read                  2257107875                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             1594658604                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                492356798                       # Number of bytes written to this memory
+system.physmem.num_reads                    493419140                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    73520729                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    11323336020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999996548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    2470028804                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13793364824                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     94754489                       # DTB read hits
+system.cpu.dtb.read_misses                         21                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 94754510                       # DTB read accesses
+system.cpu.dtb.write_hits                    73520729                       # DTB write hits
+system.cpu.dtb.write_misses                        35                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                73520764                       # DTB write accesses
+system.cpu.dtb.data_hits                    168275218                       # DTB hits
+system.cpu.dtb.data_misses                         56                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                168275274                       # DTB accesses
+system.cpu.itb.fetch_hits                   398664651                       # ITB hits
+system.cpu.itb.fetch_misses                       173                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               398664824                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
+system.cpu.numCycles                        398664824                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        398664595                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             316365907                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
+system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     25997787                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    316365907                       # number of integer instructions
+system.cpu.num_fp_insts                     155295119                       # number of float instructions
+system.cpu.num_int_register_reads           372938760                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          159335860                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     168275274                       # number of memory refs
+system.cpu.num_load_insts                    94754510                       # Number of load instructions
+system.cpu.num_store_insts                   73520764                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  398664824                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..63aac5a1a
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..860580eeb
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,52 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0  8  14
+1  8  14
+2  8  14
+3  8  14
+4  8  14
+5  8  14
+6  8  14
+7  8  14
+8  8  14
+9  8  14
+10  8  14
+11  8  14
+12  8  14
+13  8  14
+14  8  14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..06075d86e
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.566667
+Exiting @ tick 567343170000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..af7a7f90d
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,265 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.567343                       # Number of seconds simulated
+sim_ticks                                567343170000                       # Number of ticks simulated
+final_tick                               567343170000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1814376                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2582053806                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213620                       # Number of bytes of host memory used
+host_seconds                                   219.73                       # Real time elapsed on the host
+sim_insts                                   398664609                       # Number of instructions simulated
+system.physmem.bytes_read                      459520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 205120                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         7180                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                         809951                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    361545                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                        809951                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     94754490                       # DTB read hits
+system.cpu.dtb.read_misses                         21                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 94754511                       # DTB read accesses
+system.cpu.dtb.write_hits                    73520730                       # DTB write hits
+system.cpu.dtb.write_misses                        35                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                73520765                       # DTB write accesses
+system.cpu.dtb.data_hits                    168275220                       # DTB hits
+system.cpu.dtb.data_misses                         56                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                168275276                       # DTB accesses
+system.cpu.itb.fetch_hits                   398664666                       # ITB hits
+system.cpu.itb.fetch_misses                       173                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               398664839                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
+system.cpu.numCycles                       1134686340                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        398664609                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             316365921                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
+system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     25997790                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    316365921                       # number of integer instructions
+system.cpu.num_fp_insts                     155295119                       # number of float instructions
+system.cpu.num_int_register_reads           372938779                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          159335870                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads            151776196                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           100196481                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     168275276                       # number of memory refs
+system.cpu.num_load_insts                    94754511                       # Number of load instructions
+system.cpu.num_store_insts                   73520765                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1134686340                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   1769                       # number of replacements
+system.cpu.icache.tagsinuse               1795.131074                       # Cycle average of tags in use
+system.cpu.icache.total_refs                398660993                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               108538.250204                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1795.131074                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.876529                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              398660993                       # number of ReadReq hits
+system.cpu.icache.demand_hits               398660993                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              398660993                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 3673                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  3673                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 3673                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      186032000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       186032000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      186032000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          398664666                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           398664666                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 50648.516199                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 50648.516199                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 50648.516199                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3673                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3673                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3673                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    175013000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    175013000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    175013000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000009                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000009                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                    764                       # number of replacements
+system.cpu.dcache.tagsinuse               3288.912598                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               40527.713873                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3288.912598                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.802957                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               94753540                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              73517528                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               168271068                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              168271068                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  950                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                3202                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  4152                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 4152                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       48286000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     176792000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       225078000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      225078000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           94754490                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          73520730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           168275220                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000044                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54209.537572                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54209.537572                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      649                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4152                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     45436000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    167186000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    212622000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    212622000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                    13                       # number of replacements
+system.cpu.l2cache.tagsinuse              3768.712262                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     656                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4572                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.143482                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3397.175455                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           371.536808                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.103674                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011338                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                   585                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 649                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  60                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                    645                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                   645                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4038                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              3142                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 7180                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                7180                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     209976000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    163384000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      373360000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     373360000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              4623                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses             649                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               7825                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.873459                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.981262                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.917572                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.917572                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           4038                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         3142                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            7180                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           7180                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    161520000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    125680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    287200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    287200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.873459                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.981262                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.917572                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.917572                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..297538e80
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..bf930ad43
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,48 @@
+warn: Sockets disabled, not accepting gdb connections
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0  8  14
+1  8  14
+2  8  14
+3  8  14
+4  8  14
+5  8  14
+6  8  14
+7  8  14
+8  8  14
+9  8  14
+10  8  14
+11  8  14
+12  8  14
+13  8  14
+14  8  14
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..2948fc7c4
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,16 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:57:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+OO-style eon Time= 0.100000
+Exiting @ tick 104497559500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..995432cc7
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,541 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.104498                       # Number of seconds simulated
+sim_ticks                                104497559500                       # Number of ticks simulated
+final_tick                               104497559500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 155883                       # Simulator instruction rate (inst/s)
+host_tick_rate                               46665641                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228988                       # Number of bytes of host memory used
+host_seconds                                  2239.28                       # Real time elapsed on the host
+sim_insts                                   349066034                       # Number of instructions simulated
+system.physmem.bytes_read                      464512                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 192704                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         7258                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        4445195                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1844100                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       4445195                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.numCycles                        208995120                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 38326507                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           21101495                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3258977                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              27386254                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 21276883                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  7682399                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               61114                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           43645867                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      338408122                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    38326507                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           28959282                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      79027162                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                10989913                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               78526305                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            81                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  41243030                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                908340                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          208882385                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.119969                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.192320                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                130507129     62.48%     62.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  9423807      4.51%     66.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6028759      2.89%     69.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6771553      3.24%     73.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  5439017      2.60%     75.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4859666      2.33%     78.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3802857      1.82%     79.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4240079      2.03%     81.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 37809518     18.10%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            208882385                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.183385                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.619215                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 51208963                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              73647751                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  72596931                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3816657                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                7612083                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              7463930                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 71162                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              431701457                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                197547                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                7612083                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 58859623                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1188483                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       57604104                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  68958235                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14659857                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              416634975                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                  21102                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               8024802                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               88                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           455431964                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2446622850                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1351809132                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups        1094813718                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             384568599                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 70863365                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            3987641                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        4044473                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  48252141                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            108792162                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            93099672                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3342545                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2273908                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  394239255                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3865155                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 379120981                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1801347                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        46369193                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    143590674                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         309514                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     208882385                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.814997                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.995935                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            82049002     39.28%     39.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            34801326     16.66%     55.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            24478546     11.72%     67.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18529016      8.87%     76.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            21712805     10.39%     86.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15357191      7.35%     94.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8402907      4.02%     98.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2691838      1.29%     99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              859754      0.41%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       208882385                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    2250      0.01%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5043      0.03%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd             10815      0.06%      0.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp              2509      0.01%      0.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               378      0.00%      0.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      0.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc            64370      0.37%      0.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult              798      0.00%      0.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        177500      1.02%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9658261     55.66%     57.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               7430721     42.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             129606192     34.19%     34.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2147281      0.57%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                   13      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6746387      1.78%     36.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8673518      2.29%     38.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3499070      0.92%     39.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1584810      0.42%     40.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       21149805      5.58%     45.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7187648      1.90%     47.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7147289      1.89%     49.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            103746274     27.36%     76.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            87457408     23.07%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              379120981                       # Type of FU issued
+system.cpu.iq.rate                           1.814018                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    17352648                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.045771                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          735350759                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         310614656                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    251531674                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           250927583                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          133866908                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    118270115                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              267600383                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               128873246                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          7282081                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     14143162                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       112354                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         8279                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     10723841                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads          272                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           117                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                7612083                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   19341                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   437                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           398151655                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2633597                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             108792162                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             93099672                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            3853935                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     34                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   205                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           8279                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3193235                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       309338                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3502573                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             373031388                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             102121270                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6089593                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         47245                       # number of nop insts executed
+system.cpu.iew.exec_refs                    188074720                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32215232                       # Number of branches executed
+system.cpu.iew.exec_stores                   85953450                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.784881                       # Inst execution rate
+system.cpu.iew.wb_sent                      370805637                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     369801789                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 175613931                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 345608979                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.769428                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.508129                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      349066646                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        49085191                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         3555641                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           3229927                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    201270303                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.734318                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.320939                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     89873146     44.65%     44.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     39586205     19.67%     64.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     17962686      8.92%     73.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13145817      6.53%     79.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     14573998      7.24%     87.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7584463      3.77%     90.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3507612      1.74%     92.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3437369      1.71%     94.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11599007      5.76%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    201270303                       # Number of insts commited each cycle
+system.cpu.commit.count                     349066646                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      177024831                       # Number of memory references committed
+system.cpu.commit.loads                      94649000                       # Number of loads committed
+system.cpu.commit.membars                       11033                       # Number of memory barriers committed
+system.cpu.commit.branches                   30521879                       # Number of branches committed
+system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 279585929                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              6225114                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              11599007                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    587820610                       # The number of ROB reads
+system.cpu.rob.rob_writes                   803918901                       # The number of ROB writes
+system.cpu.timesIdled                            2585                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          112735                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   349066034                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             349066034                       # Number of Instructions Simulated
+system.cpu.cpi                               0.598727                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.598727                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.670211                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.670211                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1781871579                       # number of integer regfile reads
+system.cpu.int_regfile_writes               235815438                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 188771754                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                133861667                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1003473737                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               34422193                       # number of misc regfile writes
+system.cpu.icache.replacements                  14107                       # number of replacements
+system.cpu.icache.tagsinuse               1842.677380                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 41226387                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  15987                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                2578.744417                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1842.677380                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.899745                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               41226387                       # number of ReadReq hits
+system.cpu.icache.demand_hits                41226387                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               41226387                       # number of overall hits
+system.cpu.icache.ReadReq_misses                16643                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 16643                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                16643                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      201090500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       201090500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      201090500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           41243030                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            41243030                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           41243030                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000404                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000404                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000404                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 12082.587274                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 12082.587274                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 12082.587274                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               637                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                637                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               637                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           16006                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            16006                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           16006                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    136032000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    136032000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    136032000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000388                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000388                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000388                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  8498.812945                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  8498.812945                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  8498.812945                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                   1408                       # number of replacements
+system.cpu.dcache.tagsinuse               3101.194672                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                176614084                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4596                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               38427.781549                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3101.194672                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.757128                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               94558380                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              82033210                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            11361                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             11114                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               176591590                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              176591590                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 3380                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               19484                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses                 22864                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                22864                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency      111762500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     649531500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        76000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency       761294000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      761294000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           94561760                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          82052694                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        11363                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         11114                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           176614454                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          176614454                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000036                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000237                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000176                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.000129                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000129                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 33065.828402                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33336.660850                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 33296.623513                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 33296.623513                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       307500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                     1030                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              1630                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits            16619                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits              18249                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits             18249                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses            1750                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           2865                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4615                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4615                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     53437000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    101725000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    155162000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    155162000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000019                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000026                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000026                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30535.428571                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35506.108202                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33621.235103                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33621.235103                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                    57                       # number of replacements
+system.cpu.l2cache.tagsinuse              3897.011564                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13334                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  5354                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.490474                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3518.810301                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           378.201262                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.107386                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011542                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 13251                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                1030                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  19                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  13270                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 13270                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4485                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses               19                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses              2828                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 7313                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                7313                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     153892500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     97502000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      251394500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     251394500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             17736                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses            1030                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses             19                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            2847                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              20583                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             20583                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.252876                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.993326                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.355293                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.355293                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34312.709030                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.369165                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34376.384521                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34376.384521                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               55                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                55                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               55                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           4430                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses           19                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         2828                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            7258                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           7258                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    138008000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       589000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     88479500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    226487500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    226487500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.249774                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.993326                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.352621                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.352621                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.047404                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31286.951909                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.221824                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.221824                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..5628f29f0
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..bf930ad43
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,48 @@
+warn: Sockets disabled, not accepting gdb connections
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0  8  14
+1  8  14
+2  8  14
+3  8  14
+4  8  14
+5  8  14
+6  8  14
+7  8  14
+8  8  14
+9  8  14
+10  8  14
+11  8  14
+12  8  14
+13  8  14
+14  8  14
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..2369bef1b
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,16 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:01:21
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+OO-style eon Time= 0.210000
+Exiting @ tick 212344048000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..7857a9031
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.212344                       # Number of seconds simulated
+sim_ticks                                212344048000                       # Number of ticks simulated
+final_tick                               212344048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2434260                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1480812932                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218160                       # Number of bytes of host memory used
+host_seconds                                   143.40                       # Real time elapsed on the host
+sim_insts                                   349065408                       # Number of instructions simulated
+system.physmem.bytes_read                  1875350709                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             1394641440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                400047783                       # Number of bytes written to this memory
+system.physmem.num_reads                    443242866                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    82063572                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8831661291                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                6567838624                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1883960425                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   10715621716                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.numCycles                        424688097                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        349065408                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             279584926                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
+system.cpu.num_func_calls                    12433363                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     16271154                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    279584926                       # number of integer instructions
+system.cpu.num_fp_insts                     114216705                       # number of float instructions
+system.cpu.num_int_register_reads          1887652191                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          251197918                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     177024357                       # number of memory refs
+system.cpu.num_load_insts                    94648758                       # Number of load instructions
+system.cpu.num_store_insts                   82375599                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  424688097                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..28a0917d8
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..bf930ad43
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,48 @@
+warn: Sockets disabled, not accepting gdb connections
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0  8  14
+1  8  14
+2  8  14
+3  8  14
+4  8  14
+5  8  14
+6  8  14
+7  8  14
+8  8  14
+9  8  14
+10  8  14
+11  8  14
+12  8  14
+13  8  14
+14  8  14
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..3428f8224
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,16 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:03:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+OO-style eon Time= 0.520000
+Exiting @ tick 525854475000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..3b365c759
--- /dev/null
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,279 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.525854                       # Number of seconds simulated
+sim_ticks                                525854475000                       # Number of ticks simulated
+final_tick                               525854475000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1206167                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1819018700                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227092                       # Number of bytes of host memory used
+host_seconds                                   289.09                       # Real time elapsed on the host
+sim_insts                                   348687131                       # Number of instructions simulated
+system.physmem.bytes_read                      437312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 167040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         6833                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                         831622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    317654                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                        831622                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.numCycles                       1051708950                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        348687131                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             279584925                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
+system.cpu.num_func_calls                    12433363                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     16271153                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    279584925                       # number of integer instructions
+system.cpu.num_fp_insts                     114216705                       # number of float instructions
+system.cpu.num_int_register_reads          2212913209                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          251197915                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     177024357                       # number of memory refs
+system.cpu.num_load_insts                    94648758                       # Number of load instructions
+system.cpu.num_store_insts                   82375599                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1051708950                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                  13796                       # number of replacements
+system.cpu.icache.tagsinuse               1765.984158                       # Cycle average of tags in use
+system.cpu.icache.total_refs                348644756                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  15603                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               22344.725758                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1765.984158                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.862297                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              348644756                       # number of ReadReq hits
+system.cpu.icache.demand_hits               348644756                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              348644756                       # number of overall hits
+system.cpu.icache.ReadReq_misses                15603                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 15603                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                15603                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      328062000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       328062000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      328062000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          348660359                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           348660359                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          348660359                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000045                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000045                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000045                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 21025.572005                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 21025.572005                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 21025.572005                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           15603                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            15603                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           15603                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    281253000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    281253000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    281253000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000045                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000045                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000045                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                   1332                       # number of replacements
+system.cpu.dcache.tagsinuse               3078.396238                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                176641600                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4478                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               39446.538633                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3078.396238                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.751562                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               94570005                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              82049805                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            10895                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             10895                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               176619810                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              176619810                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1606                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                2872                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  4478                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 4478                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       79898000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     160160000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       240058000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      240058000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           94571611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           176624288                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          176624288                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000017                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000035                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 53608.307280                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 53608.307280                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      998                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses            1606                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           2872                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4478                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4478                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     75080000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    151544000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    226624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    226624000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000017                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                    48                       # number of replacements
+system.cpu.l2cache.tagsinuse              3475.672922                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13308                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4883                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.725374                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3134.059650                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           341.613272                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.095644                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.010425                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 13232                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 998                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  16                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  13248                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 13248                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3977                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              2856                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 6833                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                6833                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     206804000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    148512000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      355316000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     355316000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             17209                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses             998                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            2872                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              20081                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             20081                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.231100                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.994429                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.340272                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.340272                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           3977                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         2856                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            6833                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           6833                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    159080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    114240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    273320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    273320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.231100                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994429                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.340272                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.340272                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/test.py b/tests/long/se/30.eon/test.py
new file mode 100644
index 000000000..de4d12dd8
--- /dev/null
+++ b/tests/long/se/30.eon/test.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import eon_cook
+
+workload = eon_cook(isa, opsys, 'mdred')
+root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..c87170fbe
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..ca52b457d
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,7 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(0, 1, ...)
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..2a099e16b
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,1388 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:26:04
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+Exiting @ tick 643030478500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..90210da82
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,526 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.643030                       # Number of seconds simulated
+sim_ticks                                643030478500                       # Number of ticks simulated
+final_tick                               643030478500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 153915                       # Simulator instruction rate (inst/s)
+host_tick_rate                               54289503                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215008                       # Number of bytes of host memory used
+host_seconds                                 11844.47                       # Real time elapsed on the host
+sim_insts                                  1823043370                       # Number of instructions simulated
+system.physmem.bytes_read                    94779264                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 185664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  4281472                       # Number of bytes written to this memory
+system.physmem.num_reads                      1480926                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       66898                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      147394668                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    288733                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       6658272                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     154052940                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    520282071                       # DTB read hits
+system.cpu.dtb.read_misses                     658976                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                520941047                       # DTB read accesses
+system.cpu.dtb.write_hits                   283837075                       # DTB write hits
+system.cpu.dtb.write_misses                     53680                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               283890755                       # DTB write accesses
+system.cpu.dtb.data_hits                    804119146                       # DTB hits
+system.cpu.dtb.data_misses                     712656                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                804831802                       # DTB accesses
+system.cpu.itb.fetch_hits                   398310361                       # ITB hits
+system.cpu.itb.fetch_misses                       225                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               398310586                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   39                       # Number of system calls
+system.cpu.numCycles                       1286060958                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                402586298                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          267183275                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           28898117                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             333702913                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                271687015                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 60998120                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                7269                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          415096525                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3352093116                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   402586298                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          332685135                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     645195661                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               165271358                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               89752324                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  146                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          4176                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 398310361                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11197226                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1285935042                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.606736                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.132660                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                640739381     49.83%     49.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 57260959      4.45%     54.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 45174683      3.51%     57.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 73956325      5.75%     63.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                134643957     10.47%     74.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 43704830      3.40%     77.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 44948525      3.50%     80.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  8228368      0.64%     81.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                237278014     18.45%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total           1285935042                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.313038                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.606481                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                451176980                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              71498937                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 618592802                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8792068                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              135874255                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             30910962                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12070                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3252787569                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 45959                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              135874255                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                481268394                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                29024257                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          25510                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 595950971                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              43791655                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3151351284                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   355                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 750555                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              36590752                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2105050619                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3698513195                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3586317765                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         112195430                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                720081549                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4177                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             82                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 124172087                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            732020123                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           345520616                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          66357929                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8901879                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2642218507                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  75                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2155449111                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          17941201                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       818701684                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    780988431                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             36                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1285935042                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.676173                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.767949                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           465245543     36.18%     36.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           229606292     17.86%     54.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           242969112     18.89%     72.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           129449912     10.07%     83.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           105111994      8.17%     91.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            71454382      5.56%     96.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            23774402      1.85%     98.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            15398679      1.20%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2924726      0.23%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1285935042                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   19151      0.06%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               21356146     65.69%     65.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              11134345     34.25%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1238361266     57.45%     57.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                16703      0.00%     57.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            27850917      1.29%     58.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             8254688      0.38%     59.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             7204646      0.33%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            584304865     27.11%     86.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           289453270     13.43%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             2155449111                       # Type of FU issued
+system.cpu.iq.rate                           1.676009                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    32509642                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.015083                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5498808910                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3382020905                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1990959088                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           148475197                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           78969876                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     72622847                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2112315501                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                75640500                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         67702370                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    220950097                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       171000                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        71734                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    134725720                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         4434                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            21                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles              135874255                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3818188                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                203306                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3005431260                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2750522                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             732020123                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            345520616                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 75                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 131111                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  4921                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          71734                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       30723187                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       903682                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             31626869                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2066254472                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             520941220                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          89194639                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                     363212678                       # number of nop insts executed
+system.cpu.iew.exec_refs                    804832688                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                279771397                       # Number of branches executed
+system.cpu.iew.exec_stores                  283891468                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.606654                       # Inst execution rate
+system.cpu.iew.wb_sent                     2065581707                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2063581935                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1176945723                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1742555439                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.604576                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.675414                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     2008987604                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       979738658                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          28886163                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1150060787                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.746853                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.513737                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    543040951     47.22%     47.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    216685952     18.84%     66.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    119778809     10.41%     76.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     61132291      5.32%     81.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     44136002      3.84%     85.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24968433      2.17%     87.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19265020      1.68%     89.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     16055764      1.40%     90.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    104997565      9.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1150060787                       # Number of insts commited each cycle
+system.cpu.commit.count                    2008987604                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      721864922                       # Number of memory references committed
+system.cpu.commit.loads                     511070026                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                  266706457                       # Number of branches committed
+system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events             104997565                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   4028153074                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6113513811                       # The number of ROB writes
+system.cpu.timesIdled                            3507                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          125916                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
+system.cpu.cpi                               0.705447                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.705447                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.417540                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.417540                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2630724063                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1493026464                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  77824314                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 52830391                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
+system.cpu.icache.replacements                   8239                       # number of replacements
+system.cpu.icache.tagsinuse               1650.873085                       # Cycle average of tags in use
+system.cpu.icache.total_refs                398299261                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   9946                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               40046.175447                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1650.873085                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.806090                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              398299261                       # number of ReadReq hits
+system.cpu.icache.demand_hits               398299261                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              398299261                       # number of overall hits
+system.cpu.icache.ReadReq_misses                11100                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 11100                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                11100                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      182477500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       182477500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      182477500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          398310361                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           398310361                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          398310361                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000028                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000028                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000028                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 16439.414414                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 16439.414414                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 16439.414414                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1153                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1153                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1153                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            9947                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             9947                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            9947                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    119555000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    119555000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    119555000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000025                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12019.201769                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12019.201769                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12019.201769                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1527592                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.113983                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                660890207                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1531688                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 431.478347                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              255376000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.113983                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999784                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              450646939                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             210243259                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits               660890198                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              660890198                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1928305                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              551637                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               2479942                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2479942                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    71444429000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   20878144491                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        59000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     92322573491                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    92322573491                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          452575244                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           663370140                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          663370140                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.004261                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.002617                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.181818                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.003738                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.003738                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 37050.377923                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 37847.614448                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        29500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 37227.714798                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 37227.714798                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        79500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        20500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                14                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5678.571429                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        20500                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   107326                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            468223                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           480032                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             948255                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            948255                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1460082                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          71605                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1531687                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1531687                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  49942277500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2493130000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  52435407500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  52435407500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.003226                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000340                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.090909                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002309                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002309                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34205.118274                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34817.819985                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34233.761532                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34233.761532                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               1480630                       # number of replacements
+system.cpu.l2cache.tagsinuse             31935.913288                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   63583                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1513317                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.042016                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         28876.475418                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3059.437870                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.881240                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.093367                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 55959                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              107326                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                4750                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  60709                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 60709                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1414071                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             66855                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              1480926                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             1480926                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   48513510000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2349021500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    50862531500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   50862531500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1470030                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          107326                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           71605                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1541635                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1541635                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.961933                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.933664                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.960620                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.960620                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34307.690349                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.063122                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34345.086453                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34345.086453                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs        37500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                5                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs         7500                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   66898                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1414071                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        66855                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1480926                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        1480926                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  43837380500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2147695000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  45985075500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  45985075500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.961933                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.933664                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.960620                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.960620                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.834117                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.672799                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568748                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568748                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..a895468a4
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..ca52b457d
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,7 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(0, 1, ...)
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..67c7a90bd
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,1388 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:26:36
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+Exiting @ tick 1004710587000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..5a9e50b92
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  1.004711                       # Number of seconds simulated
+sim_ticks                                1004710587000                       # Number of ticks simulated
+final_tick                               1004710587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                4051601                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2026237516                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204820                       # Number of bytes of host memory used
+host_seconds                                   495.85                       # Real time elapsed on the host
+sim_insts                                  2008987605                       # Number of instructions simulated
+system.physmem.bytes_read                 11607100996                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             8037684280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written               1586125963                       # Number of bytes written to this memory
+system.physmem.num_reads                   2520491096                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   210794896                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    11552681087                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999999586                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1578689409                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13131370496                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    511070026                       # DTB read hits
+system.cpu.dtb.read_misses                     418884                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
+system.cpu.dtb.write_hits                   210794896                       # DTB write hits
+system.cpu.dtb.write_misses                     14581                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               210809477                       # DTB write accesses
+system.cpu.dtb.data_hits                    721864922                       # DTB hits
+system.cpu.dtb.data_misses                     433465                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                722298387                       # DTB accesses
+system.cpu.itb.fetch_hits                  2009421070                       # ITB hits
+system.cpu.itb.fetch_misses                       105                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses              2009421175                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   39                       # Number of system calls
+system.cpu.numCycles                       2009421175                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       2008987605                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
+system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1779374816                       # number of integer instructions
+system.cpu.num_fp_insts                      71831671                       # number of float instructions
+system.cpu.num_int_register_reads          2314712013                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1332688300                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     722298387                       # number of memory refs
+system.cpu.num_load_insts                   511488910                       # Number of load instructions
+system.cpu.num_store_insts                  210809477                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 2009421175                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..f60b78837
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..ca52b457d
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,7 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(0, 1, ...)
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..e767ec1c4
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,1388 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:03
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+Exiting @ tick 2813467842000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..668a6f1dd
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,266 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.813468                       # Number of seconds simulated
+sim_ticks                                2813467842000                       # Number of ticks simulated
+final_tick                               2813467842000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1954286                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2736861040                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213480                       # Number of bytes of host memory used
+host_seconds                                  1027.99                       # Real time elapsed on the host
+sim_insts                                  2008987605                       # Number of instructions simulated
+system.physmem.bytes_read                    94708160                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 152128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  4281472                       # Number of bytes written to this memory
+system.physmem.num_reads                      1479815                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       66898                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       33662428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     54071                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       1521777                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      35184206                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    511070026                       # DTB read hits
+system.cpu.dtb.read_misses                     418884                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
+system.cpu.dtb.write_hits                   210794896                       # DTB write hits
+system.cpu.dtb.write_misses                     14581                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               210809477                       # DTB write accesses
+system.cpu.dtb.data_hits                    721864922                       # DTB hits
+system.cpu.dtb.data_misses                     433465                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                722298387                       # DTB accesses
+system.cpu.itb.fetch_hits                  2009421071                       # ITB hits
+system.cpu.itb.fetch_misses                       105                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses              2009421176                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   39                       # Number of system calls
+system.cpu.numCycles                       5626935684                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       2008987605                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
+system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1779374816                       # number of integer instructions
+system.cpu.num_fp_insts                      71831671                       # number of float instructions
+system.cpu.num_int_register_reads          2314712013                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1332688300                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     722298387                       # number of memory refs
+system.cpu.num_load_insts                   511488910                       # Number of load instructions
+system.cpu.num_store_insts                  210809477                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 5626935684                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   9046                       # number of replacements
+system.cpu.icache.tagsinuse               1478.423269                       # Cycle average of tags in use
+system.cpu.icache.total_refs               2009410475                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               189638.587675                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1478.423269                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.721886                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits             2009410475                       # number of ReadReq hits
+system.cpu.icache.demand_hits              2009410475                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             2009410475                       # number of overall hits
+system.cpu.icache.ReadReq_misses                10596                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 10596                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                10596                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      248178000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       248178000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      248178000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         2009421071                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          2009421071                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         2009421071                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 23421.857305                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 23421.857305                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 23421.857305                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           10596                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            10596                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           10596                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    216390000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    216390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    216390000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1526048                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.204626                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             1049839000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.204626                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999806                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             210722944                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               720334778                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              720334778                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               71952                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1530144                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1530144                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    79658418000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    3815994000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     83474412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    83474412000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000341                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.002120                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002120                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54553.304787                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54553.304787                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   107612                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          71952                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1530144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1530144                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  75283842000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3600138000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  78883980000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  78883980000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000341                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002120                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002120                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               1479797                       # number of replacements
+system.cpu.l2cache.tagsinuse             31929.841726                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   63431                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1512480                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.041938                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         28848.012979                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3081.828747                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.880371                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.094050                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 55846                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              107612                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                5079                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  60925                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 60925                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1412942                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             66873                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              1479815                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             1479815                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   73472984000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3477396000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    76950380000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   76950380000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1468788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          107612                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           71952                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1540740                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.961978                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.929411                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.960457                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.960457                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   66898                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1412942                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        66873                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1479815                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        1479815                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56517680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2674920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  59192600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  59192600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.961978                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.929411                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.960457                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.960457                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..7e5e4838d
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..cba73e085
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: fcntl64(3, 2) passed through to host
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..af8b043ac
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,1388 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:08:55
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+1375000: 2038431008
+1374000: 3487365506
+1373000: 4184770123
+1372000: 1943746837
+1371000: 2651673663
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+Exiting @ tick 708403313500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..7b72f7ce4
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,544 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.708403                       # Number of seconds simulated
+sim_ticks                                708403313500                       # Number of ticks simulated
+final_tick                               708403313500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 118434                       # Simulator instruction rate (inst/s)
+host_tick_rate                               44501063                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226576                       # Number of bytes of host memory used
+host_seconds                                 15918.80                       # Real time elapsed on the host
+sim_insts                                  1885333786                       # Number of instructions simulated
+system.physmem.bytes_read                    94812032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 200960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  4230336                       # Number of bytes written to this memory
+system.physmem.num_reads                      1481438                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       66099                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      133839058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    283680                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       5971649                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     139810707                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
+system.cpu.numCycles                       1416806628                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                503033036                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          388160087                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           32894916                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             402481986                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                281923865                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 59796610                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect             2840141                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          410550003                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2542460473                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   503033036                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          341720475                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     682921340                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               205013758                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              105428035                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2115                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         34704                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 384233965                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              12151873                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1365478165                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.588855                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.160415                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                682595631     49.99%     49.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 48342952      3.54%     53.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                108702790      7.96%     61.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 62379051      4.57%     66.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 89292584      6.54%     72.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 54148565      3.97%     76.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 35470304      2.60%     79.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 34965610      2.56%     81.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                249580678     18.28%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total           1365478165                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.355047                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.794501                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                455361727                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              85217138                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 647145530                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              11223736                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              166530034                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             68649997                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12124                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3424361675                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 24057                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              166530034                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                496888956                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                29110139                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        3718079                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 615295356                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              53935601                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3298153337                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                4569845                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              42334817                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents                3                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          3261061532                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           15624755618                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      14989571898                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         635183720                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1993153599                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps               1267907933                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             310582                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         306325                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 155884977                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads           1045137132                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           527476218                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          35886570                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         45267364                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 3077754179                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              303954                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2619291842                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          18689867                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1192085861                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   2899457281                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          92624                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1365478165                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.918223                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.900205                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           480779837     35.21%     35.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           182587607     13.37%     48.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           216609244     15.86%     64.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           179766275     13.17%     77.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           150868799     11.05%     88.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            89721779      6.57%     95.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            48758870      3.57%     98.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            11536421      0.84%     99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4849333      0.36%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1365478165                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2044403      2.26%      2.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  23929      0.03%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               55649007     61.42%     63.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              32885475     36.30%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1200920026     45.85%     45.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult             11234109      0.43%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     46.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.05%     46.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     46.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         6876476      0.26%     46.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         5505406      0.21%     46.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       24362118      0.93%     47.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            895924024     34.20%     81.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           473094394     18.06%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             2619291842                       # Type of FU issued
+system.cpu.iq.rate                           1.848729                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    90602814                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.034591                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6584849993                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4170838685                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2409550549                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           128504537                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           99358414                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     57073276                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2644267181                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                65627475                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         71974387                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    413748263                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       264274                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      1389738                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    250479234                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads           88                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            24                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles              166530034                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                16377218                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1473925                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3078126585                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          12745051                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts            1045137132                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            527476218                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             292477                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1470662                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   212                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        1389738                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       34580674                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8873578                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             43454252                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2534450261                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             842463670                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          84841581                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         68452                       # number of nop insts executed
+system.cpu.iew.exec_refs                   1294415982                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                344601931                       # Number of branches executed
+system.cpu.iew.exec_stores                  451952312                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.788847                       # Inst execution rate
+system.cpu.iew.wb_sent                     2495608341                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2466623825                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1448525550                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2707902616                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.740974                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.534925                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1885344802                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts      1192782047                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          211330                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          38420798                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1198948133                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.572499                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.256451                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    532143962     44.38%     44.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    299077946     24.95%     69.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    106761313      8.90%     78.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     77538501      6.47%     84.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     53400435      4.45%     89.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     23357302      1.95%     91.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     17130441      1.43%     92.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      9348033      0.78%     93.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     80190200      6.69%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1198948133                       # Number of insts commited each cycle
+system.cpu.commit.count                    1885344802                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      908385853                       # Number of memory references committed
+system.cpu.commit.loads                     631388869                       # Number of loads committed
+system.cpu.commit.membars                        9986                       # Number of memory barriers committed
+system.cpu.commit.branches                  291350232                       # Number of branches committed
+system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1653705623                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              80190200                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   4196866437                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6322804382                       # The number of ROB writes
+system.cpu.timesIdled                         1340913                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        51328463                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1885333786                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1885333786                       # Number of Instructions Simulated
+system.cpu.cpi                               0.751488                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.751488                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.330692                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.330692                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads              12567203807                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2360160094                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  68800597                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 50187558                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              3980455481                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               13776276                       # number of misc regfile writes
+system.cpu.icache.replacements                  27305                       # number of replacements
+system.cpu.icache.tagsinuse               1638.856970                       # Cycle average of tags in use
+system.cpu.icache.total_refs                384199729                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  28984                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               13255.579941                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1638.856970                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.800223                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              384199814                       # number of ReadReq hits
+system.cpu.icache.demand_hits               384199814                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              384199814                       # number of overall hits
+system.cpu.icache.ReadReq_misses                34151                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 34151                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                34151                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      301141000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       301141000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      301141000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          384233965                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           384233965                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          384233965                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000089                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000089                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000089                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  8817.926269                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  8817.926269                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  8817.926269                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               772                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                772                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               772                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           33379                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            33379                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           33379                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    180850500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    180850500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    180850500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000087                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000087                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000087                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  5418.092214                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  5418.092214                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  5418.092214                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1531788                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.791932                       # Cycle average of tags in use
+system.cpu.dcache.total_refs               1029449306                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1535884                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 670.265011                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              305577000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.791932                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999705                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              753290045                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             276118528                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            15313                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             11672                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits              1029408573                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits             1029408573                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1938158                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              817150                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               2755308                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2755308                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    69348240500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   28488261000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       108500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     97836501500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    97836501500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          755228203                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        15316                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         11672                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses          1032163881                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses         1032163881                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002566                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.002951                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000196                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.002669                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002669                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 35780.488742                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 34862.951722                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 35508.372022                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 35508.372022                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        62000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        15500                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   106544                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            474971                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           740057                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1215028                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1215028                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1463187                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          77093                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1540280                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1540280                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  50020048000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2484862000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  52504910000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  52504910000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001937                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000278                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.001492                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001492                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34185.683716                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32232.005500                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34087.899603                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34087.899603                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               1480006                       # number of replacements
+system.cpu.l2cache.tagsinuse             31970.917218                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   84924                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1512726                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.056140                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         29008.328912                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          2962.588306                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.885264                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.090411                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 76788                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              106544                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits                  4                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits                6616                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  83404                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 83404                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1415384                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses             4391                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses             66082                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              1481466                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             1481466                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   48555371000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2252634000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    50808005000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   50808005000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1492172                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          106544                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses           4395                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           72698                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1564870                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1564870                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.948539                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.999090                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.908993                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.946702                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.946702                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34305.440078                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.465845                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34295.761766                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34295.761766                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   66099                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               28                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                28                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               28                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1415356                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses         4391                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        66082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1481438                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        1481438                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  43973863500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency    136121000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048597500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  46022461000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  46022461000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.948521                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.999090                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908993                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.946684                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.946684                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118653                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..6a275dc9a
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..cba73e085
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: fcntl64(3, 2) passed through to host
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..dd29e750e
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,1388 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:17:45
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+Exiting @ tick 945613131000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..49ae2817e
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.945613                       # Number of seconds simulated
+sim_ticks                                945613131000                       # Number of ticks simulated
+final_tick                               945613131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2997522                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1503443037                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215364                       # Number of bytes of host memory used
+host_seconds                                   628.97                       # Real time elapsed on the host
+sim_insts                                  1885336367                       # Number of instructions simulated
+system.physmem.bytes_read                  8025491315                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             5561086040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written               1123958396                       # Number of bytes written to this memory
+system.physmem.num_reads                   2010616909                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   276945663                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8487076852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                5880931491                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1188602780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9675679632                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
+system.cpu.numCycles                       1891226263                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1885336367                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1653698876                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
+system.cpu.num_func_calls                    80344203                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    223625914                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1653698876                       # number of integer instructions
+system.cpu.num_fp_insts                      52289415                       # number of float instructions
+system.cpu.num_int_register_reads          8601515950                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1874331406                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     908382480                       # number of memory refs
+system.cpu.num_load_insts                   631387182                       # Number of load instructions
+system.cpu.num_store_insts                  276995298                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1891226263                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..01aaafc03
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..cba73e085
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: fcntl64(3, 2) passed through to host
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..df0dd80b9
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,1388 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:28:26
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+0: 2206428413
+Exiting @ tick 2369901960000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..117215dc5
--- /dev/null
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.369902                       # Number of seconds simulated
+sim_ticks                                2369901960000                       # Number of ticks simulated
+final_tick                               2369901960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1407810                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1780114775                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224180                       # Number of bytes of host memory used
+host_seconds                                  1331.32                       # Real time elapsed on the host
+sim_insts                                  1874244950                       # Number of instructions simulated
+system.physmem.bytes_read                    94696320                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 144448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  4230336                       # Number of bytes written to this memory
+system.physmem.num_reads                      1479630                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       66099                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       39957906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     60951                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       1785026                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      41742932                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
+system.cpu.numCycles                       4739803920                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1874244950                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1653698876                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
+system.cpu.num_func_calls                    80344203                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    223625914                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1653698876                       # number of integer instructions
+system.cpu.num_fp_insts                      52289415                       # number of float instructions
+system.cpu.num_int_register_reads         10466679954                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1874331406                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     908382480                       # number of memory refs
+system.cpu.num_load_insts                   631387182                       # Number of load instructions
+system.cpu.num_store_insts                  276995298                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 4739803920                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                  18364                       # number of replacements
+system.cpu.icache.tagsinuse               1392.324437                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1390251708                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               70204.095743                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1392.324437                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.679846                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits             1390251708                       # number of ReadReq hits
+system.cpu.icache.demand_hits              1390251708                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             1390251708                       # number of overall hits
+system.cpu.icache.ReadReq_misses                19803                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 19803                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                19803                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      372036000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       372036000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      372036000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         1390271511                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          1390271511                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         1390271511                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000014                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000014                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 18786.850477                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 18786.850477                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 18786.850477                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           19803                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            19803                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           19803                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    312627000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    312627000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    312627000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000014                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000014                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1529557                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.960333                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                895757409                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 584.067849                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              997882000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.960333                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999746                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              618874541                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             276862898                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             9985                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              9985                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               895737439                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              895737439                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1460873                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               72780                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1533653                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1533653                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    79725982000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    3794826000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     83520808000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    83520808000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          620335414                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         9985                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          9985                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           897271092                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          897271092                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002355                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000263                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.001709                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.001709                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54458.738711                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54458.738711                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   107259                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1460873                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          72780                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1533653                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1533653                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  75343363000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3576486000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  78919849000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  78919849000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002355                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.001709                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001709                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               1478755                       # number of replacements
+system.cpu.l2cache.tagsinuse             31934.844118                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   75453                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1511475                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.049920                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         28893.420796                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3041.423322                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.881757                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.092817                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 67139                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              107259                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                6687                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  73826                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 73826                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1413537                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             66093                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              1479630                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             1479630                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   73503924000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3436836000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    76940760000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   76940760000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1480676                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          107259                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           72780                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1553456                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1553456                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.954657                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.908120                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.952476                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.952476                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   66099                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1413537                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        66093                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1479630                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        1479630                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56541480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2643720000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  59185200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  59185200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.954657                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908120                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.952476                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.952476                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/test.py b/tests/long/se/40.perlbmk/test.py
new file mode 100644
index 000000000..8fe5d6047
--- /dev/null
+++ b/tests/long/se/40.perlbmk/test.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import perlbmk_makerand
+
+workload = perlbmk_makerand(isa, opsys, 'lgred')
+root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
new file mode 100644
index 000000000..1b963b10c
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -0,0 +1,240 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
new file mode 100755
index 000000000..0aab67a06
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:56
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 46914279500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
new file mode 100644
index 000000000..472b08431
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
@@ -0,0 +1,158 @@
+
+  SYSTEM TYPE...
+  __ZTC__                := False 
+  __UNIX__               := True 
+  __RISC__               := True 
+  SPEC_CPU2000_LP64        := True 
+  __MAC__                := False 
+  __BCC__                := False 
+  __BORLANDC__           := False 
+  __GUI__                := False 
+  __WTC__                := False 
+  __HP__                 := False 
+
+  CODE OPTIONS...
+  __MACROIZE_HM__        := True 
+  __MACROIZE_MEM__       := True 
+  ENV01                  := True 
+  USE_HPP_STYPE_HDRS     := False 
+  USE_H_STYPE_HDRS       := False 
+
+  CODE INCLUSION PARAMETERS...
+  INCLUDE_ALL_CODE       := False 
+  INCLUDE_DELETE_CODE    := True 
+  __SWAP_GRP_POS__       := True 
+  __INCLUDE_MTRX__       := False 
+  __BAD_CODE__           := False 
+  API_INCLUDE            := False 
+  BE_CAREFUL             := False 
+  OLDWAY                 := False 
+  NOTUSED                := False 
+
+  SYSTEM PARAMETERS...
+  EXT_ENUM               := 999999999L 
+  CHUNK_CONSTANT         := 55555555 
+  CORE_CONSTANT          := 55555555 
+  CORE_LIMIT             := 20971520 
+  CorePage_Size          := 384000 
+  ALIGN_BYTES            := True 
+  CORE_BLOCK_ALIGN       :=    8 
+  FAR_MEM                := False 
+
+  MEMORY MANAGEMENT PARAMETERS...
+  SYSTEM_ALLOC           := True 
+  SYSTEM_FREESTORE       := True 
+  __NO_DISKCACHE__       := False 
+  __FREEZE_VCHUNKS__     := True 
+  __FREEZE_GRP_PACKETS__ := True 
+  __MINIMIZE_TREE_CACHE__:= True 
+
+  SYSTEM STD PARAMETERS...
+  __STDOUT__             := False 
+  NULL                   :=    0 
+  LPTR                   := False 
+  False_Status           :=    1 
+  True_Status            :=    0 
+  LARGE                  := True 
+  TWOBYTE_BOOL           := False 
+  __NOSTR__              := False 
+
+  MEMORY VALIDATION PARAMETERS...
+  CORE_CRC_CHECK         := False 
+  VALIDATE_MEM_CHUNKS    := False 
+
+  SYSTEM DEBUG OPTIONS...
+  DEBUG                  := False 
+  MCSTAT                 := False 
+  TRACKBACK              := False 
+  FLUSH_FILES            := False 
+  DEBUG_CORE0            := False 
+  DEBUG_RISC             := False 
+  __TREE_BUG__           := False 
+  __TRACK_FILE_READS__   := False 
+  PAGE_SPACE             := False 
+  LEAVE_NO_TRACE         := True 
+  NULL_TRACE_STRS        := False 
+
+  TIME PARAMETERS...
+  CLOCK_IS_LONG          := False 
+  __DISPLAY_TIME__       := False 
+  __TREE_TIME__          := False 
+  __DISPLAY_ERRORS__     := False 
+
+  API MACROS...
+  __BMT01__              := True 
+  OPTIMIZE               := True 
+
+  END OF DEFINES.
+
+
+
+              ...   IMPLODE MEMORY ...
+
+  SWAP to DiskCache := False
+
+  FREEZE_GRP_PACKETS:= True
+
+  QueBug            := 1000
+
+  sizeof(boolean)      =  4
+  sizeof(sizetype)     =  4
+  sizeof(chunkstruc)   = 32
+
+  sizeof(shorttype )   =  2
+  sizeof(idtype    )   =  2
+  sizeof(sizetype  )   =  4
+  sizeof(indextype )   =  4
+  sizeof(numtype   )   =  4
+  sizeof(handletype)   =  4
+  sizeof(tokentype )   =  8
+
+  sizeof(short     )   =  2
+  sizeof(int       )   =  4
+
+  sizeof(lt64      )   =  4
+  sizeof(farlongtype)  =  4
+  sizeof(long      )   =  8
+  sizeof(longaddr  )   =  8
+
+  sizeof(float     )   =  4
+  sizeof(double    )   =  8
+
+  sizeof(addrtype  )   =  8
+  sizeof(char *    )   =  8
+ ALLOC   CORE_1    :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @  2030c0
+    DB BlkDirChunk       : Chunk[  10] AT Vbn[3146]
+    DB BlkTknChunk       : Chunk[  11] AT Vbn[3147]
+    DB BlkSizeChunk      : Chunk[  12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+  DB[ 1] LOADED;  Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @   21c40
+    DB BlkDirChunk       : Chunk[  31] AT Vbn[ 81]
+    DB BlkTknChunk       : Chunk[  32] AT Vbn[ 82]
+    DB BlkSizeChunk      : Chunk[  33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+  DB[ 2] LOADED;  Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+    BE HERE NOW !!!
+
+
+
+               ... VORTEx ON LINE ...
+
+
+              ...   END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
new file mode 100644
index 000000000..32a07ce20
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -0,0 +1,315 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.046914                       # Number of seconds simulated
+sim_ticks                                 46914279500                       # Number of ticks simulated
+final_tick                                46914279500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 107347                       # Simulator instruction rate (inst/s)
+host_tick_rate                               57007816                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216192                       # Number of bytes of host memory used
+host_seconds                                   822.94                       # Real time elapsed on the host
+sim_insts                                    88340673                       # Number of instructions simulated
+system.physmem.bytes_read                    11164096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 599296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  7712960                       # Number of bytes written to this memory
+system.physmem.num_reads                       174439                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      120515                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      237967973                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  12774277                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     164405381                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     402373354                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     20277222                       # DTB read hits
+system.cpu.dtb.read_misses                      90148                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 20367370                       # DTB read accesses
+system.cpu.dtb.write_hits                    14736811                       # DTB write hits
+system.cpu.dtb.write_misses                      7252                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                14744063                       # DTB write accesses
+system.cpu.dtb.data_hits                     35014033                       # DTB hits
+system.cpu.dtb.data_misses                      97400                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                 35111433                       # DTB accesses
+system.cpu.itb.fetch_hits                    12380499                       # ITB hits
+system.cpu.itb.fetch_misses                     10576                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                12391075                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
+system.cpu.numCycles                         93828560                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                      77431415                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                          305691                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        24228941                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         69599619                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         74.177435                       # Percentage of cycles cpu is active
+system.cpu.comLoads                          20276638                       # Number of Load instructions committed
+system.cpu.comStores                         14613377                       # Number of Store instructions committed
+system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
+system.cpu.comNops                            8748916                       # Number of Nop instructions committed
+system.cpu.comNonSpec                            4583                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                           30791227                       # Number of Integer instructions committed
+system.cpu.comFloats                           151453                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                    88340673                       # Number of Instructions Simulated (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total              88340673                       # Number of Instructions Simulated (Total)
+system.cpu.cpi                               1.062122                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         1.062122                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.941512                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         0.941512                       # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups          18761151                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted     12342012                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect      4785453                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups       15763185                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits           4708455                       # Number of BTB hits
+system.cpu.branch_predictor.usedRAS           1660959                       # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect         1029                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct       29.869947                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken      8112975                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken     10648176                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads     74148043                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites     52319250                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses    126467293                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads        65874                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites       227630                       # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses       293504                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards       14179622                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                   35053135                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect      4496417                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect       178536                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted        4674953                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted           9097544                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     33.944121                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions         44764178                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies             41107                       # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.stage0.idleCycles                 41142190                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  52686370                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               56.151741                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 51376338                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  42452222                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               45.244456                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 50789796                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  43038764                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               45.869577                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 71702339                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  22126221                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               23.581542                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 47784207                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  46044353                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               49.072855                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                  83610                       # number of replacements
+system.cpu.icache.tagsinuse               1886.858130                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12263478                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  85656                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 143.171266                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1886.858130                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.921317                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               12263478                       # number of ReadReq hits
+system.cpu.icache.demand_hits                12263478                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               12263478                       # number of overall hits
+system.cpu.icache.ReadReq_misses               116984                       # number of ReadReq misses
+system.cpu.icache.demand_misses                116984                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses               116984                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     2068004000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      2068004000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     2068004000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           12380462                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            12380462                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           12380462                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.009449                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.009449                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.009449                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 17677.665322                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 17677.665322                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 17677.665322                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets      1596000                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets             172                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets  9279.069767                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits             31328                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits              31328                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits             31328                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           85656                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            85656                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           85656                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency   1345401500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   1345401500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   1345401500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.006919                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.006919                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.006919                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15707.031615                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15707.031615                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15707.031615                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 200251                       # number of replacements
+system.cpu.dcache.tagsinuse               4073.105766                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 34126014                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 204347                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 167.000318                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              486265000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4073.105766                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994411                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               20180445                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              13945569                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                34126014                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               34126014                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                96193                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              667808                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                764001                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               764001                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     4158649000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   35332073000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     39490722000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    39490722000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.004744                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.045698                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.021897                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.021897                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 43232.345389                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 52907.531806                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 51689.359045                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 51689.359045                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   6330522500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          124112                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   161216                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             35426                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           524228                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             559654                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            559654                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           60767                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         143580                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           204347                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          204347                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   2088724500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   7254420000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   9343144500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   9343144500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009825                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005857                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005857                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34372.677605                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.282073                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 45721.955791                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 45721.955791                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                148060                       # number of replacements
+system.cpu.l2cache.tagsinuse             18663.556927                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  131331                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                173405                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.757366                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3005.792321                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15657.764606                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.091730                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.477837                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                103294                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              161216                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               12270                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 115564                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                115564                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               42939                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            131500                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               174439                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              174439                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    2242306500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   6854385000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     9096691500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    9096691500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            146233                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          161216                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          143770                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             290003                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            290003                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.293634                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.914655                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.601508                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.601508                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52148.266729                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52148.266729                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                  120515                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          42939                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       131500                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          174439                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         174439                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1718628500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   5262711000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   6981339500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   6981339500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.293634                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.914655                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.601508                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.601508                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..ea038d4da
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
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+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
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+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
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+
+[system.cpu.fuPool.FUList5.opList07]
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+opClass=SimdMultAcc
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+
+[system.cpu.fuPool.FUList5.opList08]
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+opClass=SimdShift
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+
+[system.cpu.fuPool.FUList5.opList09]
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+opClass=SimdShiftAcc
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+
+[system.cpu.fuPool.FUList5.opList10]
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+
+[system.cpu.fuPool.FUList5.opList11]
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+
+[system.cpu.fuPool.FUList5.opList12]
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+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
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+
+[system.cpu.fuPool.FUList5.opList14]
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+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
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+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
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+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
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+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
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+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..9e435cc97
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:35:02
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 21259532000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
new file mode 100644
index 000000000..472b08431
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
@@ -0,0 +1,158 @@
+
+  SYSTEM TYPE...
+  __ZTC__                := False 
+  __UNIX__               := True 
+  __RISC__               := True 
+  SPEC_CPU2000_LP64        := True 
+  __MAC__                := False 
+  __BCC__                := False 
+  __BORLANDC__           := False 
+  __GUI__                := False 
+  __WTC__                := False 
+  __HP__                 := False 
+
+  CODE OPTIONS...
+  __MACROIZE_HM__        := True 
+  __MACROIZE_MEM__       := True 
+  ENV01                  := True 
+  USE_HPP_STYPE_HDRS     := False 
+  USE_H_STYPE_HDRS       := False 
+
+  CODE INCLUSION PARAMETERS...
+  INCLUDE_ALL_CODE       := False 
+  INCLUDE_DELETE_CODE    := True 
+  __SWAP_GRP_POS__       := True 
+  __INCLUDE_MTRX__       := False 
+  __BAD_CODE__           := False 
+  API_INCLUDE            := False 
+  BE_CAREFUL             := False 
+  OLDWAY                 := False 
+  NOTUSED                := False 
+
+  SYSTEM PARAMETERS...
+  EXT_ENUM               := 999999999L 
+  CHUNK_CONSTANT         := 55555555 
+  CORE_CONSTANT          := 55555555 
+  CORE_LIMIT             := 20971520 
+  CorePage_Size          := 384000 
+  ALIGN_BYTES            := True 
+  CORE_BLOCK_ALIGN       :=    8 
+  FAR_MEM                := False 
+
+  MEMORY MANAGEMENT PARAMETERS...
+  SYSTEM_ALLOC           := True 
+  SYSTEM_FREESTORE       := True 
+  __NO_DISKCACHE__       := False 
+  __FREEZE_VCHUNKS__     := True 
+  __FREEZE_GRP_PACKETS__ := True 
+  __MINIMIZE_TREE_CACHE__:= True 
+
+  SYSTEM STD PARAMETERS...
+  __STDOUT__             := False 
+  NULL                   :=    0 
+  LPTR                   := False 
+  False_Status           :=    1 
+  True_Status            :=    0 
+  LARGE                  := True 
+  TWOBYTE_BOOL           := False 
+  __NOSTR__              := False 
+
+  MEMORY VALIDATION PARAMETERS...
+  CORE_CRC_CHECK         := False 
+  VALIDATE_MEM_CHUNKS    := False 
+
+  SYSTEM DEBUG OPTIONS...
+  DEBUG                  := False 
+  MCSTAT                 := False 
+  TRACKBACK              := False 
+  FLUSH_FILES            := False 
+  DEBUG_CORE0            := False 
+  DEBUG_RISC             := False 
+  __TREE_BUG__           := False 
+  __TRACK_FILE_READS__   := False 
+  PAGE_SPACE             := False 
+  LEAVE_NO_TRACE         := True 
+  NULL_TRACE_STRS        := False 
+
+  TIME PARAMETERS...
+  CLOCK_IS_LONG          := False 
+  __DISPLAY_TIME__       := False 
+  __TREE_TIME__          := False 
+  __DISPLAY_ERRORS__     := False 
+
+  API MACROS...
+  __BMT01__              := True 
+  OPTIMIZE               := True 
+
+  END OF DEFINES.
+
+
+
+              ...   IMPLODE MEMORY ...
+
+  SWAP to DiskCache := False
+
+  FREEZE_GRP_PACKETS:= True
+
+  QueBug            := 1000
+
+  sizeof(boolean)      =  4
+  sizeof(sizetype)     =  4
+  sizeof(chunkstruc)   = 32
+
+  sizeof(shorttype )   =  2
+  sizeof(idtype    )   =  2
+  sizeof(sizetype  )   =  4
+  sizeof(indextype )   =  4
+  sizeof(numtype   )   =  4
+  sizeof(handletype)   =  4
+  sizeof(tokentype )   =  8
+
+  sizeof(short     )   =  2
+  sizeof(int       )   =  4
+
+  sizeof(lt64      )   =  4
+  sizeof(farlongtype)  =  4
+  sizeof(long      )   =  8
+  sizeof(longaddr  )   =  8
+
+  sizeof(float     )   =  4
+  sizeof(double    )   =  8
+
+  sizeof(addrtype  )   =  8
+  sizeof(char *    )   =  8
+ ALLOC   CORE_1    :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @  2030c0
+    DB BlkDirChunk       : Chunk[  10] AT Vbn[3146]
+    DB BlkTknChunk       : Chunk[  11] AT Vbn[3147]
+    DB BlkSizeChunk      : Chunk[  12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+  DB[ 1] LOADED;  Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @   21c40
+    DB BlkDirChunk       : Chunk[  31] AT Vbn[ 81]
+    DB BlkTknChunk       : Chunk[  32] AT Vbn[ 82]
+    DB BlkSizeChunk      : Chunk[  33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+  DB[ 2] LOADED;  Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+    BE HERE NOW !!!
+
+
+
+               ... VORTEx ON LINE ...
+
+
+              ...   END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..9c4b77b7d
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,517 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.021260                       # Number of seconds simulated
+sim_ticks                                 21259532000                       # Number of ticks simulated
+final_tick                                21259532000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 187781                       # Simulator instruction rate (inst/s)
+host_tick_rate                               50157547                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217440                       # Number of bytes of host memory used
+host_seconds                                   423.86                       # Real time elapsed on the host
+sim_insts                                    79591756                       # Number of instructions simulated
+system.physmem.bytes_read                    11229312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 642688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  7713344                       # Number of bytes written to this memory
+system.physmem.num_reads                       175458                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      120521                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      528201279                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  30230581                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     362818147                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     891019426                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     22309038                       # DTB read hits
+system.cpu.dtb.read_misses                     216523                       # DTB read misses
+system.cpu.dtb.read_acv                            41                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22525561                       # DTB read accesses
+system.cpu.dtb.write_hits                    15629688                       # DTB write hits
+system.cpu.dtb.write_misses                     39366                       # DTB write misses
+system.cpu.dtb.write_acv                            9                       # DTB write access violations
+system.cpu.dtb.write_accesses                15669054                       # DTB write accesses
+system.cpu.dtb.data_hits                     37938726                       # DTB hits
+system.cpu.dtb.data_misses                     255889                       # DTB misses
+system.cpu.dtb.data_acv                            50                       # DTB access violations
+system.cpu.dtb.data_accesses                 38194615                       # DTB accesses
+system.cpu.itb.fetch_hits                    13877051                       # ITB hits
+system.cpu.itb.fetch_misses                     28133                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                13905184                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
+system.cpu.numCycles                         42519067                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 16615602                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           10784809                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             464390                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              14543138                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8570194                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1986002                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               35485                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           14905140                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      105779121                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16615602                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           10556196                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      20616414                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2026173                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                4867777                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 5763                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        282637                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  13877051                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                219292                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           42124503                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.511107                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.106328                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 21508089     51.06%     51.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2128231      5.05%     56.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1654689      3.93%     60.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2031982      4.82%     64.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3913911      9.29%     74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1970832      4.68%     78.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   733979      1.74%     80.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1130432      2.68%     83.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7052358     16.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total             42124503                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.390780                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.487804                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15964361                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               4443062                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19692488                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                675645                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1348947                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3728678                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 99733                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              103933078                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                280329                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1348947                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 16452599                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2364451                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          84031                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  19835916                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               2038559                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102562493                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   192                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                   2676                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1925408                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            61709040                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             123636906                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        123159992                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            476914                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  9162159                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5463                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5460                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   4149992                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23138107                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16243401                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1017520                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           376699                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   90712605                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5415                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  88293060                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            101013                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        10834162                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4923026                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            832                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      42124503                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.096002                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.077334                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            13300851     31.58%     31.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7326403     17.39%     48.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5817137     13.81%     62.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4863957     11.55%     74.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4880067     11.58%     85.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2467879      5.86%     91.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1850711      4.39%     96.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1163401      2.76%     98.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              454097      1.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        42124503                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   99927      5.41%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      1      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 762620     41.31%     46.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                983690     53.28%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49334128     55.88%     55.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                44107      0.05%     55.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              126794      0.14%     56.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  90      0.00%     56.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              127284      0.14%     56.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 54      0.00%     56.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               38913      0.04%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22763265     25.78%     82.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            15858425     17.96%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total               88293060                       # Type of FU issued
+system.cpu.iq.rate                           2.076552                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1846238                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.020910                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          220034609                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         101108296                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86316001                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              623265                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             459484                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       302223                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               89827554                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  311744                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1421900                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      2861469                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         4255                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        15998                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1630024                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         1270                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            38                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                1348947                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1395228                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 60292                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100209488                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            330917                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23138107                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16243401                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5415                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  42613                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   717                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          15998                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         305754                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       116766                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               422520                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              87324044                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22528336                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            969016                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                       9491468                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38197877                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15069707                       # Number of branches executed
+system.cpu.iew.exec_stores                   15669541                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.053762                       # Inst execution rate
+system.cpu.iew.wb_sent                       87015038                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      86618224                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  32981280                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  42978824                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       2.037162                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.767384                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       88340672                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts         8835054                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            366565                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     40775556                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.166511                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.804904                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     17645835     43.28%     43.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7080138     17.36%     60.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3592753      8.81%     69.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2169640      5.32%     74.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2013725      4.94%     79.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1230420      3.02%     82.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1128970      2.77%     85.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       727312      1.78%     87.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5186763     12.72%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     40775556                       # Number of insts commited each cycle
+system.cpu.commit.count                      88340672                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       34890015                       # Number of memory references committed
+system.cpu.commit.loads                      20276638                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   13754477                       # Number of branches committed
+system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               5186763                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    131447177                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195703293                       # The number of ROB writes
+system.cpu.timesIdled                           15923                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          394564                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
+system.cpu.cpi                               0.534214                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.534214                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.871907                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.871907                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                115518864                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57354047                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    252314                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   251108                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38108                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
+system.cpu.icache.replacements                  88378                       # number of replacements
+system.cpu.icache.tagsinuse               1927.638696                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 13782143                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  90426                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 152.413498                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            17839872000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1927.638696                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.941230                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               13782143                       # number of ReadReq hits
+system.cpu.icache.demand_hits                13782143                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               13782143                       # number of overall hits
+system.cpu.icache.ReadReq_misses                94908                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 94908                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                94908                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      914028500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       914028500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      914028500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           13877051                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            13877051                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           13877051                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.006839                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.006839                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.006839                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  9630.679184                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  9630.679184                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  9630.679184                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              4481                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               4481                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              4481                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           90427                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            90427                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           90427                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    542589500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    542589500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    542589500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.006516                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.006516                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.006516                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  6000.304113                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  6000.304113                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  6000.304113                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 201340                       # number of replacements
+system.cpu.dcache.tagsinuse               4076.154176                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 34207250                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 205436                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 166.510495                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              157430000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4076.154176                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995155                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               20628725                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              13578476                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               49                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits                34207201                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               34207201                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               257071                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1034901                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1291972                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1291972                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     8273144500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   33900181500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     42173326000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    42173326000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           20885796                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses           49                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            35499173                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           35499173                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.012308                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.070819                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.036394                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.036394                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 32182.332896                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 32756.931822                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 32642.600614                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 32642.600614                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        53500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        27000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                20                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs         2675                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        27000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   161613                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            195029                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           891507                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1086536                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1086536                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           62042                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         143394                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           205436                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          205436                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1278233000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   4733826000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   6012059000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   6012059000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002971                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005787                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005787                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20602.704619                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33012.720197                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 29264.875679                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 29264.875679                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                149119                       # number of replacements
+system.cpu.l2cache.tagsinuse             18923.797261                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  136861                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                174485                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.784371                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3200.297768                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15723.499493                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.097665                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.479843                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                108391                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              161613                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               12014                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 120405                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                120405                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               44050                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            131408                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               175458                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              175458                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1516062500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   4525488500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     6041551000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    6041551000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            152441                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          161613                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          143422                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             295863                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            295863                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.288964                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.916233                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.593038                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.593038                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34416.855846                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34438.455041                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34433.032407                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34433.032407                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                  120521                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          44050                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       131408                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          175458                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         175458                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1367587500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4118168500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   5485756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   5485756000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.288964                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.916233                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.593038                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.593038                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31046.254257                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31338.795964                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31265.351252                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31265.351252                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..d8535707b
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..160c80ddb
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:17
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 44221003000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
new file mode 100644
index 000000000..472b08431
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
@@ -0,0 +1,158 @@
+
+  SYSTEM TYPE...
+  __ZTC__                := False 
+  __UNIX__               := True 
+  __RISC__               := True 
+  SPEC_CPU2000_LP64        := True 
+  __MAC__                := False 
+  __BCC__                := False 
+  __BORLANDC__           := False 
+  __GUI__                := False 
+  __WTC__                := False 
+  __HP__                 := False 
+
+  CODE OPTIONS...
+  __MACROIZE_HM__        := True 
+  __MACROIZE_MEM__       := True 
+  ENV01                  := True 
+  USE_HPP_STYPE_HDRS     := False 
+  USE_H_STYPE_HDRS       := False 
+
+  CODE INCLUSION PARAMETERS...
+  INCLUDE_ALL_CODE       := False 
+  INCLUDE_DELETE_CODE    := True 
+  __SWAP_GRP_POS__       := True 
+  __INCLUDE_MTRX__       := False 
+  __BAD_CODE__           := False 
+  API_INCLUDE            := False 
+  BE_CAREFUL             := False 
+  OLDWAY                 := False 
+  NOTUSED                := False 
+
+  SYSTEM PARAMETERS...
+  EXT_ENUM               := 999999999L 
+  CHUNK_CONSTANT         := 55555555 
+  CORE_CONSTANT          := 55555555 
+  CORE_LIMIT             := 20971520 
+  CorePage_Size          := 384000 
+  ALIGN_BYTES            := True 
+  CORE_BLOCK_ALIGN       :=    8 
+  FAR_MEM                := False 
+
+  MEMORY MANAGEMENT PARAMETERS...
+  SYSTEM_ALLOC           := True 
+  SYSTEM_FREESTORE       := True 
+  __NO_DISKCACHE__       := False 
+  __FREEZE_VCHUNKS__     := True 
+  __FREEZE_GRP_PACKETS__ := True 
+  __MINIMIZE_TREE_CACHE__:= True 
+
+  SYSTEM STD PARAMETERS...
+  __STDOUT__             := False 
+  NULL                   :=    0 
+  LPTR                   := False 
+  False_Status           :=    1 
+  True_Status            :=    0 
+  LARGE                  := True 
+  TWOBYTE_BOOL           := False 
+  __NOSTR__              := False 
+
+  MEMORY VALIDATION PARAMETERS...
+  CORE_CRC_CHECK         := False 
+  VALIDATE_MEM_CHUNKS    := False 
+
+  SYSTEM DEBUG OPTIONS...
+  DEBUG                  := False 
+  MCSTAT                 := False 
+  TRACKBACK              := False 
+  FLUSH_FILES            := False 
+  DEBUG_CORE0            := False 
+  DEBUG_RISC             := False 
+  __TREE_BUG__           := False 
+  __TRACK_FILE_READS__   := False 
+  PAGE_SPACE             := False 
+  LEAVE_NO_TRACE         := True 
+  NULL_TRACE_STRS        := False 
+
+  TIME PARAMETERS...
+  CLOCK_IS_LONG          := False 
+  __DISPLAY_TIME__       := False 
+  __TREE_TIME__          := False 
+  __DISPLAY_ERRORS__     := False 
+
+  API MACROS...
+  __BMT01__              := True 
+  OPTIMIZE               := True 
+
+  END OF DEFINES.
+
+
+
+              ...   IMPLODE MEMORY ...
+
+  SWAP to DiskCache := False
+
+  FREEZE_GRP_PACKETS:= True
+
+  QueBug            := 1000
+
+  sizeof(boolean)      =  4
+  sizeof(sizetype)     =  4
+  sizeof(chunkstruc)   = 32
+
+  sizeof(shorttype )   =  2
+  sizeof(idtype    )   =  2
+  sizeof(sizetype  )   =  4
+  sizeof(indextype )   =  4
+  sizeof(numtype   )   =  4
+  sizeof(handletype)   =  4
+  sizeof(tokentype )   =  8
+
+  sizeof(short     )   =  2
+  sizeof(int       )   =  4
+
+  sizeof(lt64      )   =  4
+  sizeof(farlongtype)  =  4
+  sizeof(long      )   =  8
+  sizeof(longaddr  )   =  8
+
+  sizeof(float     )   =  4
+  sizeof(double    )   =  8
+
+  sizeof(addrtype  )   =  8
+  sizeof(char *    )   =  8
+ ALLOC   CORE_1    :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @  2030c0
+    DB BlkDirChunk       : Chunk[  10] AT Vbn[3146]
+    DB BlkTknChunk       : Chunk[  11] AT Vbn[3147]
+    DB BlkSizeChunk      : Chunk[  12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+  DB[ 1] LOADED;  Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @   21c40
+    DB BlkDirChunk       : Chunk[  31] AT Vbn[ 81]
+    DB BlkTknChunk       : Chunk[  32] AT Vbn[ 82]
+    DB BlkSizeChunk      : Chunk[  33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+  DB[ 2] LOADED;  Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+    BE HERE NOW !!!
+
+
+
+               ... VORTEx ON LINE ...
+
+
+              ...   END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..4fc91e266
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.044221                       # Number of seconds simulated
+sim_ticks                                 44221003000                       # Number of ticks simulated
+final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3998504                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2001543652                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 206876                       # Number of bytes of host memory used
+host_seconds                                    22.09                       # Real time elapsed on the host
+sim_insts                                    88340673                       # Number of instructions simulated
+system.physmem.bytes_read                   480454939                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              353752292                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 91652896                       # Number of bytes written to this memory
+system.physmem.num_reads                    108714711                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    14613377                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10864858470                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999644241                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    2072610067                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   12937468537                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     20276638                       # DTB read hits
+system.cpu.dtb.read_misses                      90148                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 20366786                       # DTB read accesses
+system.cpu.dtb.write_hits                    14613377                       # DTB write hits
+system.cpu.dtb.write_misses                      7252                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                14620629                       # DTB write accesses
+system.cpu.dtb.data_hits                     34890015                       # DTB hits
+system.cpu.dtb.data_misses                      97400                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
+system.cpu.itb.fetch_hits                    88438073                       # ITB hits
+system.cpu.itb.fetch_misses                      3934                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                88442007                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
+system.cpu.numCycles                         88442007                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         88340673                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
+system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8920848                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     78039444                       # number of integer instructions
+system.cpu.num_fp_insts                        267757                       # number of float instructions
+system.cpu.num_int_register_reads           105931758                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           52319251                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               229023                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              227630                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      34987415                       # number of memory refs
+system.cpu.num_load_insts                    20366786                       # Number of load instructions
+system.cpu.num_store_insts                   14620629                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                   88442007                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..f99b5fb55
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..e74b48d2a
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 134276988000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
new file mode 100644
index 000000000..472b08431
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
@@ -0,0 +1,158 @@
+
+  SYSTEM TYPE...
+  __ZTC__                := False 
+  __UNIX__               := True 
+  __RISC__               := True 
+  SPEC_CPU2000_LP64        := True 
+  __MAC__                := False 
+  __BCC__                := False 
+  __BORLANDC__           := False 
+  __GUI__                := False 
+  __WTC__                := False 
+  __HP__                 := False 
+
+  CODE OPTIONS...
+  __MACROIZE_HM__        := True 
+  __MACROIZE_MEM__       := True 
+  ENV01                  := True 
+  USE_HPP_STYPE_HDRS     := False 
+  USE_H_STYPE_HDRS       := False 
+
+  CODE INCLUSION PARAMETERS...
+  INCLUDE_ALL_CODE       := False 
+  INCLUDE_DELETE_CODE    := True 
+  __SWAP_GRP_POS__       := True 
+  __INCLUDE_MTRX__       := False 
+  __BAD_CODE__           := False 
+  API_INCLUDE            := False 
+  BE_CAREFUL             := False 
+  OLDWAY                 := False 
+  NOTUSED                := False 
+
+  SYSTEM PARAMETERS...
+  EXT_ENUM               := 999999999L 
+  CHUNK_CONSTANT         := 55555555 
+  CORE_CONSTANT          := 55555555 
+  CORE_LIMIT             := 20971520 
+  CorePage_Size          := 384000 
+  ALIGN_BYTES            := True 
+  CORE_BLOCK_ALIGN       :=    8 
+  FAR_MEM                := False 
+
+  MEMORY MANAGEMENT PARAMETERS...
+  SYSTEM_ALLOC           := True 
+  SYSTEM_FREESTORE       := True 
+  __NO_DISKCACHE__       := False 
+  __FREEZE_VCHUNKS__     := True 
+  __FREEZE_GRP_PACKETS__ := True 
+  __MINIMIZE_TREE_CACHE__:= True 
+
+  SYSTEM STD PARAMETERS...
+  __STDOUT__             := False 
+  NULL                   :=    0 
+  LPTR                   := False 
+  False_Status           :=    1 
+  True_Status            :=    0 
+  LARGE                  := True 
+  TWOBYTE_BOOL           := False 
+  __NOSTR__              := False 
+
+  MEMORY VALIDATION PARAMETERS...
+  CORE_CRC_CHECK         := False 
+  VALIDATE_MEM_CHUNKS    := False 
+
+  SYSTEM DEBUG OPTIONS...
+  DEBUG                  := False 
+  MCSTAT                 := False 
+  TRACKBACK              := False 
+  FLUSH_FILES            := False 
+  DEBUG_CORE0            := False 
+  DEBUG_RISC             := False 
+  __TREE_BUG__           := False 
+  __TRACK_FILE_READS__   := False 
+  PAGE_SPACE             := False 
+  LEAVE_NO_TRACE         := True 
+  NULL_TRACE_STRS        := False 
+
+  TIME PARAMETERS...
+  CLOCK_IS_LONG          := False 
+  __DISPLAY_TIME__       := False 
+  __TREE_TIME__          := False 
+  __DISPLAY_ERRORS__     := False 
+
+  API MACROS...
+  __BMT01__              := True 
+  OPTIMIZE               := True 
+
+  END OF DEFINES.
+
+
+
+              ...   IMPLODE MEMORY ...
+
+  SWAP to DiskCache := False
+
+  FREEZE_GRP_PACKETS:= True
+
+  QueBug            := 1000
+
+  sizeof(boolean)      =  4
+  sizeof(sizetype)     =  4
+  sizeof(chunkstruc)   = 32
+
+  sizeof(shorttype )   =  2
+  sizeof(idtype    )   =  2
+  sizeof(sizetype  )   =  4
+  sizeof(indextype )   =  4
+  sizeof(numtype   )   =  4
+  sizeof(handletype)   =  4
+  sizeof(tokentype )   =  8
+
+  sizeof(short     )   =  2
+  sizeof(int       )   =  4
+
+  sizeof(lt64      )   =  4
+  sizeof(farlongtype)  =  4
+  sizeof(long      )   =  8
+  sizeof(longaddr  )   =  8
+
+  sizeof(float     )   =  4
+  sizeof(double    )   =  8
+
+  sizeof(addrtype  )   =  8
+  sizeof(char *    )   =  8
+ ALLOC   CORE_1    :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @  2030c0
+    DB BlkDirChunk       : Chunk[  10] AT Vbn[3146]
+    DB BlkTknChunk       : Chunk[  11] AT Vbn[3147]
+    DB BlkSizeChunk      : Chunk[  12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+  DB[ 1] LOADED;  Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @   21c40
+    DB BlkDirChunk       : Chunk[  31] AT Vbn[ 81]
+    DB BlkTknChunk       : Chunk[  32] AT Vbn[ 82]
+    DB BlkSizeChunk      : Chunk[  33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+  DB[ 2] LOADED;  Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+    BE HERE NOW !!!
+
+
+
+               ... VORTEx ON LINE ...
+
+
+              ...   END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..59b869a9f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,266 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.134277                       # Number of seconds simulated
+sim_ticks                                134276988000                       # Number of ticks simulated
+final_tick                               134276988000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1801981                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2738992827                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215584                       # Number of bytes of host memory used
+host_seconds                                    49.02                       # Real time elapsed on the host
+sim_insts                                    88340673                       # Number of instructions simulated
+system.physmem.bytes_read                    11121920                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 558272                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  7712384                       # Number of bytes written to this memory
+system.physmem.num_reads                       173780                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      120506                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       82828191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   4157615                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      57436379                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     140264570                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     20276638                       # DTB read hits
+system.cpu.dtb.read_misses                      90148                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 20366786                       # DTB read accesses
+system.cpu.dtb.write_hits                    14613377                       # DTB write hits
+system.cpu.dtb.write_misses                      7252                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                14620629                       # DTB write accesses
+system.cpu.dtb.data_hits                     34890015                       # DTB hits
+system.cpu.dtb.data_misses                      97400                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
+system.cpu.itb.fetch_hits                    88438074                       # ITB hits
+system.cpu.itb.fetch_misses                      3934                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                88442008                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
+system.cpu.numCycles                        268553976                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         88340673                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
+system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8920848                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     78039444                       # number of integer instructions
+system.cpu.num_fp_insts                        267757                       # number of float instructions
+system.cpu.num_int_register_reads           105931758                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           52319251                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               229023                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              227630                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      34987415                       # number of memory refs
+system.cpu.num_load_insts                    20366786                       # Number of load instructions
+system.cpu.num_store_insts                   14620629                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  268553976                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                  74391                       # number of replacements
+system.cpu.icache.tagsinuse               1871.404551                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 88361638                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  76436                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                1156.021220                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1871.404551                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.913772                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               88361638                       # number of ReadReq hits
+system.cpu.icache.demand_hits                88361638                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               88361638                       # number of overall hits
+system.cpu.icache.ReadReq_misses                76436                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 76436                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                76436                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     1436470000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      1436470000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     1436470000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           88438074                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            88438074                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           88438074                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000864                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000864                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000864                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 18793.107960                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 18793.107960                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 18793.107960                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           76436                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            76436                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           76436                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency   1207162000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   1207162000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   1207162000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000864                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000864                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000864                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 200248                       # number of replacements
+system.cpu.dcache.tagsinuse               4078.858373                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 34685671                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 169.741568                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              943232000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4078.858373                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995815                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               20215872                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              14469799                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                34685671                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               34685671                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                60766                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              143578                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                204344                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               204344                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     2261000000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    7532210000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency      9793210000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     9793210000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002997                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.009825                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.005857                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.005857                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 47925.116470                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 47925.116470                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   161222                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           60766                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         143578                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           204344                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          204344                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   2078702000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   7101476000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   9180178000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   9180178000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009825                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005857                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005857                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                147405                       # number of replacements
+system.cpu.l2cache.tagsinuse             18614.813333                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  122958                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                172748                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.711777                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2806.549776                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15808.263557                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.085649                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.482430                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 94901                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              161222                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               12099                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 107000                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                107000                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               42301                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            131479                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               173780                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              173780                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    2199652000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   6836908000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     9036560000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    9036560000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            137202                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          161222                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          143578                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             280780                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            280780                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.308312                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.915732                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.618919                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.618919                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                  120506                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          42301                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       131479                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          173780                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         173780                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1692040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   5259160000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   6951200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   6951200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.308312                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.915732                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.618919                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.618919                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..1feff9641
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..41153b9d0
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:34:51
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 31183407000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..858b9d08f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,544 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.031183                       # Number of seconds simulated
+sim_ticks                                 31183407000                       # Number of ticks simulated
+final_tick                                31183407000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 157932                       # Simulator instruction rate (inst/s)
+host_tick_rate                               48938242                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229072                       # Number of bytes of host memory used
+host_seconds                                   637.20                       # Real time elapsed on the host
+sim_insts                                   100634165                       # Number of instructions simulated
+system.physmem.bytes_read                     8651648                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 350016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  5661184                       # Number of bytes written to this memory
+system.physmem.num_reads                       135182                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       88456                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      277443962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                  11224431                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     181544756                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     458988718                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.numCycles                         62366815                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 17631068                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           11525225                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             822451                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              15041021                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  9743390                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1887340                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              176888                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           12968459                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       88523933                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17631068                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11630730                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22984896                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2898005                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               23107334                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   15                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           525                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  12208408                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                230644                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           61059715                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.021356                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.077680                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 38090584     62.38%     62.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2437224      3.99%     66.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2605062      4.27%     70.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2470326      4.05%     74.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1717744      2.81%     77.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1704134      2.79%     80.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1004081      1.64%     81.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1295541      2.12%     84.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9735019     15.94%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total             61059715                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.282700                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.419408                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 14872380                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              21838408                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  21376813                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1070090                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1902024                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3467429                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 98061                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              120316029                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                332599                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1902024                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 16801594                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2005674                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       15516104                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20489827                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4344492                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              117017437                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     7                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                   3607                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2996198                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               60                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           118959985                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             538237718                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        538236225                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              1493                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              99144333                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 19815652                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             778147                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         778546                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12135199                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29749057                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            22305499                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2463618                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          3436887                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  111737256                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              774255                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 107616850                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            306406                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11658627                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     29328565                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          71223                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      61059715                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.762485                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.902924                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            22160160     36.29%     36.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            11614525     19.02%     55.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8577298     14.05%     69.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7396039     12.11%     81.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4782616      7.83%     89.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3521695      5.77%     95.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1664317      2.73%     97.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              809749      1.33%     99.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              533316      0.87%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        61059715                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   88066      3.33%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1488278     56.33%     59.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1065734     40.34%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              57002654     52.97%     52.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                87399      0.08%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  39      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             28992824     26.94%     79.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21533927     20.01%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              107616850                       # Type of FU issued
+system.cpu.iq.rate                           1.725547                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2642078                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.024551                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          279241693                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         124185257                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    105412682                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 206                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                204                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           76                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              110258821                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     107                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1870348                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      2440492                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3482                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        15956                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1748305                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads           52                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            53                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                1902024                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  953128                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 28578                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           112587966                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            618611                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29749057                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             22305499                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             756996                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1135                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  1192                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          15956                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         682416                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       198748                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               881164                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             106274273                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              28622040                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1342577                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         76455                       # number of nop insts executed
+system.cpu.iew.exec_refs                     49853649                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14601408                       # Number of branches executed
+system.cpu.iew.exec_stores                   21231609                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.704020                       # Inst execution rate
+system.cpu.iew.wb_sent                      105725224                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     105412758                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  52507879                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 101154765                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.690206                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.519085                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      100639717                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        11948697                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          703032                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            788200                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     59157692                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.701211                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.430896                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     26246617     44.37%     44.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14635662     24.74%     69.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4223894      7.14%     76.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3641491      6.16%     82.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2268632      3.83%     86.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1889350      3.19%     89.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       703853      1.19%     90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       498146      0.84%     91.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5050047      8.54%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     59157692                       # Number of insts commited each cycle
+system.cpu.commit.count                     100639717                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       47865759                       # Number of memory references committed
+system.cpu.commit.loads                      27308565                       # Number of loads committed
+system.cpu.commit.membars                       15920                       # Number of memory barriers committed
+system.cpu.commit.branches                   13670084                       # Number of branches committed
+system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  91478611                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               5050047                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    166670760                       # The number of ROB reads
+system.cpu.rob.rob_writes                   227084538                       # The number of ROB writes
+system.cpu.timesIdled                           61622                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1307100                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   100634165                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             100634165                       # Number of Instructions Simulated
+system.cpu.cpi                               0.619738                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.619738                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.613585                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.613585                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                511657086                       # number of integer regfile reads
+system.cpu.int_regfile_writes               103892124                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       166                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      126                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               146210782                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  34752                       # number of misc regfile writes
+system.cpu.icache.replacements                  26083                       # number of replacements
+system.cpu.icache.tagsinuse               1805.405384                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12179175                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  28115                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 433.191357                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1805.405384                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.881546                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               12179178                       # number of ReadReq hits
+system.cpu.icache.demand_hits                12179178                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               12179178                       # number of overall hits
+system.cpu.icache.ReadReq_misses                29230                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 29230                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                29230                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      357885000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       357885000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      357885000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           12208408                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            12208408                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           12208408                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.002394                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.002394                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.002394                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 12243.756415                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 12243.756415                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 12243.756415                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        1                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1069                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1069                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1069                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           28161                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            28161                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           28161                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    246973000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    246973000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    246973000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.002307                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.002307                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.002307                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  8770.036575                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  8770.036575                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  8770.036575                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 157879                       # number of replacements
+system.cpu.dcache.tagsinuse               4072.329363                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 44742203                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 161975                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 276.229066                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              306596000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4072.329363                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994221                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               26395464                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              18310275                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            18919                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             17375                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                44705739                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               44705739                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               108834                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1539626                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses             27                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               1648460                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1648460                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     2418698500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   52283649500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       386000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     54702348000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    54702348000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           26504298                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        18946                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         17375                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            46354199                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           46354199                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.004106                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.077563                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.001425                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.035562                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.035562                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 22223.739824                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33958.668859                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 14296.296296                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 33183.909831                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 33183.909831                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       190500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              10                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        19050                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   123472                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             53734                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1432703                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits           27                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1486437                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1486437                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           55100                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         106923                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           162023                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          162023                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1035726000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3662471000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4698197000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4698197000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002079                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005387                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.003495                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.003495                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18797.205082                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.350542                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 28997.099177                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 28997.099177                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                114920                       # number of replacements
+system.cpu.l2cache.tagsinuse             18304.700184                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   72415                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                133774                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.541323                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2370.650310                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15934.049874                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.072347                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.486269                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 50510                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              123473                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits                 16                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits                4309                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  54819                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 54819                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32664                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses               31                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            102598                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               135262                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              135262                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1118309000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3526121000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4644430000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4644430000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             83174                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          123473                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses             47                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          106907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             190081                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            190081                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.392719                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.659574                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.959694                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.711602                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.711602                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34236.743816                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.321020                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34336.546850                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34336.546850                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   88456                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               80                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                80                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               80                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          32584                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses           31                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       102598                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          135182                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         135182                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1012754000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       962000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   3197891500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   4210645500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   4210645500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.391757                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.659574                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.959694                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.711181                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.711181                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.328259                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31032.258065                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.140724                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31147.974582                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31147.974582                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..321a621c1
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..cba7edc9e
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:35:25
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 53932162000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..550377594
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.053932                       # Number of seconds simulated
+sim_ticks                                 53932162000                       # Number of ticks simulated
+final_tick                                53932162000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3016681                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1616735818                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217624                       # Number of bytes of host memory used
+host_seconds                                    33.36                       # Real time elapsed on the host
+sim_insts                                   100632437                       # Number of instructions simulated
+system.physmem.bytes_read                   419153654                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              312580308                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 78660211                       # Number of bytes written to this memory
+system.physmem.num_reads                    105301330                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    19865820                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     7771868185                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                5795805256                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1458502832                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9230371017                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.numCycles                        107864325                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        100632437                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
+system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8920660                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     91472788                       # number of integer instructions
+system.cpu.num_fp_insts                            56                       # number of float instructions
+system.cpu.num_int_register_reads           452177233                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           96252298                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      47862848                       # number of memory refs
+system.cpu.num_load_insts                    27307109                       # Number of load instructions
+system.cpu.num_store_insts                   20555739                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  107864325                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..62eb4cdbf
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..4fb750502
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:06
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 133117442000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..2fff6cef5
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.133117                       # Number of seconds simulated
+sim_ticks                                133117442000                       # Number of ticks simulated
+final_tick                               133117442000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1410680                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1881780580                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226592                       # Number of bytes of host memory used
+host_seconds                                    70.74                       # Real time elapsed on the host
+sim_insts                                    99791663                       # Number of instructions simulated
+system.physmem.bytes_read                     8570688                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 294208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  5660736                       # Number of bytes written to this memory
+system.physmem.num_reads                       133917                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       88449                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       64384410                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   2210139                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      42524375                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     106908785                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.numCycles                        266234884                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         99791663                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
+system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8920660                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     91472788                       # number of integer instructions
+system.cpu.num_fp_insts                            56                       # number of float instructions
+system.cpu.num_int_register_reads           533542913                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           96252298                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      47862848                       # number of memory refs
+system.cpu.num_load_insts                    27307109                       # Number of load instructions
+system.cpu.num_store_insts                   20555739                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  266234884                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                  16890                       # number of replacements
+system.cpu.icache.tagsinuse               1736.182852                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 78126170                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                4131.910831                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1736.182852                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.847746                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               78126170                       # number of ReadReq hits
+system.cpu.icache.demand_hits                78126170                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               78126170                       # number of overall hits
+system.cpu.icache.ReadReq_misses                18908                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 18908                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                18908                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      457786000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       457786000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      457786000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           78145078                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            78145078                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           78145078                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000242                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000242                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000242                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 24211.233340                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 24211.233340                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           18908                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            18908                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           18908                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    401062000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    401062000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    401062000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000242                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000242                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000242                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 155902                       # number of replacements
+system.cpu.dcache.tagsinuse               4076.934010                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 46862075                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 159998                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 292.891630                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             1079641000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4076.934010                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995345                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               27087368                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              19742869                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            15919                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             15919                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                46830237                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               46830237                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                52966                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              107032                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                159998                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               159998                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     1862630000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    5808782000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency      7671412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     7671412000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           27140334                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            46990235                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           46990235                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001952                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.005392                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.003405                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.003405                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 47946.924337                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 47946.924337                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   122808                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           52966                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         107032                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           159998                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          159998                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1703732000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5487686000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   7191418000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   7191418000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001952                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.003405                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.003405                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                113660                       # number of replacements
+system.cpu.l2cache.tagsinuse             18191.621028                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   61800                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                132489                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.466454                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2165.921088                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16025.699940                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.066099                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.489066                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 40584                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              122808                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                4405                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  44989                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 44989                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               31290                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            102627                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               133917                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              133917                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1627080000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   5336604000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     6963684000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    6963684000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             71874                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          122808                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          107032                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             178906                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            178906                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.435345                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.958844                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.748533                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.748533                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   88449                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          31290                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       102627                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          133917                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         133917                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1251600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4105080000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   5356680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   5356680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.435345                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958844                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.748533                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.748533                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..2df6b792d
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex bendian.raw
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
new file mode 100755
index 000000000..bb51748c6
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
@@ -0,0 +1,563 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall time(4026528248, 4026527848, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
new file mode 100755
index 000000000..542479326
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:20
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 68148678500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
new file mode 100644
index 000000000..0ac2d9980
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
@@ -0,0 +1,158 @@
+
+  SYSTEM TYPE...
+  __ZTC__                := False 
+  __UNIX__               := True 
+  __RISC__               := True 
+  SPEC_CPU2000_LP64        := False 
+  __MAC__                := False 
+  __BCC__                := False 
+  __BORLANDC__           := False 
+  __GUI__                := False 
+  __WTC__                := False 
+  __HP__                 := False 
+
+  CODE OPTIONS...
+  __MACROIZE_HM__        := True 
+  __MACROIZE_MEM__       := True 
+  ENV01                  := True 
+  USE_HPP_STYPE_HDRS     := False 
+  USE_H_STYPE_HDRS       := False 
+
+  CODE INCLUSION PARAMETERS...
+  INCLUDE_ALL_CODE       := False 
+  INCLUDE_DELETE_CODE    := True 
+  __SWAP_GRP_POS__       := True 
+  __INCLUDE_MTRX__       := False 
+  __BAD_CODE__           := False 
+  API_INCLUDE            := False 
+  BE_CAREFUL             := False 
+  OLDWAY                 := False 
+  NOTUSED                := False 
+
+  SYSTEM PARAMETERS...
+  EXT_ENUM               := 999999999L 
+  CHUNK_CONSTANT         := 55555555 
+  CORE_CONSTANT          := 55555555 
+  CORE_LIMIT             := 20971520 
+  CorePage_Size          := 384000 
+  ALIGN_BYTES            := True 
+  CORE_BLOCK_ALIGN       :=    8 
+  FAR_MEM                := False 
+
+  MEMORY MANAGEMENT PARAMETERS...
+  SYSTEM_ALLOC           := True 
+  SYSTEM_FREESTORE       := True 
+  __NO_DISKCACHE__       := False 
+  __FREEZE_VCHUNKS__     := True 
+  __FREEZE_GRP_PACKETS__ := True 
+  __MINIMIZE_TREE_CACHE__:= True 
+
+  SYSTEM STD PARAMETERS...
+  __STDOUT__             := False 
+  NULL                   :=    0 
+  LPTR                   := False 
+  False_Status           :=    1 
+  True_Status            :=    0 
+  LARGE                  := True 
+  TWOBYTE_BOOL           := False 
+  __NOSTR__              := False 
+
+  MEMORY VALIDATION PARAMETERS...
+  CORE_CRC_CHECK         := False 
+  VALIDATE_MEM_CHUNKS    := False 
+
+  SYSTEM DEBUG OPTIONS...
+  DEBUG                  := False 
+  MCSTAT                 := False 
+  TRACKBACK              := False 
+  FLUSH_FILES            := False 
+  DEBUG_CORE0            := False 
+  DEBUG_RISC             := False 
+  __TREE_BUG__           := False 
+  __TRACK_FILE_READS__   := False 
+  PAGE_SPACE             := False 
+  LEAVE_NO_TRACE         := True 
+  NULL_TRACE_STRS        := False 
+
+  TIME PARAMETERS...
+  CLOCK_IS_LONG          := False 
+  __DISPLAY_TIME__       := False 
+  __TREE_TIME__          := False 
+  __DISPLAY_ERRORS__     := False 
+
+  API MACROS...
+  __BMT01__              := True 
+  OPTIMIZE               := True 
+
+  END OF DEFINES.
+
+
+
+              ...   IMPLODE MEMORY ...
+
+  SWAP to DiskCache := False
+
+  FREEZE_GRP_PACKETS:= True
+
+  QueBug            := 1000
+
+  sizeof(boolean)      =  4
+  sizeof(sizetype)     =  4
+  sizeof(chunkstruc)   = 32
+
+  sizeof(shorttype )   =  2
+  sizeof(idtype    )   =  2
+  sizeof(sizetype  )   =  4
+  sizeof(indextype )   =  4
+  sizeof(numtype   )   =  4
+  sizeof(handletype)   =  4
+  sizeof(tokentype )   =  8
+
+  sizeof(short     )   =  2
+  sizeof(int       )   =  4
+
+  sizeof(lt64      )   =  4
+  sizeof(farlongtype)  =  4
+  sizeof(long      )   =  4
+  sizeof(longaddr  )   =  4
+
+  sizeof(float     )   =  4
+  sizeof(double    )   =  8
+
+  sizeof(addrtype  )   =  4
+  sizeof(char *    )   =  4
+ ALLOC   CORE_1    :: 8
+ BHOOLE NATH
+
+ OPEN File ./input/bendian.rnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @  2030c0
+    DB BlkDirChunk       : Chunk[  10] AT Vbn[3146]
+    DB BlkTknChunk       : Chunk[  11] AT Vbn[3147]
+    DB BlkSizeChunk      : Chunk[  12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+  DB[ 1] LOADED;  Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 1b4750
+
+ OPEN File ./input/bendian.wnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @   21c40
+    DB BlkDirChunk       : Chunk[  31] AT Vbn[ 81]
+    DB BlkTknChunk       : Chunk[  32] AT Vbn[ 82]
+    DB BlkSizeChunk      : Chunk[  33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+  DB[ 2] LOADED;  Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+    BE HERE NOW !!!
+
+
+
+               ... VORTEx ON LINE ...
+
+
+              ...   END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..dc6c31998
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.068149                       # Number of seconds simulated
+sim_ticks                                 68148678500                       # Number of ticks simulated
+final_tick                                68148678500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3420916                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1712444497                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214012                       # Number of bytes of host memory used
+host_seconds                                    39.80                       # Real time elapsed on the host
+sim_insts                                   136139203                       # Number of instructions simulated
+system.physmem.bytes_read                   685773693                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              538214332                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 89882950                       # Number of bytes written to this memory
+system.physmem.num_reads                    171784884                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    20864304                       # Number of write requests responded to by this memory
+system.physmem.num_other                        15916                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10062905226                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7897648844                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1318924328                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11381829554                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.numCycles                        136297358                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        136139203                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
+system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8898970                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    115187758                       # number of integer instructions
+system.cpu.num_fp_insts                       2326977                       # number of float instructions
+system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          113147747                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      58160249                       # number of memory refs
+system.cpu.num_load_insts                    37275868                       # Number of load instructions
+system.cpu.num_store_insts                   20884381                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  136297358                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
new file mode 100644
index 000000000..5e34ae7a1
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex bendian.raw
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
new file mode 100755
index 000000000..bb51748c6
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
@@ -0,0 +1,563 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall time(4026528248, 4026527848, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
new file mode 100755
index 000000000..787eaa97a
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:48
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 202941992000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
new file mode 100644
index 000000000..0ac2d9980
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
@@ -0,0 +1,158 @@
+
+  SYSTEM TYPE...
+  __ZTC__                := False 
+  __UNIX__               := True 
+  __RISC__               := True 
+  SPEC_CPU2000_LP64        := False 
+  __MAC__                := False 
+  __BCC__                := False 
+  __BORLANDC__           := False 
+  __GUI__                := False 
+  __WTC__                := False 
+  __HP__                 := False 
+
+  CODE OPTIONS...
+  __MACROIZE_HM__        := True 
+  __MACROIZE_MEM__       := True 
+  ENV01                  := True 
+  USE_HPP_STYPE_HDRS     := False 
+  USE_H_STYPE_HDRS       := False 
+
+  CODE INCLUSION PARAMETERS...
+  INCLUDE_ALL_CODE       := False 
+  INCLUDE_DELETE_CODE    := True 
+  __SWAP_GRP_POS__       := True 
+  __INCLUDE_MTRX__       := False 
+  __BAD_CODE__           := False 
+  API_INCLUDE            := False 
+  BE_CAREFUL             := False 
+  OLDWAY                 := False 
+  NOTUSED                := False 
+
+  SYSTEM PARAMETERS...
+  EXT_ENUM               := 999999999L 
+  CHUNK_CONSTANT         := 55555555 
+  CORE_CONSTANT          := 55555555 
+  CORE_LIMIT             := 20971520 
+  CorePage_Size          := 384000 
+  ALIGN_BYTES            := True 
+  CORE_BLOCK_ALIGN       :=    8 
+  FAR_MEM                := False 
+
+  MEMORY MANAGEMENT PARAMETERS...
+  SYSTEM_ALLOC           := True 
+  SYSTEM_FREESTORE       := True 
+  __NO_DISKCACHE__       := False 
+  __FREEZE_VCHUNKS__     := True 
+  __FREEZE_GRP_PACKETS__ := True 
+  __MINIMIZE_TREE_CACHE__:= True 
+
+  SYSTEM STD PARAMETERS...
+  __STDOUT__             := False 
+  NULL                   :=    0 
+  LPTR                   := False 
+  False_Status           :=    1 
+  True_Status            :=    0 
+  LARGE                  := True 
+  TWOBYTE_BOOL           := False 
+  __NOSTR__              := False 
+
+  MEMORY VALIDATION PARAMETERS...
+  CORE_CRC_CHECK         := False 
+  VALIDATE_MEM_CHUNKS    := False 
+
+  SYSTEM DEBUG OPTIONS...
+  DEBUG                  := False 
+  MCSTAT                 := False 
+  TRACKBACK              := False 
+  FLUSH_FILES            := False 
+  DEBUG_CORE0            := False 
+  DEBUG_RISC             := False 
+  __TREE_BUG__           := False 
+  __TRACK_FILE_READS__   := False 
+  PAGE_SPACE             := False 
+  LEAVE_NO_TRACE         := True 
+  NULL_TRACE_STRS        := False 
+
+  TIME PARAMETERS...
+  CLOCK_IS_LONG          := False 
+  __DISPLAY_TIME__       := False 
+  __TREE_TIME__          := False 
+  __DISPLAY_ERRORS__     := False 
+
+  API MACROS...
+  __BMT01__              := True 
+  OPTIMIZE               := True 
+
+  END OF DEFINES.
+
+
+
+              ...   IMPLODE MEMORY ...
+
+  SWAP to DiskCache := False
+
+  FREEZE_GRP_PACKETS:= True
+
+  QueBug            := 1000
+
+  sizeof(boolean)      =  4
+  sizeof(sizetype)     =  4
+  sizeof(chunkstruc)   = 32
+
+  sizeof(shorttype )   =  2
+  sizeof(idtype    )   =  2
+  sizeof(sizetype  )   =  4
+  sizeof(indextype )   =  4
+  sizeof(numtype   )   =  4
+  sizeof(handletype)   =  4
+  sizeof(tokentype )   =  8
+
+  sizeof(short     )   =  2
+  sizeof(int       )   =  4
+
+  sizeof(lt64      )   =  4
+  sizeof(farlongtype)  =  4
+  sizeof(long      )   =  4
+  sizeof(longaddr  )   =  4
+
+  sizeof(float     )   =  4
+  sizeof(double    )   =  8
+
+  sizeof(addrtype  )   =  4
+  sizeof(char *    )   =  4
+ ALLOC   CORE_1    :: 8
+ BHOOLE NATH
+
+ OPEN File ./input/bendian.rnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @  2030c0
+    DB BlkDirChunk       : Chunk[  10] AT Vbn[3146]
+    DB BlkTknChunk       : Chunk[  11] AT Vbn[3147]
+    DB BlkSizeChunk      : Chunk[  12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+  DB[ 1] LOADED;  Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 1b4750
+
+ OPEN File ./input/bendian.wnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @   21c40
+    DB BlkDirChunk       : Chunk[  31] AT Vbn[ 81]
+    DB BlkTknChunk       : Chunk[  32] AT Vbn[ 82]
+    DB BlkSizeChunk      : Chunk[  33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+  DB[ 2] LOADED;  Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+    BE HERE NOW !!!
+
+
+
+               ... VORTEx ON LINE ...
+
+
+              ...   END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ 	MESSAGE       FileName:	 smred.msg            
+	OUTPUT        FileName:	 smred.out            
+	DISK CACHE    FileName:	 NULL                 
+	PART DB       FileName:	 parts.db             
+	DRAW DB       FileName:	 draw.db              
+	PERSON DB     FileName:	 emp.db               
+	PERSONS Data  FileName:	 ./input/persons.250  
+	PARTS         Count   :	 100     
+	OUTER         Loops   :	 1       
+	INNER         Loops   :	 1       
+	LOOKUP        Parts   :	 25      
+	DELETE        Parts   :	 10      
+	STUFF         Parts   :	 10      
+	DEPTH         Traverse:	 5       
+	% DECREASE    Parts   :	 0       
+	% INCREASE    LookUps :	 0       
+	% INCREASE    Deletes :	 0       
+	% INCREASE    Stuffs  :	 0       
+	FREEZE_PACKETS        :	 1       
+	ALLOC_CHUNKS          :	 10000   
+	EXTEND_CHUNKS         :	 5000    
+	DELETE Draw objects   :	 True                 
+	DELETE Part objects   :	 False                
+	QUE_BUG               :	 1000
+	VOID_BOUNDARY         :	 67108864
+	VOID_RESERVE          :	 1048576
+
+	COMMIT_DBS            :	 False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..168a8eefa
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -0,0 +1,244 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.202942                       # Number of seconds simulated
+sim_ticks                                202941992000                       # Number of ticks simulated
+final_tick                               202941992000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1608666                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2398029397                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222724                       # Number of bytes of host memory used
+host_seconds                                    84.63                       # Real time elapsed on the host
+sim_insts                                   136139203                       # Number of instructions simulated
+system.physmem.bytes_read                     8970304                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 835264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  5584960                       # Number of bytes written to this memory
+system.physmem.num_reads                       140161                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       87265                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       44201320                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   4115777                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      27519982                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      71721303                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.numCycles                        405883984                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        136139203                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
+system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8898970                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    115187758                       # number of integer instructions
+system.cpu.num_fp_insts                       2326977                       # number of float instructions
+system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          113147746                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      58160249                       # number of memory refs
+system.cpu.num_load_insts                    37275868                       # Number of load instructions
+system.cpu.num_store_insts                   20884381                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  405883984                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                 184976                       # number of replacements
+system.cpu.icache.tagsinuse               2004.721102                       # Cycle average of tags in use
+system.cpu.icache.total_refs                134366560                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 718.445547                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle           144544557000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           2004.721102                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.978868                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              134366560                       # number of ReadReq hits
+system.cpu.icache.demand_hits               134366560                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              134366560                       # number of overall hits
+system.cpu.icache.ReadReq_misses               187024                       # number of ReadReq misses
+system.cpu.icache.demand_misses                187024                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses               187024                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     3166478000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      3166478000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     3166478000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          134553584                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           134553584                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          134553584                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.001390                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.001390                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.001390                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 16930.864488                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 16930.864488                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 16930.864488                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          187024                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           187024                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          187024                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency   2605406000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   2605406000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   2605406000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.001390                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.001390                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.001390                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13930.864488                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 146582                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.617150                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              776708000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4087.617150                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997953                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               37185802                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              20759140                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits                  15901                       # number of SwapReq hits
+system.cpu.dcache.demand_hits                57944942                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               57944942                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                45499                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              105164                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses                   15                       # number of SwapReq misses
+system.cpu.dcache.demand_misses                150663                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               150663                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     1709246000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    5738404000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency         462000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency      7447650000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     7447650000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           37231301                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          20864304                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses              15916                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            58095605                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001222                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.005040                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate          0.000942                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate           0.002593                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002593                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 37566.671795                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 54566.239398                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency        30800                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 49432.508313                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 49432.508313                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   118818                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           45499                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         105164                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses              15                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           150663                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          150663                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1572749000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   5422912000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency       417000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   6995661000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   6995661000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001222                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005040                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.000942                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002593                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002593                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34566.671795                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51566.239398                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        27800                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                120138                       # number of replacements
+system.cpu.l2cache.tagsinuse             19734.031622                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  212003                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                139002                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.525179                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3965.924560                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15768.107062                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.121030                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.481204                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                193942                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              118818                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                3599                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 197541                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                197541                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               38581                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            101580                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               140161                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              140161                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    2006212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   5282160000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     7288372000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    7288372000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            232523                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          118818                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          105179                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             337702                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            337702                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.165923                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.965782                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.415043                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.415043                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   87265                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          38581                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       101580                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          140161                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         140161                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1543240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4063200000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   5606440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   5606440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165923                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.965782                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.415043                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.415043                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/test.py b/tests/long/se/50.vortex/test.py
new file mode 100644
index 000000000..92422c234
--- /dev/null
+++ b/tests/long/se/50.vortex/test.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import vortex
+
+workload = vortex(isa, opsys, 'smred')
+root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
new file mode 100644
index 000000000..0d09e2e14
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -0,0 +1,240 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
new file mode 100755
index 000000000..8bc14bb8a
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:50
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 1009857089500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
new file mode 100644
index 000000000..bf815a6e1
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -0,0 +1,315 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  1.009857                       # Number of seconds simulated
+sim_ticks                                1009857089500                       # Number of ticks simulated
+final_tick                               1009857089500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 102085                       # Simulator instruction rate (inst/s)
+host_tick_rate                               56650413                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208040                       # Number of bytes of host memory used
+host_seconds                                 17826.12                       # Real time elapsed on the host
+sim_insts                                  1819780127                       # Number of instructions simulated
+system.physmem.bytes_read                   172617984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  54912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 74938304                       # Number of bytes written to this memory
+system.physmem.num_reads                      2697156                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1170911                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      170933081                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     54376                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      74206841                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     245139922                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    444614420                       # DTB read hits
+system.cpu.dtb.read_misses                    4897078                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                449511498                       # DTB read accesses
+system.cpu.dtb.write_hits                   160920903                       # DTB write hits
+system.cpu.dtb.write_misses                   1701304                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               162622207                       # DTB write accesses
+system.cpu.dtb.data_hits                    605535323                       # DTB hits
+system.cpu.dtb.data_misses                    6598382                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                612133705                       # DTB accesses
+system.cpu.itb.fetch_hits                   233080732                       # ITB hits
+system.cpu.itb.fetch_misses                        22                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               233080754                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
+system.cpu.numCycles                       2019714180                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                    1746235830                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                         7533712                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       442869413                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                       1576844767                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         78.072669                       # Percentage of cycles cpu is active
+system.cpu.comLoads                         444595663                       # Number of Load instructions committed
+system.cpu.comStores                        160728502                       # Number of Store instructions committed
+system.cpu.comBranches                      214632552                       # Number of Branches instructions committed
+system.cpu.comNops                           83736345                       # Number of Nop instructions committed
+system.cpu.comNonSpec                              29                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                          916086844                       # Number of Integer instructions committed
+system.cpu.comFloats                              190                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                  1819780127                       # Number of Instructions Simulated (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total            1819780127                       # Number of Instructions Simulated (Total)
+system.cpu.cpi                               1.109867                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         1.109867                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.901009                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         0.901009                       # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups         330376347                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted    257464252                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect    140461747                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups      220099806                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits         142435401                       # Number of BTB hits
+system.cpu.branch_predictor.usedRAS          16767439                       # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct       64.714006                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken    178933469                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken    151442878                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads   1665721133                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites   1376202617                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses   3041923750                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads          230                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites          345                       # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses          575                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      654640669                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  617252269                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect    126684712                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect      7178577                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted      133863289                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          81336473                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     62.204199                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions       1137868323                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies                75                       # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.stage0.idleCycles                827214176                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                1192500004                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               59.043008                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles               1086300254                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 933413926                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               46.215149                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles               1046559994                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 973154186                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               48.182767                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles               1609984436                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 409729744                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               20.286521                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                997434545                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                1022279635                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               50.615065                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                      1                       # number of replacements
+system.cpu.icache.tagsinuse                664.479191                       # Cycle average of tags in use
+system.cpu.icache.total_refs                233079667                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    858                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               271654.623543                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            664.479191                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.324453                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              233079667                       # number of ReadReq hits
+system.cpu.icache.demand_hits               233079667                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              233079667                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1062                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1062                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1062                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       58337000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        58337000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       58337000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          233080729                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           233080729                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          233080729                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54931.261770                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54931.261770                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54931.261770                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets        83500                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               204                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                204                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               204                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             858                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              858                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             858                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     45872500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     45872500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     45872500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                9107352                       # number of replacements
+system.cpu.dcache.tagsinuse               4082.611665                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                595070081                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9111448                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  65.310155                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            12612838000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4082.611665                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.996731                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              437271428                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             157798653                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               595070081                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              595070081                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              7324235                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             2929849                       # number of WriteReq misses
+system.cpu.dcache.demand_misses              10254084                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses             10254084                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   180892053500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency  110288339500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency    291180393000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   291180393000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.016474                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.018229                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.016940                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.016940                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 28396.528934                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 28396.528934                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     10999000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   8091026500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2761                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          208994                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3983.701557                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  3058572                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            101953                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1040683                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1142636                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1142636                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7222282                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1889166                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9111448                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9111448                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  59191835500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 215279506500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 215279506500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.011754                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.015052                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.015052                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               2686299                       # number of replacements
+system.cpu.l2cache.tagsinuse             26355.239368                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7564573                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2710943                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.790384                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          223979031000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15511.274798                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10843.964569                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.473367                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.330932                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5414817                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3058572                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits             1000333                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6415150                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6415150                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1807881                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            889275                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2697156                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2697156                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   94453509000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  46507390000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency   140960899000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency  140960899000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7222698                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3058572                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1889608                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9112306                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9112306                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.250305                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.470613                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.295990                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.295990                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52262.790510                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52262.790510                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs       580500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               70                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8292.857143                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                 1170911                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1807881                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       889275                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2697156                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2697156                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  72354298500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  35671113500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 108025412000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 108025412000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250305                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.470613                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.295990                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.295990                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..4951679e2
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..35ea78ab1
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:43:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 615292058500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..3e098da07
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,525 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.615292                       # Number of seconds simulated
+sim_ticks                                615292058500                       # Number of ticks simulated
+final_tick                               615292058500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 151558                       # Simulator instruction rate (inst/s)
+host_tick_rate                               53715526                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208624                       # Number of bytes of host memory used
+host_seconds                                 11454.64                       # Real time elapsed on the host
+sim_insts                                  1736043781                       # Number of instructions simulated
+system.physmem.bytes_read                   173080384                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  60288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 74996480                       # Number of bytes written to this memory
+system.physmem.num_reads                      2704381                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1171820                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      281297933                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     97983                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     121887612                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     403185545                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    602552271                       # DTB read hits
+system.cpu.dtb.read_misses                   10614048                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                613166319                       # DTB read accesses
+system.cpu.dtb.write_hits                   207913538                       # DTB write hits
+system.cpu.dtb.write_misses                   6806894                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               214720432                       # DTB write accesses
+system.cpu.dtb.data_hits                    810465809                       # DTB hits
+system.cpu.dtb.data_misses                   17420942                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                827886751                       # DTB accesses
+system.cpu.itb.fetch_hits                   385401096                       # ITB hits
+system.cpu.itb.fetch_misses                        38                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               385401134                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
+system.cpu.numCycles                       1230584118                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                368788427                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          284655595                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           19443984                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             335810201                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                329206676                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 24336435                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1745                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          397544739                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3103801885                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   368788427                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          353543111                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     607804339                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               131920976                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              113986099                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   26                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           951                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 385401096                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               9585477                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1225061020                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.533590                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.019465                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                617256681     50.39%     50.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 52795543      4.31%     54.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 34983733      2.86%     57.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 53721044      4.39%     61.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                135046011     11.02%     72.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 74719502      6.10%     79.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 51323378      4.19%     83.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 43567102      3.56%     86.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                161648026     13.20%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total           1225061020                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.299686                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.522218                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                426009855                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             101612047                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 578250802                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              13464213                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              105724103                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             57118243                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   889                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3023280149                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  1933                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              105724103                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                448226724                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                58166398                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           3444                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 568166155                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              44774196                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2937967281                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                510732                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1525332                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              40266143                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2197783940                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3797275773                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3796267426                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1008347                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                821580977                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                180                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            178                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  93606956                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            663953354                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           248514283                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          54484359                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         31450059                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2647456890                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 154                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2459087861                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1981205                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       899874302                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    377613541                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            125                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1225061020                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.007319                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.938295                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           390052689     31.84%     31.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           197664545     16.14%     47.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           194534552     15.88%     63.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           152397104     12.44%     76.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           138172730     11.28%     87.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            75830053      6.19%     93.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            56958095      4.65%     98.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            14036871      1.15%     99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             5414381      0.44%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1225061020                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1870870     11.50%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11042349     67.89%     79.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3352440     20.61%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1607157901     65.36%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                   88      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 251      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  20      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 149      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 19      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  24      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            631365239     25.67%     91.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           220564170      8.97%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             2459087861                       # Type of FU issued
+system.cpu.iq.rate                           1.998309                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    16265659                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006615                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6159722029                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3546409355                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2357254024                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1761577                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1006663                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       825129                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2474476437                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  877083                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         54564037                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    219357691                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       276764                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        87944                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     87785781                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads           71                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        162830                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles              105724103                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                22305472                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1113476                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2788688851                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          12944530                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             663953354                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            248514283                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                154                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 231462                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 18115                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          87944                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       20335960                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2039327                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             22375287                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2405013673                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             613166540                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          54074188                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                     141231807                       # number of nop insts executed
+system.cpu.iew.exec_refs                    827886992                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                294323253                       # Number of branches executed
+system.cpu.iew.exec_stores                  214720452                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.954368                       # Inst execution rate
+system.cpu.iew.wb_sent                     2384887539                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2358079153                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1347433304                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1703552370                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.916228                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.790955                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       736139047                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          19443221                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1119336917                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.625766                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.487685                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    586822597     52.43%     52.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    186310200     16.64%     69.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     95274520      8.51%     77.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     53747896      4.80%     82.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     37177452      3.32%     85.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26985316      2.41%     88.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     21737766      1.94%     90.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     22635146      2.02%     92.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     88646024      7.92%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1119336917                       # Number of insts commited each cycle
+system.cpu.commit.count                    1819780126                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      605324165                       # Number of memory references committed
+system.cpu.commit.loads                     444595663                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                  214632552                       # Number of branches committed
+system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              88646024                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   3500830866                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5217723058                       # The number of ROB writes
+system.cpu.timesIdled                          398057                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5523098                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
+system.cpu.cpi                               0.708844                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.708844                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.410748                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.410748                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3237009112                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1887111006                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     12550                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      508                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
+system.cpu.icache.replacements                      1                       # number of replacements
+system.cpu.icache.tagsinuse                746.155324                       # Cycle average of tags in use
+system.cpu.icache.total_refs                385399748                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    942                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               409129.244161                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            746.155324                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.364334                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              385399748                       # number of ReadReq hits
+system.cpu.icache.demand_hits               385399748                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              385399748                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1348                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1348                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1348                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       47398000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        47398000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       47398000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          385401096                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           385401096                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          385401096                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35161.721068                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35161.721068                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35161.721068                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               406                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                406                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               406                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             942                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              942                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             942                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     33448000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     33448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     33448000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000002                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000002                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000002                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35507.430998                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35507.430998                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35507.430998                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                9159821                       # number of replacements
+system.cpu.dcache.tagsinuse               4086.961398                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                693411949                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9163917                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  75.667637                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             5157991000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4086.961398                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997793                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              537597174                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             155814773                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits                2                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits               693411947                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              693411947                       # number of overall hits
+system.cpu.dcache.ReadReq_misses             10313435                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             4913729                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              1                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses              15227164                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses             15227164                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   172073260500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency  137521396881                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        38500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency    309594657381                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   309594657381                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          547910609                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           708639111                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          708639111                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.018823                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.030572                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.333333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.021488                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.021488                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 16684.379210                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27987.175703                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        38500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 20331.734615                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 20331.734615                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    119268264                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   2148368000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             37813                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           65113                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3154.160315                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 32994.455792                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  3077535                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           3034555                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          3028693                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            6063248                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           6063248                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7278880                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1885036                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9163916                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9163916                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  81039107500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  38640356536                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 119679464036                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 119679464036                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.013285                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.011728                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.333333                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.012932                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.012932                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11133.458375                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20498.471401                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13059.860439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 13059.860439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               2693797                       # number of replacements
+system.cpu.l2cache.tagsinuse             26669.588705                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7633154                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2718439                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.807918                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          126954186500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15903.024773                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10766.563932                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.485322                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.328569                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5458962                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3077535                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits             1001516                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6460478                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6460478                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1820852                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            883529                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2704381                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2704381                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   62524059000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  30450873000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    92974932000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   92974932000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7279814                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3077535                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1885045                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9164859                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9164859                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.250123                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.468704                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.295082                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.295082                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34337.803951                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.052081                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34379.376279                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34379.376279                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs     17570000                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs             1704                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10311.032864                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                 1171820                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1820852                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       883529                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2704381                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2704381                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56737753000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  27632234500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  84369987500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  84369987500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250123                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.468704                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.295082                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.295082                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31160.002570                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31274.847232                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31197.522649                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31197.522649                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..52ac7c920
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..3465b9fda
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:45:21
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 913189263000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..1f32f6942
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.913189                       # Number of seconds simulated
+sim_ticks                                913189263000                       # Number of ticks simulated
+final_tick                               913189263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                4221832                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2118570165                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 198896                       # Number of bytes of host memory used
+host_seconds                                   431.04                       # Real time elapsed on the host
+sim_insts                                  1819780127                       # Number of instructions simulated
+system.physmem.bytes_read                  9280309971                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             7305514036                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                827777307                       # Number of bytes written to this memory
+system.physmem.num_reads                   2270974172                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   160728502                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10162526375                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999999926                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     906468506                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11068994882                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    444595663                       # DTB read hits
+system.cpu.dtb.read_misses                    4897078                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                449492741                       # DTB read accesses
+system.cpu.dtb.write_hits                   160728502                       # DTB write hits
+system.cpu.dtb.write_misses                   1701304                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               162429806                       # DTB write accesses
+system.cpu.dtb.data_hits                    605324165                       # DTB hits
+system.cpu.dtb.data_misses                    6598382                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                611922547                       # DTB accesses
+system.cpu.itb.fetch_hits                  1826378509                       # ITB hits
+system.cpu.itb.fetch_misses                        18                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses              1826378527                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
+system.cpu.numCycles                       1826378527                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1819780127                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1725565901                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 805526                       # Number of float alu accesses
+system.cpu.num_func_calls                    33534877                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    164021647                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1725565901                       # number of integer instructions
+system.cpu.num_fp_insts                        805526                       # number of float instructions
+system.cpu.num_int_register_reads          2347934659                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1376202618                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                  357                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                 345                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     611922547                       # number of memory refs
+system.cpu.num_load_insts                   449492741                       # Number of load instructions
+system.cpu.num_store_insts                  162429806                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1826378527                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..b74c06509
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..5e40861f7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:52:43
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2663443716000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..99a911858
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,266 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.663444                       # Number of seconds simulated
+sim_ticks                                2663443716000                       # Number of ticks simulated
+final_tick                               2663443716000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1948044                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2851171142                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207608                       # Number of bytes of host memory used
+host_seconds                                   934.16                       # Real time elapsed on the host
+sim_insts                                  1819780127                       # Number of instructions simulated
+system.physmem.bytes_read                   172614208                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  51328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 74939072                       # Number of bytes written to this memory
+system.physmem.num_reads                      2697097                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1170923                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       64808656                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     19271                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      28136158                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      92944814                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    444595663                       # DTB read hits
+system.cpu.dtb.read_misses                    4897078                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                449492741                       # DTB read accesses
+system.cpu.dtb.write_hits                   160728502                       # DTB write hits
+system.cpu.dtb.write_misses                   1701304                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               162429806                       # DTB write accesses
+system.cpu.dtb.data_hits                    605324165                       # DTB hits
+system.cpu.dtb.data_misses                    6598382                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                611922547                       # DTB accesses
+system.cpu.itb.fetch_hits                  1826378510                       # ITB hits
+system.cpu.itb.fetch_misses                        18                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses              1826378528                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
+system.cpu.numCycles                       5326887432                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1819780127                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1725565901                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 805526                       # Number of float alu accesses
+system.cpu.num_func_calls                    33534877                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    164021647                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1725565901                       # number of integer instructions
+system.cpu.num_fp_insts                        805526                       # number of float instructions
+system.cpu.num_int_register_reads          2347934659                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1376202618                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                  357                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                 345                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     611922547                       # number of memory refs
+system.cpu.num_load_insts                   449492741                       # Number of load instructions
+system.cpu.num_store_insts                  162429806                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 5326887432                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      1                       # number of replacements
+system.cpu.icache.tagsinuse                612.356766                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1826377708                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               2277278.937656                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            612.356766                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.299002                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits             1826377708                       # number of ReadReq hits
+system.cpu.icache.demand_hits              1826377708                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             1826377708                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  802                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   802                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  802                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       44912000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        44912000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       44912000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         1826378510                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          1826378510                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         1826378510                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             802                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              802                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             802                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     42506000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     42506000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     42506000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                9107638                       # number of replacements
+system.cpu.dcache.tagsinuse               4079.504248                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            40989969000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4079.504248                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995973                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              437373249                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             158839182                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               596212431                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              596212431                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              7222414                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1889320                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               9111734                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              9111734                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   177010400000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   63798266000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency    240808666000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   240808666000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.016245                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.011755                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.015053                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.015053                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 26428.412638                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 26428.412638                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  3058802                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7222414                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1889320                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9111734                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9111734                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  58130306000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 213473464000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 213473464000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.011755                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.015053                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.015053                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               2686269                       # number of replacements
+system.cpu.l2cache.tagsinuse             26040.087196                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7565346                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2710912                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.790701                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          582065656000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15312.508302                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10727.578894                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.467301                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.327380                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5415352                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3058802                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits             1000087                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6415439                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6415439                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1807864                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            889233                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2697097                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2697097                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   94008928000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  46240116000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency   140249044000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency  140249044000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7223216                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3058802                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1889320                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9112536                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9112536                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.250285                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.470663                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.295977                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.295977                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                 1170923                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1807864                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       889233                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2697097                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2697097                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  72314560000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  35569320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 107883880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 107883880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250285                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.470663                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.295977                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.295977                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..669a8b83b
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..1474108e5
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:09
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 483463019500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..bd2b3efef
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,536 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.483463                       # Number of seconds simulated
+sim_ticks                                483463019500                       # Number of ticks simulated
+final_tick                               483463019500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 152421                       # Simulator instruction rate (inst/s)
+host_tick_rate                               42766664                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220608                       # Number of bytes of host memory used
+host_seconds                                 11304.67                       # Real time elapsed on the host
+sim_insts                                  1723073849                       # Number of instructions simulated
+system.physmem.bytes_read                   188174592                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  45888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 77926272                       # Number of bytes written to this memory
+system.physmem.num_reads                      2940228                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1217598                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                      389222307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     94915                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     161183522                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     550405829                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.numCycles                        966926040                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                298898243                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          243989412                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           18339920                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             264347245                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                238745657                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 17668157                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                3423                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          295953389                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2175230772                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   298898243                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          256413814                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     484717826                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                87053301                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              107577195                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    8                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           142                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 285045078                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               5311594                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          956547645                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.521914                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.026495                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                471829873     49.33%     49.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 35367236      3.70%     53.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 65085859      6.80%     59.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 66860371      6.99%     66.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 46850107      4.90%     71.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 59747954      6.25%     77.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 54343246      5.68%     83.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 17692463      1.85%     85.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                138770536     14.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            956547645                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.309122                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.249635                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                322987122                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              92097194                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 459538157                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              13626726                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               68298446                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             46874540                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   671                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2352694278                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2235                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               68298446                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                343127088                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46537686                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          27220                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 451783493                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              46773712                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2295847883                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 19963                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2697037                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              37730930                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents                3                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2264588148                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           10605407368                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      10605405778                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              1590                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1706319951                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                558268197                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              10043                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          10038                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  98804137                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            618742816                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           222099567                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          74239442                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         61602093                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2187718033                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2090                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2018498325                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3274725                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       458502719                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1049949895                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1587                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     956547645                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.110191                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.840946                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262039584     27.39%     27.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           150878554     15.77%     43.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           168430661     17.61%     60.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           136432052     14.26%     75.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           124835406     13.05%     88.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            73540708      7.69%     95.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            29241453      3.06%     98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            10225405      1.07%     99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              923822      0.10%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       956547645                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  901388      3.68%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    177      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               19016870     77.70%     81.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4557312     18.62%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1238993791     61.38%     61.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              1017752      0.05%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              14      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               3      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc             13      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              2      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            583952461     28.93%     90.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           194534287      9.64%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             2018498325                       # Type of FU issued
+system.cpu.iq.rate                           2.087542                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    24475747                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012126                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5021294480                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2646401011                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1958335598                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 287                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                294                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          124                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2042973928                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     144                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         55719619                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    132816045                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       210497                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       180679                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     47252521                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        451790                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               68298446                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                22155006                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1213609                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2187738627                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           7300026                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             618742816                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            222099567                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               2027                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 219640                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 61277                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         180679                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       18953795                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1821941                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             20775736                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1986087052                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             570299160                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          32411273                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         18504                       # number of nop insts executed
+system.cpu.iew.exec_refs                    761501875                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                238650211                       # Number of branches executed
+system.cpu.iew.exec_stores                  191202715                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.054022                       # Inst execution rate
+system.cpu.iew.wb_sent                     1967277607                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1958335722                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1288034280                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2036866160                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       2.025321                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.632361                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1723073867                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       464746992                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             503                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          18339818                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    888249200                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.939854                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.672088                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    383075847     43.13%     43.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    200735352     22.60%     65.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     81917807      9.22%     74.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     38649475      4.35%     79.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     19675094      2.22%     81.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     31029952      3.49%     85.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     22284246      2.51%     87.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     12052552      1.36%     88.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     98828875     11.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    888249200                       # Number of insts commited each cycle
+system.cpu.commit.count                    1723073867                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      660773817                       # Number of memory references committed
+system.cpu.commit.loads                     485926771                       # Number of loads committed
+system.cpu.commit.membars                          62                       # Number of memory barriers committed
+system.cpu.commit.branches                  213462365                       # Number of branches committed
+system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1536941853                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              98828875                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   2977240585                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4444170390                       # The number of ROB writes
+system.cpu.timesIdled                          920776                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        10378395                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1723073849                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1723073849                       # Number of Instructions Simulated
+system.cpu.cpi                               0.561163                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.561163                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.782012                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.782012                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               9942029327                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1939848996                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       117                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       59                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              2913839911                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    126                       # number of misc regfile writes
+system.cpu.icache.replacements                     10                       # number of replacements
+system.cpu.icache.tagsinuse                609.858480                       # Cycle average of tags in use
+system.cpu.icache.total_refs                285044064                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    744                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               383123.741935                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            609.858480                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.297782                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              285044064                       # number of ReadReq hits
+system.cpu.icache.demand_hits               285044064                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              285044064                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1014                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1014                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1014                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       35191500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        35191500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       35191500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          285045078                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           285045078                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          285045078                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 34705.621302                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 34705.621302                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 34705.621302                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               270                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                270                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               270                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             744                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              744                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             744                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     25627000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     25627000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     25627000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34444.892473                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34444.892473                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34444.892473                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                9570827                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.732038                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                666909210                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9574923                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  69.651653                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             3484303000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4087.732038                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997981                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              499513800                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             167395288                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               60                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits                62                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               666909088                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              666909088                       # number of overall hits
+system.cpu.dcache.ReadReq_misses             10448466                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             5190759                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses              15639225                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses             15639225                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   184465722500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency  128555474171                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       113500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency    313021196671                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   313021196671                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          509962266                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses            62                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           682548313                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          682548313                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.020489                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.030076                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.047619                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.022913                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.022913                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 17654.813874                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 24766.219000                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 20015.134808                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 20015.134808                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    266703683                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       196000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             90656                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2941.930848                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16333.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  3128328                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           2766203                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          3298099                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            6064302                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           6064302                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7682263                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1892660                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9574923                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9574923                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  92044930000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  45262385908                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 137307315908                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 137307315908                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.015064                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.010966                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.014028                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.014028                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.486445                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23914.694614                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 14340.304972                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 14340.304972                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               2927819                       # number of replacements
+system.cpu.l2cache.tagsinuse             26780.774124                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7851022                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2955142                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.656733                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          102041743500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15984.490640                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10796.283484                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.487808                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.329476                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5655252                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3128328                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              980176                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6635428                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6635428                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             2027753                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            912486                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2940239                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2940239                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   69614113000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  31648901500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency   101263014500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency  101263014500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7683005                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3128328                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1892662                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9575667                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9575667                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.263927                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.482118                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.307053                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.307053                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34330.666999                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.259813                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34440.402464                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34440.402464                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs     56231500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs             6603                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8516.053309                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                 1217598                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               11                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                11                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               11                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        2027742                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       912486                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2940228                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2940228                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  63235914500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  28815026500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  92050941000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  92050941000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.263926                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.482118                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.307052                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.307052                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.384778                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31578.595726                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.415955                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.415955                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..bbede2479
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..e599bde0b
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:37:28
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 861538205000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..e23300649
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.861538                       # Number of seconds simulated
+sim_ticks                                861538205000                       # Number of ticks simulated
+final_tick                               861538205000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3027828                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1513916118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210380                       # Number of bytes of host memory used
+host_seconds                                   569.08                       # Real time elapsed on the host
+sim_insts                                  1723073862                       # Number of instructions simulated
+system.physmem.bytes_read                  7759650064                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             6178262392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                624158392                       # Number of bytes written to this memory
+system.physmem.num_reads                   2026949786                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   172586108                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     9006739363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7171199555                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     724469778                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9731209141                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.numCycles                       1723076411                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1723073862                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
+system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    177498066                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1536941850                       # number of integer instructions
+system.cpu.num_fp_insts                            36                       # number of float instructions
+system.cpu.num_int_register_reads          7861284536                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1675132418                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     660773816                       # number of memory refs
+system.cpu.num_load_insts                   485926770                       # Number of load instructions
+system.cpu.num_store_insts                  174847046                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 1723076411                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..71abd898d
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..8198567b7
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:45:39
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2431419954000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..04e3122e6
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.431420                       # Number of seconds simulated
+sim_ticks                                2431419954000                       # Number of ticks simulated
+final_tick                               2431419954000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1410228                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1996689457                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219344                       # Number of bytes of host memory used
+host_seconds                                  1217.73                       # Real time elapsed on the host
+sim_insts                                  1717270343                       # Number of instructions simulated
+system.physmem.bytes_read                   172766016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  39424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 75006720                       # Number of bytes written to this memory
+system.physmem.num_reads                      2699469                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1171980                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       71055605                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     16214                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      30848937                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     101904542                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.numCycles                       4862839908                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       1717270343                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
+system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    177498066                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1536941850                       # number of integer instructions
+system.cpu.num_fp_insts                            36                       # number of float instructions
+system.cpu.num_int_register_reads          9304894713                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1675132418                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
+system.cpu.num_mem_refs                     660773816                       # number of memory refs
+system.cpu.num_load_insts                   485926770                       # Number of load instructions
+system.cpu.num_store_insts                  174847046                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 4862839908                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                      7                       # number of replacements
+system.cpu.icache.tagsinuse                514.872896                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1544564961                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               2420948.214734                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            514.872896                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.251403                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits             1544564961                       # number of ReadReq hits
+system.cpu.icache.demand_hits              1544564961                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             1544564961                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  638                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   638                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  638                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       34804000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        34804000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       34804000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         1544565599                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          1544565599                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         1544565599                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54551.724138                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54551.724138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54551.724138                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             638                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              638                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             638                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     32890000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     32890000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     32890000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                9111140                       # number of replacements
+system.cpu.dcache.tagsinuse               4083.719979                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                645855060                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9115236                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  70.854453                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            25923025000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4083.719979                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997002                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              475158040                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             170696898                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               61                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits                61                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               645854938                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              645854938                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              7226087                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1889149                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               9115236                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              9115236                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   177140908000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   63824222000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency    240965130000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   240965130000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          482384127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses            61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           654970174                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          654970174                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.014980                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.010946                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.013917                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.013917                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  3061985                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7226087                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1889149                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9115236                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9115236                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  58156775000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 213619422000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 213619422000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.014980                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.010946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.013917                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.013917                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               2687066                       # number of replacements
+system.cpu.l2cache.tagsinuse             26134.517233                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7569171                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2714383                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.788542                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          538044123000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15027.621217                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11106.896016                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.458607                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.338956                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5417164                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3061985                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              999241                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6416405                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6416405                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1809561                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            889908                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2699469                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2699469                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   94097172000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  46275216000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency   140372388000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency  140372388000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7226725                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3061985                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1889149                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9115874                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9115874                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.250398                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.471063                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.296128                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.296128                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                 1171980                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1809561                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       889908                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2699469                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2699469                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  72382440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  35596320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 107978760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 107978760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250398                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471063                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.296128                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.296128                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..fe30d10a3
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
new file mode 100755
index 000000000..a5a0064e6
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:13:31
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2846007259500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..6725100b8
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  2.846007                       # Number of seconds simulated
+sim_ticks                                2846007259500                       # Number of ticks simulated
+final_tick                               2846007259500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2006575                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1218454030                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204704                       # Number of bytes of host memory used
+host_seconds                                  2335.75                       # Real time elapsed on the host
+sim_insts                                  4686862651                       # Number of instructions simulated
+system.physmem.bytes_read                 37129731755                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read            32105863408                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written               1544656790                       # Number of bytes written to this memory
+system.physmem.num_reads                   5252417675                       # Number of read requests responded to by this memory
+system.physmem.num_writes                   438528337                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    13046253354                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read               11281019506                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     542745204                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13588998558                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.numCycles                       5692014520                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       4686862651                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            4686862580                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    182173305                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   4686862580                       # number of integer instructions
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_int_register_reads         11558008181                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         4679057393                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                    1677713086                       # number of memory refs
+system.cpu.num_load_insts                  1239184749                       # Number of load instructions
+system.cpu.num_store_insts                  438528337                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                 5692014520                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
new file mode 100644
index 000000000..e57f67518
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
new file mode 100755
index 000000000..5d5232885
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:30:19
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 5923548078000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..94c5d24c6
--- /dev/null
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -0,0 +1,234 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  5.923548                       # Number of seconds simulated
+sim_ticks                                5923548078000                       # Number of ticks simulated
+final_tick                               5923548078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1176749                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1487248019                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213688                       # Number of bytes of host memory used
+host_seconds                                  3982.89                       # Real time elapsed on the host
+sim_insts                                  4686862651                       # Number of instructions simulated
+system.physmem.bytes_read                   173910080                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  43200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 75176384                       # Number of bytes written to this memory
+system.physmem.num_reads                      2717345                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     1174631                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       29359107                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                      7293                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      12691107                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      42050214                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.numCycles                      11847096156                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                       4686862651                       # Number of instructions executed
+system.cpu.num_int_alu_accesses            4686862580                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    182173305                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   4686862580                       # number of integer instructions
+system.cpu.num_fp_insts                             0                       # number of float instructions
+system.cpu.num_int_register_reads         11558008181                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         4679057393                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                    1677713086                       # number of memory refs
+system.cpu.num_load_insts                  1239184749                       # Number of load instructions
+system.cpu.num_store_insts                  438528337                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                11847096156                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                     10                       # number of replacements
+system.cpu.icache.tagsinuse                555.713137                       # Cycle average of tags in use
+system.cpu.icache.total_refs               4013232252                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    675                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               5945529.262222                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            555.713137                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.271344                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits             4013232252                       # number of ReadReq hits
+system.cpu.icache.demand_hits              4013232252                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits             4013232252                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  675                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   675                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  675                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       37800000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        37800000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       37800000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses         4013232927                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses          4013232927                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses         4013232927                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             675                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              675                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             675                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     35775000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     35775000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     35775000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                9108581                       # number of replacements
+system.cpu.dcache.tagsinuse               4084.662246                       # Cycle average of tags in use
+system.cpu.dcache.total_refs               1668600409                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9112677                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 183.107599                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            58862779000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4084.662246                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997232                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits             1231961899                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             436638510                       # number of WriteReq hits
+system.cpu.dcache.demand_hits              1668600409                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits             1668600409                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              7222850                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1889827                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               9112677                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              9112677                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   177808540000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   63869078000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency    241677618000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   241677618000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses         1239184749                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         438528337                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses          1677713086                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses         1677713086                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.005829                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.004309                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.005432                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.005432                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 26521.034159                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 26521.034159                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  3053391                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7222850                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1889827                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9112677                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9112677                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  58199597000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 214339587000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 214339587000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.005829                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.004309                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005432                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005432                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               2706631                       # number of replacements
+system.cpu.l2cache.tagsinuse             26507.350069                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7537629                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2732923                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.758083                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          1324806325000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15478.805498                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11028.544571                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.472376                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.336564                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5396930                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3053391                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              999077                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6396007                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6396007                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1826595                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            890750                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2717345                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2717345                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   94982940000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  46319000000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency   141301940000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency  141301940000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7223525                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3053391                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1889827                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9113352                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9113352                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.252868                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.471339                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.298172                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.298172                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                 1174631                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1826595                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       890750                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2717345                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2717345                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  73063800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  35630000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 108693800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 108693800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.252868                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471339                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.298172                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.298172                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/test.py b/tests/long/se/60.bzip2/test.py
new file mode 100644
index 000000000..fa74d0860
--- /dev/null
+++ b/tests/long/se/60.bzip2/test.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import bzip2_source
+
+workload = bzip2_source(isa, opsys, 'lgred')
+root.system.cpu.workload = workload.makeLiveProcess()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
new file mode 100644
index 000000000..64fd65cd8
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -0,0 +1,240 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
new file mode 100755
index 000000000..ab1cbef0e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:57:18
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 41833966000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
new file mode 100644
index 000000000..98777e0af
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.3  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.3 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
new file mode 100644
index 000000000..db43e1bd8
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -0,0 +1,314 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.041834                       # Number of seconds simulated
+sim_ticks                                 41833966000                       # Number of ticks simulated
+final_tick                                41833966000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 111295                       # Simulator instruction rate (inst/s)
+host_tick_rate                               50660994                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211656                       # Number of bytes of host memory used
+host_seconds                                   825.76                       # Real time elapsed on the host
+sim_insts                                    91903056                       # Number of instructions simulated
+system.physmem.bytes_read                      316032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 178816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         4938                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        7554436                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   4274421                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       7554436                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     19996214                       # DTB read hits
+system.cpu.dtb.read_misses                         10                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 19996224                       # DTB read accesses
+system.cpu.dtb.write_hits                     6501905                       # DTB write hits
+system.cpu.dtb.write_misses                        23                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                 6501928                       # DTB write accesses
+system.cpu.dtb.data_hits                     26498119                       # DTB hits
+system.cpu.dtb.data_misses                         33                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                 26498152                       # DTB accesses
+system.cpu.itb.fetch_hits                     9991202                       # ITB hits
+system.cpu.itb.fetch_misses                        49                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                 9991251                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
+system.cpu.numCycles                         83667933                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.contextSwitches                          1                       # Number of context switches
+system.cpu.threadCycles                      83292959                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled                           10907                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7700653                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         75967280                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         90.796172                       # Percentage of cycles cpu is active
+system.cpu.comLoads                          19996198                       # Number of Load instructions committed
+system.cpu.comStores                          6501103                       # Number of Store instructions committed
+system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
+system.cpu.comNops                            7723346                       # Number of Nop instructions committed
+system.cpu.comNonSpec                             389                       # Number of Non-Speculative instructions committed
+system.cpu.comInts                           43665352                       # Number of Integer instructions committed
+system.cpu.comFloats                          3775974                       # Number of Floating Point instructions committed
+system.cpu.committedInsts                    91903056                       # Number of Instructions Simulated (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total              91903056                       # Number of Instructions Simulated (Total)
+system.cpu.cpi                               0.910393                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
+system.cpu.cpi_total                         0.910393                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.098426                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
+system.cpu.ipc_total                         1.098426                       # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups          13542330                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted      9941405                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect      4410938                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups        8655858                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits           4135478                       # Number of BTB hits
+system.cpu.branch_predictor.usedRAS           1029619                       # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect          132                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct       47.776639                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken      6269254                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken      7273076                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads     73609025                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites     62575472                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses    136184497                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads      2206079                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites      5851888                       # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses      8057967                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards       38654467                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                   26652325                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect      3861647                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect       548433                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted        4410080                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted           5830622                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     43.064235                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions         57347630                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies            458254                       # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.stage0.idleCycles                 27446781                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  56221152                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               67.195579                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 34307675                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  49360258                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               58.995431                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 33744588                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  49923345                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               59.668434                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 65638077                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  18029856                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               21.549303                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 29755825                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  53912108                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               64.435807                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                   7551                       # number of replacements
+system.cpu.icache.tagsinuse               1491.782957                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  9979713                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   9436                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                1057.621132                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1491.782957                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.728410                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                9979713                       # number of ReadReq hits
+system.cpu.icache.demand_hits                 9979713                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                9979713                       # number of overall hits
+system.cpu.icache.ReadReq_misses                11486                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 11486                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                11486                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      291407500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       291407500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      291407500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses            9991199                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses             9991199                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses            9991199                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.001150                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.001150                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.001150                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 25370.668640                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 25370.668640                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 25370.668640                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets        69500                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets        17375                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              2050                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               2050                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              2050                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            9436                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             9436                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            9436                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    222700000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    222700000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    222700000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000944                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000944                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000944                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                    157                       # number of replacements
+system.cpu.dcache.tagsinuse               1441.532122                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26491206                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               11916.871795                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1441.532122                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.351937                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               19995645                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               6495561                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                26491206                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               26491206                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  553                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                5542                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  6095                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 6095                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       28393500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     303801000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       332194500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      332194500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000028                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000852                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000230                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000230                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54502.789171                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54502.789171                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets     41047000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             824                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      107                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits                78                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             3794                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               3872                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              3872                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1748                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             2223                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            2223                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     23213000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     92997500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    116210500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    116210500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              2189.253602                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    6704                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3282                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.042657                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2171.415543                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            17.838059                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.066266                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000544                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  6695                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 107                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  26                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   6721                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  6721                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3216                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1722                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 4938                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                4938                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     168327500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     90565000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      258892500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     258892500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              9911                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses             107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              11659                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             11659                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.324488                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.985126                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.423535                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.423535                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52428.614824                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52428.614824                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           3216                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            4938                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           4938                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    129053500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     69344000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    198397500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    198397500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.324488                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985126                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.423535                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.423535                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..a6f9e5430
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..9901dc40b
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:08:28
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 29167093500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
new file mode 100644
index 000000000..98777e0af
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.3  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.3 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..55d9dc21f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,524 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.029167                       # Number of seconds simulated
+sim_ticks                                 29167093500                       # Number of ticks simulated
+final_tick                                29167093500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 155660                       # Simulator instruction rate (inst/s)
+host_tick_rate                               53933893                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212576                       # Number of bytes of host memory used
+host_seconds                                   540.79                       # Real time elapsed on the host
+sim_insts                                    84179709                       # Number of instructions simulated
+system.physmem.bytes_read                      332416                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 193856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         5194                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                       11396953                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   6646394                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      11396953                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     25236325                       # DTB read hits
+system.cpu.dtb.read_misses                     540509                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 25776834                       # DTB read accesses
+system.cpu.dtb.write_hits                     7362909                       # DTB write hits
+system.cpu.dtb.write_misses                      1032                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                 7363941                       # DTB write accesses
+system.cpu.dtb.data_hits                     32599234                       # DTB hits
+system.cpu.dtb.data_misses                     541541                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                 33140775                       # DTB accesses
+system.cpu.itb.fetch_hits                    18604047                       # ITB hits
+system.cpu.itb.fetch_misses                        85                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                18604132                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
+system.cpu.numCycles                         58334188                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 18443606                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           13550904                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1909309                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              15151906                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 11744171                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1797123                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                2508                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           19753130                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      155901269                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    18443606                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13541294                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      28873870                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8029527                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                3519156                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   49                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1819                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  18604047                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                633220                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           58241050                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.676828                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.252315                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 29367180     50.42%     50.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2937608      5.04%     55.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2015194      3.46%     58.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3338566      5.73%     64.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4094138      7.03%     71.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1423310      2.44%     74.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1755062      3.01%     77.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1585835      2.72%     79.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11724157     20.13%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total             58241050                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.316171                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.672554                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 21649179                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               2708949                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  27144653                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                658698                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6079571                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2969190                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13806                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              150046107                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 43597                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6079571                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 23241789                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  566661                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           6095                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  26202396                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               2144538                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              144061667                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 244284                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1605069                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           105522995                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             186327738                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        175726328                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          10601410                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 37095634                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                535                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            531                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   6071657                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29750182                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             9383371                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2457988                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           836885                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  120824169                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 510                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 104934850                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            288533                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        35688110                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     27652526                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            121                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      58241050                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.801733                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.850509                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            19806248     34.01%     34.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            11039636     18.96%     52.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             9348946     16.05%     69.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6752104     11.59%     80.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5521673      9.48%     90.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2974014      5.11%     95.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1775531      3.05%     98.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              852122      1.46%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              170776      0.29%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        58241050                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  161609      9.97%      9.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   218      0.01%      9.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  6469      0.40%     10.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                 2295      0.14%     10.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                845619     52.17%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     62.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 527151     32.52%     95.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                 77634      4.79%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              63561145     60.57%     60.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               485535      0.46%     61.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2794061      2.66%     63.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115045      0.11%     63.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2411045      2.30%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             308682      0.29%     66.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              763571      0.73%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                318      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             27006510     25.74%     92.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7488931      7.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              104934850                       # Type of FU issued
+system.cpu.iq.rate                           1.798857                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1620995                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.015448                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          254843963                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         146750024                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     92740043                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15176315                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9791044                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7062550                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               98540004                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8015834                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1319105                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      9753984                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        15279                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        28494                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2882268                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads        10177                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             1                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                6079571                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   81043                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 15363                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           132624218                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            876009                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29750182                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              9383371                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                510                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    184                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    33                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          28494                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1787084                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       342134                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              2129218                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             102333218                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25777384                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2601632                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                      11799539                       # number of nop insts executed
+system.cpu.iew.exec_refs                     33141424                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12916232                       # Number of branches executed
+system.cpu.iew.exec_stores                    7364040                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.754258                       # Inst execution rate
+system.cpu.iew.wb_sent                      101006568                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      99802593                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  67789343                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  93484829                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.710877                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.725137                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       91903055                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        40723267                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1895854                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     52161479                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.761895                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.510937                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     23655247     45.35%     45.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11195713     21.46%     66.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      5070133      9.72%     76.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2810925      5.39%     81.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1675607      3.21%     85.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1392452      2.67%     87.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       795157      1.52%     89.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       831289      1.59%     90.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4734956      9.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     52161479                       # Number of insts commited each cycle
+system.cpu.commit.count                      91903055                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       26497301                       # Number of memory references committed
+system.cpu.commit.loads                      19996198                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   10240685                       # Number of branches committed
+system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               4734956                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    180051805                       # The number of ROB reads
+system.cpu.rob.rob_writes                   271380444                       # The number of ROB writes
+system.cpu.timesIdled                            2277                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           93138                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
+system.cpu.cpi                               0.692972                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.692972                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.443060                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.443060                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                138495671                       # number of integer regfile reads
+system.cpu.int_regfile_writes                75435014                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6177236                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6044349                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  715554                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
+system.cpu.icache.replacements                   8695                       # number of replacements
+system.cpu.icache.tagsinuse               1593.002324                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 18592194                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  10628                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                1749.359616                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1593.002324                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.777833                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               18592194                       # number of ReadReq hits
+system.cpu.icache.demand_hits                18592194                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               18592194                       # number of overall hits
+system.cpu.icache.ReadReq_misses                11853                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 11853                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                11853                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      188036500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       188036500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      188036500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           18604047                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            18604047                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           18604047                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000637                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000637                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000637                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 15864.042858                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 15864.042858                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 15864.042858                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1225                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1225                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1225                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           10628                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            10628                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           10628                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    124769000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    124769000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    124769000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000571                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000571                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000571                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                    159                       # number of replacements
+system.cpu.dcache.tagsinuse               1462.507461                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 30399158                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   2246                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               13534.798753                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1462.507461                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.357057                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               23906051                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               6493055                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               52                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits                30399106                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               30399106                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  938                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                8048                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              1                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses                  8986                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 8986                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       28163500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     289889000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        38000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency       318052500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      318052500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           23906989                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses           53                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            30408092                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           30408092                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000039                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.001238                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.018868                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.000296                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000296                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 35394.224349                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 35394.224349                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         2500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs         2500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      108                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits               424                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             6317                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               6741                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              6741                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             514                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1731                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             2245                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            2245                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     16469500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     61655000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     78124500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     78124500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000021                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.018868                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000074                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000074                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              2400.275766                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    7666                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3556                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.155793                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2382.642182                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            17.633584                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.072712                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000538                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  7655                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 108                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  25                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   7680                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  7680                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3488                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1706                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 5194                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                5194                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     119792500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     59244000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      179036500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     179036500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             11143                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses             108                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1731                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              12874                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             12874                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.313022                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.985557                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.403449                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.403449                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34344.180046                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34726.846424                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34469.869080                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34469.869080                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           3488                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1706                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            5194                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           5194                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    108490000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     53828000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    162318000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    162318000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.313022                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985557                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.403449                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.403449                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..c3b5c0104
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..887ca3f4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:10:21
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 45951567500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
new file mode 100644
index 000000000..98777e0af
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.3  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.3 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..af93195e1
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.045952                       # Number of seconds simulated
+sim_ticks                                 45951567500                       # Number of ticks simulated
+final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                4191883                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2095941744                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 202544                       # Number of bytes of host memory used
+host_seconds                                    21.92                       # Real time elapsed on the host
+sim_insts                                    91903056                       # Number of instructions simulated
+system.physmem.bytes_read                   475949877                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              367612356                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 30920974                       # Number of bytes written to this memory
+system.physmem.num_reads                    111899287                       # Number of read requests responded to by this memory
+system.physmem.num_writes                     6501103                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10357641815                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999995996                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     672903574                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11030545389                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     19996198                       # DTB read hits
+system.cpu.dtb.read_misses                         10                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
+system.cpu.dtb.write_hits                     6501103                       # DTB write hits
+system.cpu.dtb.write_misses                        23                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                 6501126                       # DTB write accesses
+system.cpu.dtb.data_hits                     26497301                       # DTB hits
+system.cpu.dtb.data_misses                         33                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
+system.cpu.itb.fetch_hits                    91903089                       # ITB hits
+system.cpu.itb.fetch_misses                        47                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                91903136                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
+system.cpu.numCycles                         91903136                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         91903056                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
+system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7465012                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     79581109                       # number of integer instructions
+system.cpu.num_fp_insts                       6862064                       # number of float instructions
+system.cpu.num_int_register_reads           115028592                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           62575473                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              6071661                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             5851888                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      26497334                       # number of memory refs
+system.cpu.num_load_insts                    19996208                       # Number of load instructions
+system.cpu.num_store_insts                    6501126                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                   91903136                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..2fe44f969
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..84097b1db
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 06:10:54
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+info: Increasing stack size by one page.
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 118740049000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out
new file mode 100644
index 000000000..98777e0af
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.3  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.3 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..ba87aad33
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,265 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.118740                       # Number of seconds simulated
+sim_ticks                                118740049000                       # Number of ticks simulated
+final_tick                               118740049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                2095418                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2707308980                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211256                       # Number of bytes of host memory used
+host_seconds                                    43.86                       # Real time elapsed on the host
+sim_insts                                    91903056                       # Number of instructions simulated
+system.physmem.bytes_read                      304960                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 167744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         4765                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2568299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1412699                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       2568299                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     19996198                       # DTB read hits
+system.cpu.dtb.read_misses                         10                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
+system.cpu.dtb.write_hits                     6501103                       # DTB write hits
+system.cpu.dtb.write_misses                        23                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                 6501126                       # DTB write accesses
+system.cpu.dtb.data_hits                     26497301                       # DTB hits
+system.cpu.dtb.data_misses                         33                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
+system.cpu.itb.fetch_hits                    91903090                       # ITB hits
+system.cpu.itb.fetch_misses                        47                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                91903137                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
+system.cpu.numCycles                        237480098                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                         91903056                       # Number of instructions executed
+system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
+system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7465012                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     79581109                       # number of integer instructions
+system.cpu.num_fp_insts                       6862064                       # number of float instructions
+system.cpu.num_int_register_reads           115028592                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           62575473                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              6071661                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             5851888                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      26497334                       # number of memory refs
+system.cpu.num_load_insts                    19996208                       # Number of load instructions
+system.cpu.num_store_insts                    6501126                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  237480098                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   6681                       # number of replacements
+system.cpu.icache.tagsinuse               1418.037996                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 91894580                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               10798.423032                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1418.037996                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.692401                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               91894580                       # number of ReadReq hits
+system.cpu.icache.demand_hits                91894580                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               91894580                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 8510                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  8510                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 8510                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      229222000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       229222000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      229222000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           91903090                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            91903090                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           91903090                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000093                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000093                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000093                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 26935.605170                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 26935.605170                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 26935.605170                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            8510                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             8510                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            8510                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    203692000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    203692000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    203692000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000093                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000093                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000093                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                    157                       # number of replacements
+system.cpu.dcache.tagsinuse               1442.028823                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1442.028823                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.352058                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               19995723                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               6499355                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                26495078                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               26495078                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  475                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                1748                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  2223                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 2223                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       24374000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      96796000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       121170000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      121170000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000024                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000269                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000084                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000084                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54507.422402                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54507.422402                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                      107                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1748                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             2223                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            2223                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     22949000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     91552000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    114501000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    114501000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              2074.048594                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    5951                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3109                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.914120                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2056.253411                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            17.795183                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.062752                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000543                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  5942                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                 107                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  26                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   5968                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  5968                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3043                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1722                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 4765                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                4765                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     158236000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     89544000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      247780000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     247780000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              8985                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses             107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              10733                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             10733                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.338676                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.985126                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.443958                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.443958                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           3043                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            4765                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           4765                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    121720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     68880000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    190600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    190600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338676                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985126                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.443958                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.443958                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..8db3f9119
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..bee9aa417
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:47:07
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 105874925000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..4282a0231
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,534 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.105875                       # Number of seconds simulated
+sim_ticks                                105874925000                       # Number of ticks simulated
+final_tick                               105874925000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 103612                       # Simulator instruction rate (inst/s)
+host_tick_rate                               58144234                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224188                       # Number of bytes of host memory used
+host_seconds                                  1820.90                       # Real time elapsed on the host
+sim_insts                                   188667572                       # Number of instructions simulated
+system.physmem.bytes_read                      240192                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 128512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         3753                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2268639                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1213810                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       2268639                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        211749851                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                102127285                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           80698368                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            9933568                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              84243150                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 79257318                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  4698618                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              111511                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           44551125                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      416786863                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   102127285                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           83955936                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     108810185                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                33218375                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               35074253                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    9                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           251                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.CacheLines                  40624886                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2204416                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          211691341                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.135529                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.646861                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                103083318     48.70%     48.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4611723      2.18%     50.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 32955553     15.57%     66.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 18242297      8.62%     75.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  9176940      4.34%     79.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 12529739      5.92%     85.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  8472403      4.00%     89.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4322449      2.04%     91.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 18296919      8.64%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            211691341                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.482302                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.968298                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 53244805                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              33622636                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 100506105                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1219607                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               23098188                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             14186059                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                166456                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              422686981                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                695509                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               23098188                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 62205667                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  461892                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       28663713                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  92688664                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4573217                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              388586256                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                  22473                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2248529                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           666261253                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1656600047                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1638859233                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          17740814                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             298061848                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                368199405                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2723713                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2675909                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  23519864                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             46897665                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16902365                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3883401                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2525721                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  332696460                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2225712                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 261853052                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            956132                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       143515224                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    342118821                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         589705                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     211691341                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.236957                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.489139                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            97854722     46.23%     46.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            37874169     17.89%     64.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34110087     16.11%     80.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            22786114     10.76%     90.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            11453676      5.41%     96.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4761165      2.25%     98.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2318956      1.10%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              393514      0.19%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              138938      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       211691341                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  398184     18.25%     18.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5522      0.25%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                54      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc               48      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1324595     60.71%     79.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                453293     20.78%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             204944335     78.27%     78.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               928862      0.35%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33072      0.01%     78.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          166569      0.06%     78.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          257495      0.10%     78.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76397      0.03%     78.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         468208      0.18%     79.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         207568      0.08%     79.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71821      0.03%     79.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt            325      0.00%     79.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             40739224     15.56%     94.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13959176      5.33%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              261853052                       # Type of FU issued
+system.cpu.iq.rate                           1.236615                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2181696                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008332                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          734785745                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         476212492                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    242882419                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3749528                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2237188                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1845400                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              262148601                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1886147                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1588917                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     17045968                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        31330                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        12732                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4255519                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads           19                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             1                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               23098188                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   13857                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   833                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           334975630                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           3751995                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              46897665                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16902365                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2201836                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    328                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   255                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          12732                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        9997150                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1695546                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11692696                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             249230612                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              38607191                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          12622440                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         53458                       # number of nop insts executed
+system.cpu.iew.exec_refs                     52205543                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 52589382                       # Number of branches executed
+system.cpu.iew.exec_stores                   13598352                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.177005                       # Inst execution rate
+system.cpu.iew.wb_sent                      246260336                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     244727819                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 148531018                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 247826872                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.155740                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.599334                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      188681960                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       146293697                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1636007                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9795278                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    188593154                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.000471                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.681076                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    105401505     55.89%     55.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     40855723     21.66%     77.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     19482895     10.33%     87.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8763575      4.65%     92.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4920568      2.61%     95.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2013461      1.07%     96.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1707502      0.91%     97.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1008267      0.53%     97.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4439658      2.35%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    188593154                       # Number of insts commited each cycle
+system.cpu.commit.count                     188681960                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       42498543                       # Number of memory references committed
+system.cpu.commit.loads                      29851697                       # Number of loads committed
+system.cpu.commit.membars                       22408                       # Number of memory barriers committed
+system.cpu.commit.branches                   40283895                       # Number of branches committed
+system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 150115073                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               4439658                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    519123952                       # The number of ROB reads
+system.cpu.rob.rob_writes                   693113124                       # The number of ROB writes
+system.cpu.timesIdled                            1721                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           58510                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   188667572                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             188667572                       # Number of Instructions Simulated
+system.cpu.cpi                               1.122344                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.122344                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.890993                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.890993                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1112090730                       # number of integer regfile reads
+system.cpu.int_regfile_writes               407417013                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2928432                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2499453                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               503028333                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 824460                       # number of misc regfile writes
+system.cpu.icache.replacements                   1929                       # number of replacements
+system.cpu.icache.tagsinuse               1329.893683                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 40620654                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3638                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               11165.655305                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1329.893683                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.649362                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               40620654                       # number of ReadReq hits
+system.cpu.icache.demand_hits                40620654                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               40620654                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 4232                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  4232                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 4232                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      101343500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       101343500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      101343500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           40624886                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            40624886                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           40624886                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000104                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000104                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000104                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 23946.951796                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 23946.951796                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 23946.951796                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               594                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                594                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               594                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3638                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3638                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3638                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     74666000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     74666000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     74666000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000090                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000090                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000090                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 20523.914239                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 20523.914239                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 20523.914239                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     55                       # number of replacements
+system.cpu.dcache.tagsinuse               1403.749083                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 48644661                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1849                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               26308.632234                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1403.749083                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.342712                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               36235521                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              12356728                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            27793                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             24619                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                48592249                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               48592249                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1802                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                7559                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses                  9361                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 9361                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       59198500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     237194000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        63500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency       296392500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      296392500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           36237323                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        27795                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         24619                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            48601610                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           48601610                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000050                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000611                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000072                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.000193                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000193                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 32851.553829                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 31379.018389                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        31750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 31662.482641                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 31662.482641                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        20000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        20000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                       19                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              1044                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             6468                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               7512                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              7512                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             758                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1091                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1849                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1849                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     24153000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     38344000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     62497000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     62497000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000021                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000038                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000038                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31864.116095                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33800.432666                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33800.432666                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              1924.111202                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1711                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2681                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.638195                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1920.073953                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             4.037248                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.058596                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000123                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  1711                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                  19                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                   9                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   1720                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  1720                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                2685                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1082                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 3767                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                3767                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      92055500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     37184500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      129240000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     129240000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              4396                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses              19                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1091                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               5487                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              5487                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.610783                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.991751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.686532                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.686532                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34285.102421                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.451017                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34308.468277                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34308.468277                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               14                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           2671                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            3753                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           3753                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     83018000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     33590000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    116608000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    116608000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.607598                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.991751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.683980                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.683980                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.242980                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.610179                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.610179                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..01def30a3
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..f2a9f0661
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:50:48
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 103106771000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..079a70f11
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.103107                       # Number of seconds simulated
+sim_ticks                                103106771000                       # Number of ticks simulated
+final_tick                               103106771000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3006793                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1643182108                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213456                       # Number of bytes of host memory used
+host_seconds                                    62.75                       # Real time elapsed on the host
+sim_insts                                   188670900                       # Number of instructions simulated
+system.physmem.bytes_read                   869973902                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              759440240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 45252940                       # Number of bytes written to this memory
+system.physmem.num_reads                    219482514                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    12386694                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8437602047                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7365570977                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     438893969                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    8876496016                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        206213543                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        188670900                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
+system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     31949383                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    150106226                       # number of integer instructions
+system.cpu.num_fp_insts                       1752310                       # number of float instructions
+system.cpu.num_int_register_reads           809396650                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          294073530                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      42494120                       # number of memory refs
+system.cpu.num_load_insts                    29849485                       # Number of load instructions
+system.cpu.num_store_insts                   12644635                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  206213543                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..3f54c6512
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..b21763742
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:52:01
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 232077154000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..d861ddab1
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,279 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.232077                       # Number of seconds simulated
+sim_ticks                                232077154000                       # Number of ticks simulated
+final_tick                               232077154000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1497030                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1846187485                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222460                       # Number of bytes of host memory used
+host_seconds                                   125.71                       # Real time elapsed on the host
+sim_insts                                   188185929                       # Number of instructions simulated
+system.physmem.bytes_read                      220992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 110656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         3453                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                         952235                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    476807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                        952235                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        464154308                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        188185929                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
+system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     31949383                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    150106226                       # number of integer instructions
+system.cpu.num_fp_insts                       1752310                       # number of float instructions
+system.cpu.num_int_register_reads           898652287                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          294073530                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      42494120                       # number of memory refs
+system.cpu.num_load_insts                    29849485                       # Number of load instructions
+system.cpu.num_store_insts                   12644635                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  464154308                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   1506                       # number of replacements
+system.cpu.icache.tagsinuse               1147.981155                       # Cycle average of tags in use
+system.cpu.icache.total_refs                189857010                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               62227.797443                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1147.981155                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.560538                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              189857010                       # number of ReadReq hits
+system.cpu.icache.demand_hits               189857010                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              189857010                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 3051                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  3051                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 3051                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      115332000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       115332000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      115332000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          189860061                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           189860061                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          189860061                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000016                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000016                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 37801.376598                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 37801.376598                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 37801.376598                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3051                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3051                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3051                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    106179000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    106179000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    106179000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000016                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000016                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000016                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     40                       # number of replacements
+system.cpu.dcache.tagsinuse               1363.604315                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 42007359                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1789                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               23480.916154                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1363.604315                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.332911                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               29599358                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              12363187                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            22407                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             22407                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                41962545                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               41962545                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  689                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                1100                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  1789                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 1789                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       36190000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      61264000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency        97454000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       97454000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           29600047                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            41964334                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           41964334                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000023                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000089                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000043                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000043                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                       16                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             689                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1100                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1789                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1789                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     34123000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     57964000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     92087000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     92087000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000023                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000043                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000043                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              1675.648030                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1379                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.582102                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1672.609981                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             3.038048                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.051044                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  1379                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                  16                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   1387                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  1387                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                2361                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1092                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 3453                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                3453                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     122772000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     56784000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      179556000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     179556000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              3740                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses              16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1100                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               4840                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              4840                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.631283                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.992727                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.713430                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.713430                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           2361                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1092                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            3453                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           3453                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     94440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     43680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    138120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    138120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.631283                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.713430                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.713430                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..5551fc718
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
new file mode 100755
index 000000000..5a1dc45d3
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:25:10
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+info: Increasing stack size by one page.
+122 123 124 Exiting @ tick 96722951500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..fabf573dd
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.096723                       # Number of seconds simulated
+sim_ticks                                 96722951500                       # Number of ticks simulated
+final_tick                                96722951500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3381365                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1690691780                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210080                       # Number of bytes of host memory used
+host_seconds                                    57.21                       # Real time elapsed on the host
+sim_insts                                   193444769                       # Number of instructions simulated
+system.physmem.bytes_read                   997245606                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              773782192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 72065412                       # Number of bytes written to this memory
+system.physmem.num_reads                    251180617                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    18976439                       # Number of write requests responded to by this memory
+system.physmem.num_other                        22406                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    10310330594                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7999985319                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     745070440                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   11055401034                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  401                       # Number of system calls
+system.cpu.numCycles                        193445904                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        193444769                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             167974818                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
+system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8665107                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    167974818                       # number of integer instructions
+system.cpu.num_fp_insts                       1970372                       # number of float instructions
+system.cpu.num_int_register_reads           352617963                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          163060137                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      76733959                       # number of memory refs
+system.cpu.num_load_insts                    57735092                       # Number of load instructions
+system.cpu.num_store_insts                   18998867                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  193445904                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
new file mode 100644
index 000000000..2d0b36d34
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
new file mode 100755
index 000000000..e7f89f9a0
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:26:18
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+info: Increasing stack size by one page.
+122 123 124 Exiting @ tick 270576960000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..16bfeed42
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -0,0 +1,242 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.270577                       # Number of seconds simulated
+sim_ticks                                270576960000                       # Number of ticks simulated
+final_tick                               270576960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1675606                       # Simulator instruction rate (inst/s)
+host_tick_rate                             2343719954                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218792                       # Number of bytes of host memory used
+host_seconds                                   115.45                       # Real time elapsed on the host
+sim_insts                                   193444769                       # Number of instructions simulated
+system.physmem.bytes_read                      331072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 230208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         5173                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        1223578                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    850804                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       1223578                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  401                       # Number of system calls
+system.cpu.numCycles                        541153920                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        193444769                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             167974818                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
+system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8665107                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    167974818                       # number of integer instructions
+system.cpu.num_fp_insts                       1970372                       # number of float instructions
+system.cpu.num_int_register_reads           352617963                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          163060136                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      76733959                       # number of memory refs
+system.cpu.num_load_insts                    57735092                       # Number of load instructions
+system.cpu.num_store_insts                   18998867                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  541153920                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                  10362                       # number of replacements
+system.cpu.icache.tagsinuse               1591.571713                       # Cycle average of tags in use
+system.cpu.icache.total_refs                193433261                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  12288                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               15741.639079                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1591.571713                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.777135                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              193433261                       # number of ReadReq hits
+system.cpu.icache.demand_hits               193433261                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              193433261                       # number of overall hits
+system.cpu.icache.ReadReq_misses                12288                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 12288                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                12288                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      323106000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       323106000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      323106000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          193445549                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           193445549                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          193445549                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000064                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000064                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000064                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 26294.433594                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 26294.433594                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 26294.433594                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           12288                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            12288                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           12288                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    286242000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    286242000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    286242000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000064                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000064                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000064                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                      2                       # number of replacements
+system.cpu.dcache.tagsinuse               1237.197455                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 76732338                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1576                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               48688.031726                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1237.197455                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.302050                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               57734571                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              18975362                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits                  22405                       # number of SwapReq hits
+system.cpu.dcache.demand_hits                76709933                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               76709933                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  498                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                1077                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses                    1                       # number of SwapReq misses
+system.cpu.dcache.demand_misses                  1575                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 1575                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       27888000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      60312000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency          56000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency        88200000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       88200000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           57735069                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          18976439                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses              22406                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            76711508                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           76711508                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000057                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate          0.000045                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate           0.000021                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000021                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                        2                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             498                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1077                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses               1                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1575                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1575                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     26394000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     57081000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency        53000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     83475000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     83475000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000057                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.000045                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000021                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000021                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              2678.327135                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    8691                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4097                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.121308                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2678.326682                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             0.000454                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.081736                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000000                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  8691                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                   2                       # number of Writeback hits
+system.cpu.l2cache.demand_hits                   8691                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  8691                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4095                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1078                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 5173                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                5173                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     212940000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     56056000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      268996000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     268996000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             12786                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses               2                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1078                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              13864                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             13864                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.320272                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.373125                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.373125                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           4095                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1078                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            5173                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           5173                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    163800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     43120000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    206920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    206920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.320272                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.373125                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.373125                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
new file mode 100644
index 000000000..0cd9938ef
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
new file mode 100755
index 000000000..1f9424384
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 07:52:38
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
+Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 96689893000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1 b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2 b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2 b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..71e8505e4
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -0,0 +1,486 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.096690                       # Number of seconds simulated
+sim_ticks                                 96689893000                       # Number of ticks simulated
+final_tick                                96689893000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 118200                       # Simulator instruction rate (inst/s)
+host_tick_rate                               51629155                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224032                       # Number of bytes of host memory used
+host_seconds                                  1872.78                       # Real time elapsed on the host
+sim_insts                                   221363017                       # Number of instructions simulated
+system.physmem.bytes_read                      340224                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 215424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         5316                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        3518713                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   2227989                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       3518713                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        193379787                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 25818202                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           25818202                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2898724                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              23602930                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 20841363                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           30995459                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      261573615                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    25818202                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           20841363                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      70808397                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26924712                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               67767699                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  120                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1017                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  28859729                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                549788                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          193293197                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.259018                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.335260                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                124336745     64.33%     64.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4112034      2.13%     66.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3238737      1.68%     68.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4462671      2.31%     70.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4295145      2.22%     72.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4476640      2.32%     74.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5418723      2.80%     77.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3020771      1.56%     79.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 39931731     20.66%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            193293197                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.133510                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.352642                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 44764810                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              57827624                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  57161965                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9818293                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               23720505                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              424367292                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               23720505                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 53388300                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                14632169                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          21921                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  57615812                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              43914490                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              411765049                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    18                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               19034939                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              22478875                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           438156432                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1066580371                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1055689317                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          10891054                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                203793023                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1794                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1788                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  94980657                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            104262380                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37289638                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          67232013                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         21668119                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  396788007                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2705                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 287703359                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            254770                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       174855842                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    350938331                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1459                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     193293197                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.488430                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.480803                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            60724695     31.42%     31.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            54019027     27.95%     59.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            35712551     18.48%     77.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            21012235     10.87%     88.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            13686479      7.08%     95.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             5222239      2.70%     98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2184583      1.13%     99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              593188      0.31%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              138200      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       193293197                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  110269      4.01%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2317531     84.31%     88.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                321034     11.68%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass           1208234      0.42%      0.42% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             187072997     65.02%     65.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1650386      0.57%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             73223880     25.45%     91.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            24547862      8.53%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              287703359                       # Type of FU issued
+system.cpu.iq.rate                           1.487763                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2748834                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009554                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          766190945                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         566572341                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    278374724                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             5512574                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            5407408                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2648186                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              286471551                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2772408                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18351013                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     47612790                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        32223                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       339608                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     16773922                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads        46155                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               23720505                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  359624                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                213865                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           396790712                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            135718                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             104262380                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37289638                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1786                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 119790                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 15845                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         339608                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2505263                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       598160                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3103423                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             283855997                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              71689961                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3847362                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                     95739480                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15662592                       # Number of branches executed
+system.cpu.iew.exec_stores                   24049519                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.467868                       # Inst execution rate
+system.cpu.iew.wb_sent                      282319460                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     281022910                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 227917239                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 378870882                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.453218                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.601570                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      221363017                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       175435625                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           2898838                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    169572692                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.305417                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.741291                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     63662174     37.54%     37.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     62350604     36.77%     74.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15592003      9.19%     83.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11999288      7.08%     90.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5440588      3.21%     93.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2982193      1.76%     95.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2011991      1.19%     96.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1185528      0.70%     97.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4348323      2.56%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    169572692                       # Number of insts commited each cycle
+system.cpu.commit.count                     221363017                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       77165306                       # Number of memory references committed
+system.cpu.commit.loads                      56649590                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   12326943                       # Number of branches committed
+system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               4348323                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    562023011                       # The number of ROB reads
+system.cpu.rob.rob_writes                   817360743                       # The number of ROB writes
+system.cpu.timesIdled                            1880                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           86590                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   221363017                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             221363017                       # Number of Instructions Simulated
+system.cpu.cpi                               0.873587                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.873587                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.144706                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.144706                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                530675330                       # number of integer regfile reads
+system.cpu.int_regfile_writes               288962100                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3614411                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2302807                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               149913222                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
+system.cpu.icache.replacements                   4227                       # number of replacements
+system.cpu.icache.tagsinuse               1595.324923                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 28852140                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   6194                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                4658.078786                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1595.324923                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.778967                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               28852140                       # number of ReadReq hits
+system.cpu.icache.demand_hits                28852140                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               28852140                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 7589                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  7589                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 7589                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      174464500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       174464500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      174464500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           28859729                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            28859729                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           28859729                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000263                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000263                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000263                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 22989.129003                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 22989.129003                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 22989.129003                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1125                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1125                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1125                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            6464                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             6464                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            6464                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    125677000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    125677000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    125677000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000224                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000224                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000224                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 19442.605198                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 19442.605198                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 19442.605198                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     59                       # number of replacements
+system.cpu.dcache.tagsinuse               1416.877097                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 73598603                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1986                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               37058.712487                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1416.877097                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.345917                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               53090649                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              20507453                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                73598102                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               73598102                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  848                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                8277                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  9125                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 9125                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       26447500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     228348000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       254795500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      254795500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           53091497                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            73607227                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           73607227                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000403                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000124                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000124                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 31188.089623                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27588.256615                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 27922.794521                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 27922.794521                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                       14                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits               424                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             6443                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               6867                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              6867                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             424                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1834                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             2258                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            2258                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     13981500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     64146500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     78128000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     78128000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000031                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000031                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32975.235849                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34976.281352                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34600.531444                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34600.531444                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              2499.166941                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    2858                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3763                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.759500                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2497.181729                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             1.985212                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.076208                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000061                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  2857                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                  14                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   2865                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  2865                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3759                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses              270                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses              1557                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 5316                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                5316                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     128731000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     53240500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      181971500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     181971500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              6616                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses              14                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses            270                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1565                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               8181                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              8181                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.568168                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.994888                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.649798                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.649798                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34246.076084                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34194.283879                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34230.906697                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34230.906697                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           3759                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses          270                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1557                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            5316                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           5316                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    116600500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency      8370000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     48374500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    164975000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    164975000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.568168                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994888                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.649798                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.649798                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.021016                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.043031                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.671934                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.671934                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..4d9868de9
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
new file mode 100755
index 000000000..3217ab200
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 08:24:02
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 131393100000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..39967f660
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.131393                       # Number of seconds simulated
+sim_ticks                                131393100000                       # Number of ticks simulated
+final_tick                               131393100000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1953897                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1159762651                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211876                       # Number of bytes of host memory used
+host_seconds                                   113.29                       # Real time elapsed on the host
+sim_insts                                   221363018                       # Number of instructions simulated
+system.physmem.bytes_read                  1698379042                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read             1387955288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 99822189                       # Number of bytes written to this memory
+system.physmem.num_reads                    230176419                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    20515730                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    12925937831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read               10563380330                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     759721698                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   13685659529                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        262786201                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        221363018                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             220339607                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8268471                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    220339607                       # number of integer instructions
+system.cpu.num_fp_insts                       2162459                       # number of float instructions
+system.cpu.num_int_register_reads           567557364                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          232532006                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      77165306                       # number of memory refs
+system.cpu.num_load_insts                    56649590                       # Number of load instructions
+system.cpu.num_store_insts                   20515716                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  262786201                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
new file mode 100644
index 000000000..d7a510398
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
new file mode 100755
index 000000000..a3170a407
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -0,0 +1,27 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 08:26:06
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 250960631000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0  4 26  0 1
+$COUNT_1/$AND2_3/$IV_1 4 0  8 26  2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0  14 26  0 1
+ACOUNT_1 14 0  18 26  2 1
+twfeed1 18 0  22 26  0 1
+$COUNT_1/$FJK3_1 22 0  86 26  0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52  6 78  0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52  12 78  2 2
+$COUNT_1/$AND2_2/$IV_1 12 52  16 78  2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52  22 78  2 2
+$COUNT_1/$FJK3_2 22 52  86 78  0 2
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0  86 26  0 0
+2 0 52  86 78  0 0
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1  pin2 7 0 0
+net 2
+segment channel 3
+pin1 41  pin2 42 0 0
+segment channel 2
+pin1 12  pin2 3 0 0
+net 3
+segment channel 2
+pin1 35  pin2 36 0 0
+segment channel 2
+pin1 19  pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5  pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14  pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23  pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25  pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..1c9d2c1e6
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -0,0 +1,233 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.250961                       # Number of seconds simulated
+sim_ticks                                250960631000                       # Number of ticks simulated
+final_tick                               250960631000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1263573                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1432520595                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220856                       # Number of bytes of host memory used
+host_seconds                                   175.19                       # Real time elapsed on the host
+sim_insts                                   221363018                       # Number of instructions simulated
+system.physmem.bytes_read                      303040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 181760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         4735                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        1207520                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    724257                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       1207520                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        501921262                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        221363018                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             220339607                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
+system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      8268471                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    220339607                       # number of integer instructions
+system.cpu.num_fp_insts                       2162459                       # number of float instructions
+system.cpu.num_int_register_reads           567557364                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          232532006                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      77165306                       # number of memory refs
+system.cpu.num_load_insts                    56649590                       # Number of load instructions
+system.cpu.num_store_insts                   20515716                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  501921262                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   2836                       # number of replacements
+system.cpu.icache.tagsinuse               1455.289108                       # Cycle average of tags in use
+system.cpu.icache.total_refs                173489718                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   4694                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               36959.888794                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1455.289108                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.710590                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              173489718                       # number of ReadReq hits
+system.cpu.icache.demand_hits               173489718                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              173489718                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 4694                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  4694                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 4694                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      185041500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       185041500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      185041500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          173494412                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           173494412                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          173494412                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000027                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000027                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000027                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 39420.856412                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 39420.856412                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 39420.856412                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            4694                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             4694                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            4694                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    170928000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    170928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    170928000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000027                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000027                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000027                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     41                       # number of replacements
+system.cpu.dcache.tagsinuse               1363.451495                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 77195833                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1905                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               40522.746982                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1363.451495                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.332874                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               56681681                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              20514152                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                77195833                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               77195833                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  327                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                1578                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  1905                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 1905                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       18020000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      88242000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       106262000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      106262000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           56682008                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            77197738                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           77197738                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000077                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 55780.577428                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 55780.577428                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                        7                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             327                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1578                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1905                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1905                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     17038500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     83508000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    100546500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    100546500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000077                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              2058.168190                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1861                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3164                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.588180                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2058.146434                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             0.021756                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.062810                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000001                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  1861                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                   7                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                   3                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   1864                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  1864                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3160                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1575                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 4735                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                4735                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     164335500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     81900000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      246235500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     246235500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              5021                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses               7                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1578                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               6599                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              6599                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.629357                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.998099                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.717533                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.717533                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52003.273495                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52003.273495                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           3160                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1575                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            4735                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           4735                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    126400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     63000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    189400000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    189400000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.629357                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.998099                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.717533                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.717533                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/test.py b/tests/long/se/70.twolf/test.py
new file mode 100644
index 000000000..761ec8b2e
--- /dev/null
+++ b/tests/long/se/70.twolf/test.py
@@ -0,0 +1,47 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import twolf
+import os
+
+workload = twolf(isa, opsys, 'smred')
+root.system.cpu.workload = workload.makeLiveProcess()
+cwd = root.system.cpu.workload[0].cwd
+
+#Remove two files who's presence or absence affects execution
+sav_file = os.path.join(cwd, workload.input_set + '.sav')
+sv2_file = os.path.join(cwd, workload.input_set + '.sv2')
+try:
+    os.unlink(sav_file)
+except:
+    print "Couldn't unlink ", sav_file
+try:
+    os.unlink(sv2_file)
+except:
+    print "Couldn't unlink ", sv2_file