diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/se | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/se')
47 files changed, 11142 insertions, 10985 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index fd7ad70a0..239f60df1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,9 +699,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/mcf +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:268435455 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index c4b7fa411..f37d93ec9 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:10:45 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:33:12 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x50d0380 + 0: system.cpu.isa: ISA system set to: 0 0x666d940 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -24,4 +24,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 26911921000 because target called exit() +Exiting @ tick 26894328500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index a24a01894..b6a9feb5d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026909 # Number of seconds simulated -sim_ticks 26909234500 # Number of ticks simulated -final_tick 26909234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026894 # Number of seconds simulated +sim_ticks 26894328500 # Number of ticks simulated +final_tick 26894328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142304 # Simulator instruction rate (inst/s) -host_op_rate 143325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42270537 # Simulator tick rate (ticks/s) -host_mem_usage 446544 # Number of bytes of host memory used -host_seconds 636.60 # Real time elapsed on the host +host_inst_rate 165934 # Simulator instruction rate (inst/s) +host_op_rate 167125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49262466 # Simulator tick rate (ticks/s) +host_mem_usage 394132 # Number of bytes of host memory used +host_seconds 545.94 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 45184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory system.physmem.bytes_read::total 992640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 45184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45184 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1671991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35216461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36888452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1671991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1671991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1671991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35216461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36888452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1680057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35228840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36908897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1680057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1680057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1680057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35228840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36908897 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15510 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue @@ -40,22 +40,22 @@ system.physmem.bytesReadSys 992640 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 987 # Per bank write bursts system.physmem.perBankRdBursts::1 885 # Per bank write bursts system.physmem.perBankRdBursts::2 942 # Per bank write bursts -system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::3 1029 # Per bank write bursts +system.physmem.perBankRdBursts::4 1048 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1080 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 957 # Per bank write bursts -system.physmem.perBankRdBursts::10 935 # Per bank write bursts +system.physmem.perBankRdBursts::10 936 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 905 # Per bank write bursts -system.physmem.perBankRdBursts::13 865 # Per bank write bursts -system.physmem.perBankRdBursts::14 877 # Per bank write bursts +system.physmem.perBankRdBursts::13 863 # Per bank write bursts +system.physmem.perBankRdBursts::14 876 # Per bank write bursts system.physmem.perBankRdBursts::15 896 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26909036500 # Total gap between requests +system.physmem.totGap 26894128500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 726.491563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 533.334896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.223532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 140 10.27% 10.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 158 11.59% 21.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56 4.11% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.99% 30.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 4.18% 35.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.86% 38.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 1.76% 39.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.86% 42.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 782 57.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1363 # Bytes accessed per row activation -system.physmem.totQLat 83369750 # Total ticks spent queuing -system.physmem.totMemAccLat 374182250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 726.489019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 530.637647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.552146 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 153 11.20% 11.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146 10.69% 21.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 54 3.95% 25.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 4.76% 30.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 4.17% 34.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 3.00% 37.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 2.56% 40.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.42% 42.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 782 57.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1366 # Bytes accessed per row activation +system.physmem.totQLat 88775250 # Total ticks spent queuing +system.physmem.totMemAccLat 379587750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5375.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5723.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24125.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24473.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage @@ -216,44 +216,44 @@ system.physmem.busUtilRead 0.29 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14137 # Number of row buffer hits during reads +system.physmem.readRowHits 14143 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads +system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734947.55 # Average gap between requests -system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 24303660500 # Time in different power states -system.physmem.memoryStateTime::REF 898300000 # Time in different power states +system.physmem.avgGap 1733986.36 # Average gap between requests +system.physmem.pageHitRate 91.19 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 24303280500 # Time in different power states +system.physmem.memoryStateTime::REF 898040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1704463000 # Time in different power states +system.physmem.memoryStateTime::ACT 1692660750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 36888452 # Throughput (bytes/s) +system.membus.throughput 36908897 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 972 # Transaction distribution system.membus.trans_dist::ReadResp 972 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31026 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31026 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31022 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 992640 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19094500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 18401000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145899997 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145166999 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 26684247 # Number of BP lookups -system.cpu.branchPred.condPredicted 22003797 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 841589 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11372801 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11278925 # Number of BTB hits +system.cpu.branchPred.lookups 27364118 # Number of BP lookups +system.cpu.branchPred.condPredicted 22575249 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 843312 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11626081 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11546341 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.174557 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69990 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.314128 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70079 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 187 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,239 +339,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53818470 # number of cpu cycles simulated +system.cpu.numCycles 53788658 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14166768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127874482 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26684247 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11348915 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24030832 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4761225 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11326508 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14474692 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 130915195 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27364118 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11616420 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24576695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5106515 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 9886759 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13838942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329737 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53427318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409937 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14156505 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 349331 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53187301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.478661 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.235073 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29434889 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3387974 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2027945 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1552978 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1665988 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2918810 5.46% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1512193 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1089826 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9836715 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 28648969 53.86% 53.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3469200 6.52% 60.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2052434 3.86% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1567853 2.95% 67.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1679873 3.16% 70.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3021837 5.68% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1566641 2.95% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1116795 2.10% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10063699 18.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53427318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495820 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.376033 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16930628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9172800 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22402161 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1027234 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3894495 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4441775 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8644 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126055074 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42561 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3894495 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18710503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3595532 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 186271 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21547494 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5493023 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123139917 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 426575 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4604902 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1527 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143588109 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536432016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499923969 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 641 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53187301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.508734 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.433881 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16310855 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8657573 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23455900 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 522552 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4240421 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4543490 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8671 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 129206748 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42514 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4240421 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17921369 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2850180 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 191379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 22351654 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5632298 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 126131712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1889841 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 3251328 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 563418 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3246 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 146876533 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 549573070 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 512042051 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 826 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36173923 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4624 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4622 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12547663 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29472846 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5519091 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2169224 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1269381 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118159243 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8489 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105145248 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78272 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26728441 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65602174 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 271 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53427318 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968005 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908888 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 39462347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4633 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4631 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9072079 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30275485 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5599467 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2184620 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1363504 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 120806561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8485 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105954089 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 91175 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 29372689 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73925597 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 267 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53187301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.992094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.919550 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15370604 28.77% 28.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11662585 21.83% 50.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8230563 15.41% 66.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6832993 12.79% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4979120 9.32% 88.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2926966 5.48% 93.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2444206 4.57% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 536236 1.00% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 444045 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15526622 29.19% 29.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10753574 20.22% 49.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8641028 16.25% 65.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6157106 11.58% 77.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5949684 11.19% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2742880 5.16% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2429206 4.57% 98.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 538839 1.01% 99.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 448362 0.84% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53427318 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53187301 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 46059 6.94% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 26 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 341162 51.43% 58.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276052 41.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 44574 8.99% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 174239 35.13% 44.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277108 55.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74418244 70.78% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 122 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 157 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25603497 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5112252 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 75094311 70.87% 70.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10550 0.01% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 140 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 196 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25720178 24.27% 95.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5128709 4.84% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105145248 # Type of FU issued -system.cpu.iq.rate 1.953702 # Inst issue rate -system.cpu.iq.fu_busy_cnt 663299 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006308 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264458762 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144900942 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102674293 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 623 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 845 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 263 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105808235 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 312 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 440410 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105954089 # Type of FU issued +system.cpu.iq.rate 1.969822 # Inst issue rate +system.cpu.iq.fu_busy_cnt 495948 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004681 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 265681854 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 150192687 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 103425723 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 748 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1061 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 319 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106449666 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 371 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 469381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6898880 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6071 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6331 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 774247 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7701519 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7870 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6982 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 854623 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31563 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 30068 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3894495 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 960394 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127228 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118180427 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309851 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29472846 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5519091 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4601 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65954 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6808 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6331 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446096 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445462 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 891558 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104169534 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25284727 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 975714 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4240421 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 731718 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 478226 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 120827778 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309730 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30275485 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5599467 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4597 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 72415 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 359917 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6982 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447833 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 447193 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 895026 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104954211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25387781 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 999878 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12695 # number of nop insts executed -system.cpu.iew.exec_refs 30339844 # number of memory reference insts executed -system.cpu.iew.exec_branches 21324580 # Number of branches executed -system.cpu.iew.exec_stores 5055117 # Number of stores executed -system.cpu.iew.exec_rate 1.935572 # Inst execution rate -system.cpu.iew.wb_sent 102952816 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102674556 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62244775 # num instructions producing a value -system.cpu.iew.wb_consumers 104288684 # num instructions consuming a value +system.cpu.iew.exec_nop 12732 # number of nop insts executed +system.cpu.iew.exec_refs 30458601 # number of memory reference insts executed +system.cpu.iew.exec_branches 21526378 # Number of branches executed +system.cpu.iew.exec_stores 5070820 # Number of stores executed +system.cpu.iew.exec_rate 1.951233 # Inst execution rate +system.cpu.iew.wb_sent 103717343 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 103426042 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62672484 # num instructions producing a value +system.cpu.iew.wb_consumers 105780863 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907794 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596851 # average fanout of values written-back +system.cpu.iew.wb_rate 1.922823 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.592475 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26930418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 29588025 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 833018 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49532823 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842273 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541112 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834722 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 48946880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.864326 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.553843 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20056290 40.49% 40.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13134081 26.52% 67.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4165062 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431851 6.93% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1531687 3.09% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 719294 1.45% 86.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 966848 1.95% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 252784 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5274926 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19590544 40.02% 40.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13003525 26.57% 66.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4154420 8.49% 75.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3492472 7.14% 82.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1473630 3.01% 85.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 727145 1.49% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 923215 1.89% 88.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 261788 0.53% 89.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5320141 10.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49532823 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 48946880 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -617,238 +618,236 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction -system.cpu.commit.bw_lim_events 5274926 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5320141 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162435541 # The number of ROB reads -system.cpu.rob.rob_writes 240280947 # The number of ROB writes -system.cpu.timesIdled 46113 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 391152 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 164461990 # The number of ROB reads +system.cpu.rob.rob_writes 245943119 # The number of ROB writes +system.cpu.timesIdled 58216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 601357 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.594090 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594090 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683247 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683247 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495503749 # number of integer regfile reads -system.cpu.int_regfile_writes 120538753 # number of integer regfile writes -system.cpu.fp_regfile_reads 136 # number of floating regfile reads -system.cpu.fp_regfile_writes 324 # number of floating regfile writes -system.cpu.misc_regfile_reads 29202777 # number of misc regfile reads +system.cpu.cpi 0.593761 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.593761 # CPI: Total CPI of All Threads +system.cpu.ipc 1.684180 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.684180 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 499033245 # number of integer regfile reads +system.cpu.int_regfile_writes 121427335 # number of integer regfile writes +system.cpu.fp_regfile_reads 166 # number of floating regfile reads +system.cpu.fp_regfile_writes 402 # number of floating regfile writes +system.cpu.misc_regfile_reads 29301616 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4498112646 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904542 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942913 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43808 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838157 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888546500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4500548582 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 907410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 907410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 40933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 40933 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120992384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121039168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121039168 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888514500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1214249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1215999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424437743 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424171240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 629.782020 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13837957 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 727 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19034.328748 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 631.006365 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14155509 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 731 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19364.581395 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 629.782020 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.307511 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.307511 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 723 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 671 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.353027 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27678613 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27678613 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13837957 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13837957 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13837957 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13837957 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13837957 # number of overall hits -system.cpu.icache.overall_hits::total 13837957 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses -system.cpu.icache.overall_misses::total 984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66510498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66510498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66510498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66510498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66510498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66510498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13838941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13838941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13838941 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13838941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13838941 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13838941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67591.969512 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67591.969512 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67591.969512 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67591.969512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67591.969512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67591.969512 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 649 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 631.006365 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308109 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308109 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 728 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.355469 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 28313740 # Number of tag accesses +system.cpu.icache.tags.data_accesses 28313740 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 14155509 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14155509 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14155509 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14155509 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14155509 # number of overall hits +system.cpu.icache.overall_hits::total 14155509 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 995 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 995 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 995 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 995 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 995 # number of overall misses +system.cpu.icache.overall_misses::total 995 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67178998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67178998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67178998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67178998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67178998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67178998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14156504 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14156504 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14156504 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14156504 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14156504 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14156504 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67516.580905 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67516.580905 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 593 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.083333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 252 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 252 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 252 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 252 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 252 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 263 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 263 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 263 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 263 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 732 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50737500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50737500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50737500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50737500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50737500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50737500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69313.524590 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69313.524590 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69313.524590 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69313.524590 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69313.524590 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69313.524590 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50814250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50814250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50814250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50814250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50814250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50814250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # 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Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 461 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3114 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 521 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 452 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3133 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 59974850 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 59974850 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23597129 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23597129 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532332 # 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number of overall misses -system.cpu.dcache.overall_misses::total 1376342 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13892857479 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13892857479 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8552070346 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8552070346 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22444927825 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22444927825 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22444927825 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22444927825 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24770822 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24770822 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 28221779 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28221779 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28221779 # number of overall hits +system.cpu.dcache.overall_hits::total 28221779 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1169644 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1169644 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 190007 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 190007 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1359651 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1359651 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1359651 # number of overall misses +system.cpu.dcache.overall_misses::total 1359651 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13867675477 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13867675477 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8610605390 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8610605390 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 264500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 264500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22478280867 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22478280867 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22478280867 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22478280867 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24846449 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24846449 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29505803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29505803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29505803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29505803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047382 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047382 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042798 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042798 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001783 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001783 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046646 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046646 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046646 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046646 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.875127 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.875127 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42201.394263 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42201.394263 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16307.667589 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16307.667589 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16307.667589 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16307.667589 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154301 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29581430 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29581430 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29581430 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29581430 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047075 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047075 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040128 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040128 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.045963 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.045963 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.045963 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.045963 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16532.390199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16532.390199 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 136970 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23947 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 24472 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.443438 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.597009 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942913 # number of writebacks -system.cpu.dcache.writebacks::total 942913 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269863 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269863 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158857 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158857 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903830 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903830 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43792 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43792 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947622 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947622 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947622 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947622 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9993578260 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9993578260 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1330001932 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1330001932 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323580192 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11323580192 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323580192 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11323580192 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036488 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036488 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009249 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009249 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.922496 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.922496 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30370.888107 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30370.888107 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.469506 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.469506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.469506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.469506 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942895 # number of writebacks +system.cpu.dcache.writebacks::total 942895 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262958 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 262958 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 149081 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 149081 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 412039 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 412039 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 412039 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 412039 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906686 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906686 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40926 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 40926 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947612 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947612 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947612 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947612 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10019308761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10019308761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1304642257 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1304642257 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323951018 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11323951018 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323951018 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11323951018 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008643 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008643 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032034 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 0b4c31c18..0be389ad0 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -632,9 +634,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/x86/linux/mcf +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -674,27 +676,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:268435455 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index c033cc0d9..b2e148902 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 19:53:01 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 16:50:55 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 65613727000 because target called exit() +Exiting @ tick 64361067000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 7f2f06d97..7987e137b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065585 # Number of seconds simulated -sim_ticks 65585340000 # Number of ticks simulated -final_tick 65585340000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064361 # Number of seconds simulated +sim_ticks 64361067000 # Number of ticks simulated +final_tick 64361067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87128 # Simulator instruction rate (inst/s) -host_op_rate 153419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36169402 # Simulator tick rate (ticks/s) -host_mem_usage 428764 # Number of bytes of host memory used -host_seconds 1813.28 # Real time elapsed on the host +host_inst_rate 110006 # Simulator instruction rate (inst/s) +host_op_rate 193702 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44813910 # Simulator tick rate (ticks/s) +host_mem_usage 383472 # Number of bytes of host memory used +host_seconds 1436.19 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883456 # Number of bytes read from this memory -system.physmem.bytes_read::total 1947520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory -system.physmem.bytes_written::total 11200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29429 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory -system.physmem.num_writes::total 175 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 976804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28717637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29694441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 976804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 976804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 170770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 170770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 170770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 976804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28717637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29865211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30432 # Number of read requests accepted -system.physmem.writeReqs 175 # Number of write requests accepted -system.physmem.readBursts 30432 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1942848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4800 # Total number of bytes read from write queue -system.physmem.bytesWritten 10048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1947648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 64000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10944 # Number of bytes written to this memory +system.physmem.bytes_written::total 10944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1000 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 171 # Number of write requests responded to by this memory +system.physmem.num_writes::total 171 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 994390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 29256942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 30251332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 994390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 994390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 170041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 170041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 170041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 994390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 29256942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30421373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30424 # Number of read requests accepted +system.physmem.writeReqs 171 # Number of write requests accepted +system.physmem.readBursts 30424 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 171 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1942272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4864 # Total number of bytes read from write queue +system.physmem.bytesWritten 9152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1947136 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 76 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1922 # Per bank write bursts -system.physmem.perBankRdBursts::1 2061 # Per bank write bursts -system.physmem.perBankRdBursts::2 2029 # Per bank write bursts -system.physmem.perBankRdBursts::3 1929 # Per bank write bursts +system.physmem.perBankRdBursts::0 1923 # Per bank write bursts +system.physmem.perBankRdBursts::1 2059 # Per bank write bursts +system.physmem.perBankRdBursts::2 2030 # Per bank write bursts +system.physmem.perBankRdBursts::3 1927 # Per bank write bursts system.physmem.perBankRdBursts::4 2025 # Per bank write bursts -system.physmem.perBankRdBursts::5 1900 # Per bank write bursts -system.physmem.perBankRdBursts::6 1964 # Per bank write bursts +system.physmem.perBankRdBursts::5 1901 # Per bank write bursts +system.physmem.perBankRdBursts::6 1962 # Per bank write bursts system.physmem.perBankRdBursts::7 1863 # Per bank write bursts -system.physmem.perBankRdBursts::8 1940 # Per bank write bursts -system.physmem.perBankRdBursts::9 1934 # Per bank write bursts +system.physmem.perBankRdBursts::8 1938 # Per bank write bursts +system.physmem.perBankRdBursts::9 1933 # Per bank write bursts system.physmem.perBankRdBursts::10 1804 # Per bank write bursts system.physmem.perBankRdBursts::11 1796 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1820 # Per bank write bursts +system.physmem.perBankRdBursts::14 1817 # Per bank write bursts system.physmem.perBankRdBursts::15 1778 # Per bank write bursts -system.physmem.perBankWrBursts::0 7 # Per bank write bursts -system.physmem.perBankWrBursts::1 84 # Per bank write bursts -system.physmem.perBankWrBursts::2 9 # Per bank write bursts -system.physmem.perBankWrBursts::3 29 # Per bank write bursts -system.physmem.perBankWrBursts::4 7 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 9 # Per bank write bursts +system.physmem.perBankWrBursts::1 79 # Per bank write bursts +system.physmem.perBankWrBursts::2 8 # Per bank write bursts +system.physmem.perBankWrBursts::3 14 # Per bank write bursts +system.physmem.perBankWrBursts::4 6 # Per bank write bursts +system.physmem.perBankWrBursts::5 7 # Per bank write bursts system.physmem.perBankWrBursts::6 12 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 6 # Per bank write bursts +system.physmem.perBankWrBursts::9 5 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts @@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65585323000 # Total gap between requests +system.physmem.totGap 64361050000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30432 # Read request sizes (log2) +system.physmem.readPktSize::6 30424 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 175 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 171 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,9 +144,9 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see @@ -157,11 +157,11 @@ system.physmem.wrQLenPdf::24 9 # Wh system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,321 +193,322 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 722.766383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 519.037520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.855736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 380 14.07% 14.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 203 7.52% 21.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 114 4.22% 25.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 105 3.89% 29.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 110 4.07% 33.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 132 4.89% 38.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 83 3.07% 41.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 80 2.96% 44.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1494 55.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2701 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3366.777778 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 25.330646 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10057.961719 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.444444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.423969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.881917 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 22.22% 22.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 11.11% 33.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 6 66.67% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 122012500 # Total ticks spent queuing -system.physmem.totMemAccLat 691206250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4019.25 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 724.017831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 522.534866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.414799 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 354 13.15% 13.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 226 8.40% 21.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 117 4.35% 25.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 114 4.23% 30.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 102 3.79% 33.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 97 3.60% 37.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 103 3.83% 41.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 99 3.68% 45.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1480 54.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2692 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3785.250000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.090663 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10663.878800 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.875000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.857209 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.834523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6 75.00% 87.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 12.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads +system.physmem.totQLat 124712250 # Total ticks spent queuing +system.physmem.totMemAccLat 693737250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4109.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22769.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 22859.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 30.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 30.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.24 # Data bus utilization in percentage +system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.09 # Average write queue length when enqueuing -system.physmem.readRowHits 27699 # Number of row buffer hits during reads -system.physmem.writeRowHits 110 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.86 # Row buffer hit rate for writes -system.physmem.avgGap 2142821.02 # Average gap between requests -system.physmem.pageHitRate 91.08 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 59149173500 # Time in different power states -system.physmem.memoryStateTime::REF 2189980000 # Time in different power states +system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing +system.physmem.readRowHits 27697 # Number of row buffer hits during reads +system.physmem.writeRowHits 92 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 53.80 # Row buffer hit rate for writes +system.physmem.avgGap 2103646.02 # Average gap between requests +system.physmem.pageHitRate 91.05 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 58016949500 # Time in different power states +system.physmem.memoryStateTime::REF 2148900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 4244704000 # Time in different power states +system.physmem.memoryStateTime::ACT 4191773500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 29864235 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1427 # Transaction distribution -system.membus.trans_dist::ReadResp 1424 # Transaction distribution -system.membus.trans_dist::Writeback 175 # Transaction distribution -system.membus.trans_dist::ReadExReq 29005 # Transaction distribution -system.membus.trans_dist::ReadExResp 29005 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61036 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1958656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1958656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1958656 # Total data (bytes) +system.membus.throughput 30420378 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1422 # Transaction distribution +system.membus.trans_dist::ReadResp 1419 # Transaction distribution +system.membus.trans_dist::Writeback 171 # Transaction distribution +system.membus.trans_dist::ReadExReq 29002 # Transaction distribution +system.membus.trans_dist::ReadExResp 29002 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61016 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957888 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957888 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1957888 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1957888 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35026000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 35504500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284359000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284722250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 33857939 # Number of BP lookups -system.cpu.branchPred.condPredicted 33857939 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774699 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19294742 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19202488 # Number of BTB hits +system.cpu.branchPred.lookups 34798086 # Number of BP lookups +system.cpu.branchPred.condPredicted 34798086 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 784118 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19722572 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19623609 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.521870 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5017287 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5447 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.498225 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5229209 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5537 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 131170685 # number of cpu cycles simulated +system.cpu.numCycles 128722137 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26133192 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182246280 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33857939 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24219775 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55455334 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5351155 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44937204 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 289 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 26886538 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 188337970 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34798086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24852818 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 57142929 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6497811 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38531317 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 400 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25572777 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166462 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131067108 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.451414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 26333180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 202728 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128229739 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.583672 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.351921 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78089059 59.58% 59.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1960403 1.50% 61.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2941378 2.24% 63.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3833422 2.92% 66.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7766051 5.93% 72.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4756858 3.63% 75.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2667148 2.03% 77.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1317375 1.01% 78.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27735414 21.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 73621715 57.41% 57.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2024375 1.58% 58.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3018246 2.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3935135 3.07% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7973611 6.22% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4963159 3.87% 74.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2723923 2.12% 76.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1373007 1.07% 77.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28596568 22.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131067108 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258121 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.389383 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36820362 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37159698 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43897766 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8648241 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4541041 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318820485 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4541041 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42311218 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9731436 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7378 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46747775 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27728260 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 314978384 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26284 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25867087 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 317148193 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836430617 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 514996548 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 444 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 128229739 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.270335 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.463136 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33273315 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35123523 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 52275495 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1888908 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5668498 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 328717141 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5668498 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37218540 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3059312 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10022 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50252159 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 32021208 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 323526783 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1441 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 292036 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 27143978 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4136186 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 325451198 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 859036392 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529005653 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 495 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37935446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 481 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 479 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62636107 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101548078 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34773749 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39632863 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5801803 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311454794 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1640 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300260019 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 90405 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32683934 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46065887 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1195 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131067108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290888 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.699985 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 46238451 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 482 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38827180 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104278858 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35723148 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 46025226 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6660051 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 319586854 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1670 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 304359156 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 192192 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40795282 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 60346573 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1225 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 128229739 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.373546 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.813536 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24336657 18.57% 18.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23236619 17.73% 36.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25445511 19.41% 55.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25817468 19.70% 75.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18870400 14.40% 89.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8268823 6.31% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3966909 3.03% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 944963 0.72% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 179758 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28989242 22.61% 22.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17448953 13.61% 36.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 19181395 14.96% 51.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24360940 19.00% 70.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22567411 17.60% 87.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10236760 7.98% 95.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4240558 3.31% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1068039 0.83% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136441 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131067108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128229739 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31509 1.53% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1916553 93.05% 94.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 111592 5.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 85597 3.62% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2173481 92.00% 95.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 103394 4.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169826780 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11192 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97302133 32.41% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33088277 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 172841480 56.79% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11196 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 41 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97881417 32.16% 88.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33591350 11.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300260019 # Type of FU issued -system.cpu.iq.rate 2.289079 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2059654 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006860 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733736743 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344172361 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298003080 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 638 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 138 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302288185 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 212 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54177955 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 304359156 # Type of FU issued +system.cpu.iq.rate 2.364466 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2362472 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007762 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 739502310 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 360419132 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 302118974 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 682 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 306688087 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 202 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 56122672 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10768693 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31319 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33463 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3333997 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13499473 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33923 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 36991 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4283396 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3215 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3583 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18172 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4541041 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2814889 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 161942 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311456434 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197084 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101548078 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34773749 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2528 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73554 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33463 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393542 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427902 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 821444 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298855458 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96888981 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1404561 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5668498 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 78601 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2898580 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 319588524 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 72060 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104278858 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35723148 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 467 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4947 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2697345 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 36991 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 397417 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 436010 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 833427 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 302993807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97430054 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1365349 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129814280 # number of memory reference insts executed -system.cpu.iew.exec_branches 30819367 # Number of branches executed -system.cpu.iew.exec_stores 32925299 # Number of stores executed -system.cpu.iew.exec_rate 2.278371 # Inst execution rate -system.cpu.iew.wb_sent 298372320 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298003218 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218247752 # num instructions producing a value -system.cpu.iew.wb_consumers 296740863 # num instructions consuming a value +system.cpu.iew.exec_refs 130824453 # number of memory reference insts executed +system.cpu.iew.exec_branches 31189297 # Number of branches executed +system.cpu.iew.exec_stores 33394399 # Number of stores executed +system.cpu.iew.exec_rate 2.353859 # Inst execution rate +system.cpu.iew.wb_sent 302554101 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 302119118 # cumulative count of insts written-back +system.cpu.iew.wb_producers 223057856 # num instructions producing a value +system.cpu.iew.wb_consumers 305896063 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.271874 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735483 # average fanout of values written-back +system.cpu.iew.wb_rate 2.347064 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.729195 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33277101 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 41496946 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774736 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126526067 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.198697 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.971805 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 784165 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122561241 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.269824 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.033262 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58264985 46.05% 46.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19162475 15.15% 61.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11581155 9.15% 70.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9447794 7.47% 77.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880712 1.49% 79.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2075089 1.64% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1295892 1.02% 81.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 693068 0.55% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22124897 17.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56600375 46.18% 46.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17466589 14.25% 60.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11063696 9.03% 69.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8855238 7.23% 76.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1990404 1.62% 78.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1890723 1.54% 79.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1087341 0.89% 80.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 761508 0.62% 81.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22845367 18.64% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126526067 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122561241 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -553,230 +554,230 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 22124897 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22845367 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415870735 # The number of ROB reads -system.cpu.rob.rob_writes 627483927 # The number of ROB writes -system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 103577 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 419405284 # The number of ROB reads +system.cpu.rob.rob_writes 645053666 # The number of ROB writes +system.cpu.timesIdled 104925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 492398 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.830254 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.830254 # CPI: Total CPI of All Threads -system.cpu.ipc 1.204450 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.204450 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483721911 # number of integer regfile reads -system.cpu.int_regfile_writes 234579114 # number of integer regfile writes -system.cpu.fp_regfile_reads 126 # number of floating regfile reads -system.cpu.fp_regfile_writes 70 # number of floating regfile writes -system.cpu.cc_regfile_reads 107055944 # number of cc regfile reads -system.cpu.cc_regfile_writes 64002928 # number of cc regfile writes -system.cpu.misc_regfile_reads 191820739 # number of misc regfile reads +system.cpu.cpi 0.814756 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.814756 # CPI: Total CPI of All Threads +system.cpu.ipc 1.227361 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.227361 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 488589645 # number of integer regfile reads +system.cpu.int_regfile_writes 237913555 # number of integer regfile writes +system.cpu.fp_regfile_reads 124 # number of floating regfile reads +system.cpu.fp_regfile_writes 93 # number of floating regfile writes +system.cpu.cc_regfile_reads 107415229 # number of cc regfile reads +system.cpu.cc_regfile_writes 64109444 # number of cc regfile writes +system.cpu.misc_regfile_reads 194048137 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4043936892 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995329 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066459 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82321 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2030 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221762 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265158016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265222976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265222976 # Total data (bytes) +system.cpu.toL2Bus.throughput 4120563135 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82265 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82265 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2034 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219411 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221445 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265138752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265203840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265203840 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138515000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1696250 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138084500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1694000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121723249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 55 # number of replacements -system.cpu.icache.tags.tagsinuse 822.073751 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25571467 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1015 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25193.563547 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 3121568749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 56 # number of replacements +system.cpu.icache.tags.tagsinuse 820.274669 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26331871 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1017 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25891.711898 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 822.073751 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.401403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.401403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51146569 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51146569 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25571467 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25571467 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25571467 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25571467 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25571467 # number of overall hits -system.cpu.icache.overall_hits::total 25571467 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1310 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1310 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1310 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1310 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1310 # number of overall misses -system.cpu.icache.overall_misses::total 1310 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 88805250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 88805250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 88805250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 88805250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 88805250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 88805250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25572777 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25572777 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25572777 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25572777 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25572777 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25572777 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67790.267176 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67790.267176 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67790.267176 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67790.267176 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67790.267176 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67790.267176 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 116 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 820.274669 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.400525 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.400525 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 961 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.469238 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 52667377 # Number of tag accesses +system.cpu.icache.tags.data_accesses 52667377 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26331871 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26331871 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26331871 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26331871 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26331871 # number of overall hits +system.cpu.icache.overall_hits::total 26331871 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1309 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1309 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1309 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1309 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1309 # number of overall misses +system.cpu.icache.overall_misses::total 1309 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 89709250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 89709250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 89709250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 89709250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 89709250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 89709250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26333180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26333180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26333180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26333180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26333180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26333180 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68532.658518 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68532.658518 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68532.658518 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68532.658518 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68532.658518 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68532.658518 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 295 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 295 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 295 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 295 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1015 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1015 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1015 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1015 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1015 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1015 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69941750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69941750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69941750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69941750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69941750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69941750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 292 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 292 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1017 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1017 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1017 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70297000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70297000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70297000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 70297000 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56847.407148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52524.504396 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52524.504396 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56167.582418 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52610.198430 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52727.211488 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56167.582418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52610.198430 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52727.211488 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 171 # number of writebacks +system.cpu.l2cache.writebacks::total 171 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1000 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1422 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29002 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29002 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1000 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1000 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30424 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 56577000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24214250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80791250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526186500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526186500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56577000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1550400750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1606977750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56577000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1550400750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1606977750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000713 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352544 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352544 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57379.739336 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56815.225035 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52623.491483 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52623.491483 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56577 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52691.705750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52819.410663 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52691.705750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52819.410663 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072539 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.510002 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71382775 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076635 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.374252 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20654566000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.510002 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993533 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993533 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072519 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.536250 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 69938402 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076615 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.679041 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20171577250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.536250 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993539 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 584 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3363 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150290167 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150290167 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 40041040 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40041040 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71382775 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71382775 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71382775 # number of overall hits -system.cpu.dcache.overall_hits::total 71382775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2625974 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2625974 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98017 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98017 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2723991 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2723991 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2723991 # number of overall misses -system.cpu.dcache.overall_misses::total 2723991 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399512249 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31399512249 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2790424746 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2790424746 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34189936995 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34189936995 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34189936995 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34189936995 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42667014 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42667014 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 147464213 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 147464213 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 38592969 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 38592969 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345433 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345433 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 69938402 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 69938402 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 69938402 # number of overall hits +system.cpu.dcache.overall_hits::total 69938402 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2661078 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2661078 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 94319 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 94319 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2755397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2755397 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2755397 # number of overall misses +system.cpu.dcache.overall_misses::total 2755397 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31651251499 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31651251499 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2775683247 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2775683247 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34426934746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34426934746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34426934746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34426934746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 41254047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 41254047 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74106766 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74106766 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74106766 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74106766 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061546 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061546 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036758 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036758 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036758 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11957.282231 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11957.282231 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28468.783436 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28468.783436 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12551.413347 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12551.413347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12551.413347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12551.413347 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32593 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 72693799 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 72693799 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 72693799 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 72693799 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064505 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.064505 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003000 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003000 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037904 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037904 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037904 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037904 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11894.146470 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11894.146470 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29428.675527 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29428.675527 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12494.364604 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12494.364604 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12494.364604 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12494.364604 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 86474 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9513 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 16255 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.426154 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.319840 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066459 # number of writebacks -system.cpu.dcache.writebacks::total 2066459 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631537 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631537 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15816 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15816 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647353 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994437 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994437 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82201 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82201 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996919001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996919001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502949746 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502949746 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24499868747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24499868747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24499868747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24499868747 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046744 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046744 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028022 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028022 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028022 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028022 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.137045 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.137045 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30449.139864 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30449.139864 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.852465 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.852465 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.852465 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.852465 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2066178 # number of writebacks +system.cpu.dcache.writebacks::total 2066178 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666601 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 666601 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 12178 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 12178 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 678779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 678779 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 678779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 678779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994477 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994477 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82141 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82141 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076618 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076618 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076618 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076618 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21991461751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21991461751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2506217997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2506217997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24497679748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24497679748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24497679748 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24497679748 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048346 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048346 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028567 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.179671 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.179671 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30511.169781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30511.169781 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11796.911973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11796.911973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11796.911973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11796.911973 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index b9d303473..19f9758d3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,9 +699,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/parser +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/cpu2000/data/parser/mdred/input/parser.in +input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 980a69a9d..0d3306a6b 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:14:04 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:42:28 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x4cfd380 + 0: system.cpu.isa: ISA system set to: 0 0x6824800 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -68,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 202696649500 because target called exit() +Exiting @ tick 201639641000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 939d3dd4a..522c4ee18 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202425 # Number of seconds simulated -sim_ticks 202425052500 # Number of ticks simulated -final_tick 202425052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.201640 # Number of seconds simulated +sim_ticks 201639641000 # Number of ticks simulated +final_tick 201639641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117924 # Simulator instruction rate (inst/s) -host_op_rate 132952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47246555 # Simulator tick rate (ticks/s) -host_mem_usage 317744 # Number of bytes of host memory used -host_seconds 4284.44 # Real time elapsed on the host +host_inst_rate 135689 # Simulator instruction rate (inst/s) +host_op_rate 152980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54153116 # Simulator tick rate (ticks/s) +host_mem_usage 265540 # Number of bytes of host memory used +host_seconds 3723.51 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 216128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9265920 # Number of bytes read from this memory -system.physmem.bytes_read::total 9482048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6248320 # Number of bytes written to this memory -system.physmem.bytes_written::total 6248320 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3377 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144780 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97630 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97630 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45774571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46842265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30867326 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30867326 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30867326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45774571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77709591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148159 # Number of read requests accepted -system.physmem.writeReqs 97630 # Number of write requests accepted -system.physmem.readBursts 148159 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97630 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9473600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue -system.physmem.bytesWritten 6247040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9482176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6248320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 217344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9271296 # Number of bytes read from this memory +system.physmem.bytes_read::total 9488640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6252864 # Number of bytes written to this memory +system.physmem.bytes_written::total 6252864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144864 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148260 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1077883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45979530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47057414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1077883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1077883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31010093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31010093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31010093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1077883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45979530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78067507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148261 # Number of read requests accepted +system.physmem.writeReqs 97701 # Number of write requests accepted +system.physmem.readBursts 148261 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97701 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9478784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue +system.physmem.bytesWritten 6251328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9488704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6252864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 5 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9589 # Per bank write bursts -system.physmem.perBankRdBursts::1 9250 # Per bank write bursts -system.physmem.perBankRdBursts::2 9271 # Per bank write bursts -system.physmem.perBankRdBursts::3 8997 # Per bank write bursts -system.physmem.perBankRdBursts::4 9766 # Per bank write bursts -system.physmem.perBankRdBursts::5 9623 # Per bank write bursts -system.physmem.perBankRdBursts::6 9103 # Per bank write bursts -system.physmem.perBankRdBursts::7 8296 # Per bank write bursts -system.physmem.perBankRdBursts::8 8815 # Per bank write bursts -system.physmem.perBankRdBursts::9 8915 # Per bank write bursts -system.physmem.perBankRdBursts::10 8926 # Per bank write bursts -system.physmem.perBankRdBursts::11 9755 # Per bank write bursts -system.physmem.perBankRdBursts::12 9632 # Per bank write bursts -system.physmem.perBankRdBursts::13 9741 # Per bank write bursts -system.physmem.perBankRdBursts::14 8922 # Per bank write bursts -system.physmem.perBankRdBursts::15 9424 # Per bank write bursts -system.physmem.perBankWrBursts::0 6257 # Per bank write bursts -system.physmem.perBankWrBursts::1 6164 # Per bank write bursts -system.physmem.perBankWrBursts::2 6102 # Per bank write bursts -system.physmem.perBankWrBursts::3 5898 # Per bank write bursts -system.physmem.perBankWrBursts::4 6263 # Per bank write bursts -system.physmem.perBankWrBursts::5 6268 # Per bank write bursts -system.physmem.perBankWrBursts::6 6040 # Per bank write bursts -system.physmem.perBankWrBursts::7 5542 # Per bank write bursts -system.physmem.perBankWrBursts::8 5815 # Per bank write bursts -system.physmem.perBankWrBursts::9 5905 # Per bank write bursts -system.physmem.perBankWrBursts::10 5986 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 8 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9600 # Per bank write bursts +system.physmem.perBankRdBursts::1 9245 # Per bank write bursts +system.physmem.perBankRdBursts::2 9272 # Per bank write bursts +system.physmem.perBankRdBursts::3 9002 # Per bank write bursts +system.physmem.perBankRdBursts::4 9776 # Per bank write bursts +system.physmem.perBankRdBursts::5 9633 # Per bank write bursts +system.physmem.perBankRdBursts::6 9118 # Per bank write bursts +system.physmem.perBankRdBursts::7 8324 # Per bank write bursts +system.physmem.perBankRdBursts::8 8782 # Per bank write bursts +system.physmem.perBankRdBursts::9 8907 # Per bank write bursts +system.physmem.perBankRdBursts::10 8927 # Per bank write bursts +system.physmem.perBankRdBursts::11 9740 # Per bank write bursts +system.physmem.perBankRdBursts::12 9612 # Per bank write bursts +system.physmem.perBankRdBursts::13 9774 # Per bank write bursts +system.physmem.perBankRdBursts::14 8952 # Per bank write bursts +system.physmem.perBankRdBursts::15 9442 # Per bank write bursts +system.physmem.perBankWrBursts::0 6262 # Per bank write bursts +system.physmem.perBankWrBursts::1 6157 # Per bank write bursts +system.physmem.perBankWrBursts::2 6103 # Per bank write bursts +system.physmem.perBankWrBursts::3 5900 # Per bank write bursts +system.physmem.perBankWrBursts::4 6261 # Per bank write bursts +system.physmem.perBankWrBursts::5 6280 # Per bank write bursts +system.physmem.perBankWrBursts::6 6052 # Per bank write bursts +system.physmem.perBankWrBursts::7 5550 # Per bank write bursts +system.physmem.perBankWrBursts::8 5797 # Per bank write bursts +system.physmem.perBankWrBursts::9 5910 # Per bank write bursts +system.physmem.perBankWrBursts::10 5990 # Per bank write bursts system.physmem.perBankWrBursts::11 6523 # Per bank write bursts -system.physmem.perBankWrBursts::12 6368 # Per bank write bursts -system.physmem.perBankWrBursts::13 6315 # Per bank write bursts -system.physmem.perBankWrBursts::14 6035 # Per bank write bursts -system.physmem.perBankWrBursts::15 6129 # Per bank write bursts +system.physmem.perBankWrBursts::12 6359 # Per bank write bursts +system.physmem.perBankWrBursts::13 6344 # Per bank write bursts +system.physmem.perBankWrBursts::14 6057 # Per bank write bursts +system.physmem.perBankWrBursts::15 6132 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202425037000 # Total gap between requests +system.physmem.totGap 201639615000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148159 # Read request sizes (log2) +system.physmem.readPktSize::6 148261 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97630 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97701 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -193,104 +193,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.288837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.819388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.394880 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26636 40.71% 40.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17331 26.49% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6016 9.20% 76.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6235 9.53% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3111 4.76% 90.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1372 2.10% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 907 1.39% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 656 1.00% 95.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3157 4.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 65483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.203045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.557671 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.515687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 26845 41.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17105 26.12% 67.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6057 9.25% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6227 9.51% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3215 4.91% 90.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1344 2.05% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 866 1.32% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 634 0.97% 95.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3190 4.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65483 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.864057 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 376.771836 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5718 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.877861 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.772634 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5719 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.055740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.965515 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.130372 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 3465 60.55% 60.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2071 36.19% 96.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 82 1.43% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 27 0.47% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 23 0.40% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 13 0.23% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 7 0.12% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.05% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.067447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.968448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.305335 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 3462 60.49% 60.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2077 36.29% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 88 1.54% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 26 0.45% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 19 0.33% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 9 0.16% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 14 0.24% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 5 0.09% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads -system.physmem.totQLat 1821123750 # Total ticks spent queuing -system.physmem.totMemAccLat 4596592500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12302.81 # Average queueing delay per DRAM burst +system.physmem.totQLat 1816896000 # Total ticks spent queuing +system.physmem.totMemAccLat 4593883500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12267.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31052.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 46.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 30.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 46.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 30.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31017.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 47.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 31.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 47.06 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 31.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.22 # Average write queue length when enqueuing -system.physmem.readRowHits 115945 # Number of row buffer hits during reads -system.physmem.writeRowHits 64262 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.82 # Row buffer hit rate for writes -system.physmem.avgGap 823572.40 # Average gap between requests -system.physmem.pageHitRate 73.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 121085417750 # Time in different power states -system.physmem.memoryStateTime::REF 6759220000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.04 # Average write queue length when enqueuing +system.physmem.readRowHits 116026 # Number of row buffer hits during reads +system.physmem.writeRowHits 64266 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.78 # Row buffer hit rate for writes +system.physmem.avgGap 819799.87 # Average gap between requests +system.physmem.pageHitRate 73.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 120286035750 # Time in different power states +system.physmem.memoryStateTime::REF 6732960000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 74577349250 # Time in different power states +system.physmem.memoryStateTime::ACT 74617456750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 77709591 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46864 # Transaction distribution -system.membus.trans_dist::ReadResp 46862 # Transaction distribution -system.membus.trans_dist::Writeback 97630 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 101295 # Transaction distribution -system.membus.trans_dist::ReadExResp 101295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393956 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 393956 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15730368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15730368 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15730368 # Total data (bytes) +system.membus.throughput 78067507 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46965 # Transaction distribution +system.membus.trans_dist::ReadResp 46964 # Transaction distribution +system.membus.trans_dist::Writeback 97701 # Transaction distribution +system.membus.trans_dist::UpgradeReq 8 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 101296 # Transaction distribution +system.membus.trans_dist::ReadExResp 101296 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394238 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394238 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15741504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15741504 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15741504 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1082435500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1079764000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1397409745 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1396376742 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 182802818 # Number of BP lookups -system.cpu.branchPred.condPredicted 143112021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7267941 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93011295 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87213055 # Number of BTB hits +system.cpu.branchPred.lookups 185905498 # Number of BP lookups +system.cpu.branchPred.condPredicted 145717903 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7288959 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 95047377 # Number of BTB lookups +system.cpu.branchPred.BTBHits 88827374 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.766090 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12678218 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116271 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.455892 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12842646 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 117058 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -376,239 +378,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404850106 # number of cpu cycles simulated +system.cpu.numCycles 403279283 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119389916 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761628718 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182802818 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99891273 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170150143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35691365 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77449263 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 486 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114538694 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2440341 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394609388 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164838 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 120682752 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 776131290 # Number of instructions fetch has processed +system.cpu.fetch.Branches 185905498 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 101670020 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 172998904 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 37503258 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 68039482 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 481 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 115897812 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2525334 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 391132406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.225985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.009732 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224471880 56.88% 56.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14182431 3.59% 60.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22892997 5.80% 66.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746730 5.76% 72.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20891038 5.29% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11596009 2.94% 80.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13056866 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12000205 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52771232 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 218146201 55.77% 55.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14394493 3.68% 59.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23167694 5.92% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22933314 5.86% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21066439 5.39% 76.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11728153 3.00% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13552888 3.47% 83.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12244725 3.13% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53898499 13.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394609388 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451532 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.881261 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129090145 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72932890 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158811519 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6229483 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27545351 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26129524 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76858 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825625828 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295316 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27545351 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135687065 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10105791 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47805401 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158260364 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15205416 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800656323 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1334 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3053839 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8954907 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 385 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954272169 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3518760229 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3237464445 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 391132406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.460984 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.924550 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127941260 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 66012107 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164309835 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3533487 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 29335717 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26533351 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 77647 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 841607037 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 303900 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 29335717 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 132935936 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7523486 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 48032128 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 162776327 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10528812 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 816179204 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4868 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4457827 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 3314300 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1212194 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 4787 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 972434380 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3587695415 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3300630013 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288019878 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292922 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292918 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41836509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170268509 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73501316 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28634884 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15888043 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755077640 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775313 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665327015 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1386285 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187386746 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479953007 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797681 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394609388 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.686039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735073 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 306182089 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293511 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293509 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23291983 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173719051 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74905434 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 30225729 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 17207987 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 768522572 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775769 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 668800812 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1727981 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 200793138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 527082191 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 798137 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 391132406 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.709909 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.765965 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139096453 35.25% 35.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69938770 17.72% 52.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71532009 18.13% 71.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53395901 13.53% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31139583 7.89% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15999118 4.05% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8786717 2.23% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2904396 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1816441 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 138616997 35.44% 35.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 67517265 17.26% 52.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69869307 17.86% 70.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51755005 13.23% 83.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 32440287 8.29% 92.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16135836 4.13% 96.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9617335 2.46% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3307412 0.85% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1872962 0.48% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394609388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 391132406 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479561 5.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6536466 68.14% 73.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2577260 26.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 630442 6.26% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6879641 68.30% 74.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2562211 25.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447787138 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383414 0.06% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153368040 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63788326 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 449864838 67.26% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383889 0.06% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154509639 23.10% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 64042341 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665327015 # Type of FU issued -system.cpu.iq.rate 1.643391 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9593287 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014419 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736242767 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947046337 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646056325 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 668800812 # Type of FU issued +system.cpu.iq.rate 1.658406 # Inst issue rate +system.cpu.iq.fu_busy_cnt 10072294 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015060 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1740534066 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 973902079 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 649227410 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 239 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674920189 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8551877 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 678872985 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 121 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9444118 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44238954 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41472 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810610 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16640839 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 47689496 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 34046 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 814715 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 18044957 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19493 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7969 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19567 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5233 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27545351 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5256121 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 385567 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760412013 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1120947 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170268509 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73501316 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286771 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219704 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12090 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810610 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4341838 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4001214 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8343052 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655907838 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150084771 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9419177 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 29335717 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3955691 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1178658 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 773883644 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1025688 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 173719051 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74905434 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2287227 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 242970 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 870100 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 814715 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4363839 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4034750 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8398589 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 659340001 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151050186 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9460811 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559060 # number of nop insts executed -system.cpu.iew.exec_refs 212583673 # number of memory reference insts executed -system.cpu.iew.exec_branches 138498504 # Number of branches executed -system.cpu.iew.exec_stores 62498902 # Number of stores executed -system.cpu.iew.exec_rate 1.620125 # Inst execution rate -system.cpu.iew.wb_sent 651026464 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646056341 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374698942 # num instructions producing a value -system.cpu.iew.wb_consumers 646299992 # num instructions consuming a value +system.cpu.iew.exec_nop 1585303 # number of nop insts executed +system.cpu.iew.exec_refs 213740794 # number of memory reference insts executed +system.cpu.iew.exec_branches 139088077 # Number of branches executed +system.cpu.iew.exec_stores 62690608 # Number of stores executed +system.cpu.iew.exec_rate 1.634946 # Inst execution rate +system.cpu.iew.wb_sent 654323635 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 649227426 # cumulative count of insts written-back +system.cpu.iew.wb_producers 378014910 # num instructions producing a value +system.cpu.iew.wb_consumers 657704988 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.595791 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back +system.cpu.iew.wb_rate 1.609871 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.574748 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189472037 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 202955681 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7193780 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367064037 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555500 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230573 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7214032 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 361796689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.578146 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.256071 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159337830 43.41% 43.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98602437 26.86% 70.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33803348 9.21% 79.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18720540 5.10% 84.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16173781 4.41% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7454535 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6985415 1.90% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3172083 0.86% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22814068 6.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156712744 43.32% 43.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 96319147 26.62% 69.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33326252 9.21% 79.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 17957546 4.96% 84.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16748053 4.63% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7262749 2.01% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6923592 1.91% 92.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3096479 0.86% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23450127 6.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367064037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 361796689 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,237 +657,238 @@ system.cpu.commit.op_class_0::MemWrite 56860477 9.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 570968167 # Class of committed instruction -system.cpu.commit.bw_lim_events 22814068 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 23450127 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104683035 # The number of ROB reads -system.cpu.rob.rob_writes 1548546574 # The number of ROB writes -system.cpu.timesIdled 329089 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10240718 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1112263272 # The number of ROB reads +system.cpu.rob.rob_writes 1577313182 # The number of ROB writes +system.cpu.timesIdled 375340 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12146877 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.801306 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.801306 # CPI: Total CPI of All Threads -system.cpu.ipc 1.247962 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.247962 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058680468 # number of integer regfile reads -system.cpu.int_regfile_writes 751974394 # number of integer regfile writes +system.cpu.cpi 0.798197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.798197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.252823 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.252823 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3074448522 # number of integer regfile reads +system.cpu.int_regfile_writes 755651134 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 237852228 # number of misc regfile reads +system.cpu.misc_regfile_reads 238959520 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 734945552 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348881 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348881 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504415 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538241 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147686464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148766336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148766336 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273224996 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 738060588 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 865494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 865493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1111057 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 86 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 86 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348798 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505273 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3539717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1099136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147717056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148816192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148816192 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 6080 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273774999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26000486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 26477230 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1824563475 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1825044731 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15031 # number of replacements -system.cpu.icache.tags.tagsinuse 1100.518238 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114517542 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16885 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6782.205626 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15336 # number of replacements +system.cpu.icache.tags.tagsinuse 1096.367650 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 115876238 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 17184 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6743.263385 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1100.518238 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.537362 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.537362 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1854 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.905273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 229094338 # Number of tag accesses -system.cpu.icache.tags.data_accesses 229094338 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 114517542 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114517542 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114517542 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114517542 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114517542 # number of overall hits -system.cpu.icache.overall_hits::total 114517542 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21151 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21151 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21151 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21151 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21151 # number of overall misses -system.cpu.icache.overall_misses::total 21151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 554005735 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 554005735 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 554005735 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 554005735 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 554005735 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 554005735 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114538693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114538693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114538693 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114538693 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114538693 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114538693 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000185 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23639.129705 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115416 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27085.834103 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1781268 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146665 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.145147 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7681 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21304 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2187 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7697 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21300 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953644 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19091917 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19091917 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9066663751 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.197787 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051364 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054270 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.081395 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.081395 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290417 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290417 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.197787 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121021 # 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Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4252802250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.481628 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990596 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990596 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1192926 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.383105 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190117545 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1197022 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.825439 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4253859250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.383105 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990572 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1688 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1689 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 391451119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 391451119 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 136209146 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136209146 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50988846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488796 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488796 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 391573870 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 391573870 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 136255144 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136255144 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50884737 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50884737 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488854 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488854 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187197992 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187197992 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187197992 # number of overall hits -system.cpu.dcache.overall_hits::total 187197992 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1701390 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1701390 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3250460 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3250460 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4951850 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4951850 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4951850 # number of overall misses -system.cpu.dcache.overall_misses::total 4951850 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29115477457 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29115477457 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 71211038449 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 71211038449 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 100326515906 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 100326515906 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 100326515906 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 100326515906 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137910536 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137910536 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187139881 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187139881 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187139881 # number of overall hits +system.cpu.dcache.overall_hits::total 187139881 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1716538 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1716538 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3354569 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3354569 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 5071107 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 5071107 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 5071107 # number of overall misses +system.cpu.dcache.overall_misses::total 5071107 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29658271464 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29658271464 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 73164049214 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 73164049214 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 726000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 726000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102822320678 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102822320678 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102822320678 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102822320678 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137971682 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137971682 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488833 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488833 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192149842 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192149842 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192149842 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192149842 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012337 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012337 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059928 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059928 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025771 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025771 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025771 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025771 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17112.759248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17112.759248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21907.987931 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21907.987931 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20260.410939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20260.410939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17276 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 49920 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1691 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 664 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.216440 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.180723 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192210988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192210988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192210988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192210988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012441 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061848 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.061848 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026383 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026383 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17277.957997 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17277.957997 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21810.268089 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21810.268089 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17707.317073 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17707.317073 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20276.109472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20276.109472 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17575 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 53737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1744 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 663 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.077408 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81.051282 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110914 # number of writebacks -system.cpu.dcache.writebacks::total 1110914 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853047 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 853047 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902052 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902052 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3755099 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3755099 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3755099 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3755099 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848343 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848343 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348408 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348408 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196751 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196751 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196751 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196751 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12254549779 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12254549779 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10243730741 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10243730741 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22498280520 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22498280520 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22498280520 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22498280520 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 1111057 # number of writebacks +system.cpu.dcache.writebacks::total 1111057 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867776 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 867776 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3006223 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3006223 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3873999 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3873999 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3873999 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3873999 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848762 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848762 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348346 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348346 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1197108 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1197108 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1197108 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1197108 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264084776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264084776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10175822989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10175822989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22439907765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22439907765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22439907765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22439907765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14445.277180 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14445.277180 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29401.537109 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29401.537109 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14449.380128 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14449.380128 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29211.826715 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29211.826715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index e184df091..7faf76c14 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -632,9 +634,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/x86/linux/parser +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/cpu2000/data/parser/mdred/input/parser.in +input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -674,27 +676,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 36dc7aeb7..746dbf385 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,17 +1,28 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 15 2014 16:30:59 -gem5 started Feb 16 2014 01:49:09 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:34:22 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: *********info: Increasing stack size by one page. -**************************************** +info: Increasing stack size by one page. +******************************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +********** 58924 words stored in 3784810 bytes @@ -23,8 +34,6 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor info: Increasing stack size by one page. @@ -74,11 +83,9 @@ info: Increasing stack size by one page. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love -info: Increasing stack size by one page. -info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 459118646000 because target called exit() +Exiting @ tick 456433328000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 4a6325c04..45be2f3b2 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458513 # Number of seconds simulated -sim_ticks 458512999500 # Number of ticks simulated -final_tick 458512999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.456433 # Number of seconds simulated +sim_ticks 456433328000 # Number of ticks simulated +final_tick 456433328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75448 # Simulator instruction rate (inst/s) -host_op_rate 139512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41836736 # Simulator tick rate (ticks/s) -host_mem_usage 384056 # Number of bytes of host memory used -host_seconds 10959.58 # Real time elapsed on the host +host_inst_rate 93655 # Simulator instruction rate (inst/s) +host_op_rate 173179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51697488 # Simulator tick rate (ticks/s) +host_mem_usage 350856 # Number of bytes of host memory used +host_seconds 8828.93 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 201856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24474368 # Number of bytes read from this memory -system.physmem.bytes_read::total 24676224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 201856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 201856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18792384 # Number of bytes written to this memory -system.physmem.bytes_written::total 18792384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293631 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293631 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 440241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53377697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53817938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 440241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40985499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40985499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40985499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 440241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53377697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94803436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385568 # Number of read requests accepted -system.physmem.writeReqs 293631 # Number of write requests accepted -system.physmem.readBursts 385568 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293631 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24654400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue -system.physmem.bytesWritten 18790528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24676352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18792384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 210304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24488448 # Number of bytes read from this memory +system.physmem.bytes_read::total 24698752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 210304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 210304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18796480 # Number of bytes written to this memory +system.physmem.bytes_written::total 18796480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3286 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382632 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385918 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293695 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293695 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 460755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53651753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54112508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 460755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 460755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41181217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41181217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41181217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 460755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53651753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 95293725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385918 # Number of read requests accepted +system.physmem.writeReqs 293695 # Number of write requests accepted +system.physmem.readBursts 385918 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293695 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24677440 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue +system.physmem.bytesWritten 18795136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24698752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18796480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 136756 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24002 # Per bank write bursts -system.physmem.perBankRdBursts::1 26346 # Per bank write bursts -system.physmem.perBankRdBursts::2 24809 # Per bank write bursts -system.physmem.perBankRdBursts::3 24514 # Per bank write bursts -system.physmem.perBankRdBursts::4 23427 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 143951 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24030 # Per bank write bursts +system.physmem.perBankRdBursts::1 26462 # Per bank write bursts +system.physmem.perBankRdBursts::2 24796 # Per bank write bursts +system.physmem.perBankRdBursts::3 24548 # Per bank write bursts +system.physmem.perBankRdBursts::4 23428 # Per bank write bursts system.physmem.perBankRdBursts::5 23679 # Per bank write bursts -system.physmem.perBankRdBursts::6 24437 # Per bank write bursts -system.physmem.perBankRdBursts::7 24240 # Per bank write bursts -system.physmem.perBankRdBursts::8 23642 # Per bank write bursts -system.physmem.perBankRdBursts::9 23833 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 23968 # Per bank write bursts -system.physmem.perBankRdBursts::12 23115 # Per bank write bursts -system.physmem.perBankRdBursts::13 22838 # Per bank write bursts -system.physmem.perBankRdBursts::14 23649 # Per bank write bursts -system.physmem.perBankRdBursts::15 23923 # Per bank write bursts +system.physmem.perBankRdBursts::6 24455 # Per bank write bursts +system.physmem.perBankRdBursts::7 24282 # Per bank write bursts +system.physmem.perBankRdBursts::8 23646 # Per bank write bursts +system.physmem.perBankRdBursts::9 23871 # Per bank write bursts +system.physmem.perBankRdBursts::10 24701 # Per bank write bursts +system.physmem.perBankRdBursts::11 23965 # Per bank write bursts +system.physmem.perBankRdBursts::12 23120 # Per bank write bursts +system.physmem.perBankRdBursts::13 22899 # Per bank write bursts +system.physmem.perBankRdBursts::14 23768 # Per bank write bursts +system.physmem.perBankRdBursts::15 23935 # Per bank write bursts system.physmem.perBankWrBursts::0 18533 # Per bank write bursts -system.physmem.perBankWrBursts::1 19811 # Per bank write bursts -system.physmem.perBankWrBursts::2 18961 # Per bank write bursts -system.physmem.perBankWrBursts::3 18917 # Per bank write bursts -system.physmem.perBankWrBursts::4 18087 # Per bank write bursts -system.physmem.perBankWrBursts::5 18414 # Per bank write bursts -system.physmem.perBankWrBursts::6 18972 # Per bank write bursts -system.physmem.perBankWrBursts::7 18944 # Per bank write bursts -system.physmem.perBankWrBursts::8 18562 # Per bank write bursts -system.physmem.perBankWrBursts::9 18116 # Per bank write bursts -system.physmem.perBankWrBursts::10 18832 # Per bank write bursts -system.physmem.perBankWrBursts::11 17714 # Per bank write bursts -system.physmem.perBankWrBursts::12 17339 # Per bank write bursts -system.physmem.perBankWrBursts::13 16924 # Per bank write bursts -system.physmem.perBankWrBursts::14 17682 # Per bank write bursts -system.physmem.perBankWrBursts::15 17794 # Per bank write bursts +system.physmem.perBankWrBursts::1 19857 # Per bank write bursts +system.physmem.perBankWrBursts::2 18944 # Per bank write bursts +system.physmem.perBankWrBursts::3 18929 # Per bank write bursts +system.physmem.perBankWrBursts::4 18079 # Per bank write bursts +system.physmem.perBankWrBursts::5 18409 # Per bank write bursts +system.physmem.perBankWrBursts::6 18979 # Per bank write bursts +system.physmem.perBankWrBursts::7 18957 # Per bank write bursts +system.physmem.perBankWrBursts::8 18565 # Per bank write bursts +system.physmem.perBankWrBursts::9 18141 # Per bank write bursts +system.physmem.perBankWrBursts::10 18792 # Per bank write bursts +system.physmem.perBankWrBursts::11 17687 # Per bank write bursts +system.physmem.perBankWrBursts::12 17335 # Per bank write bursts +system.physmem.perBankWrBursts::13 16957 # Per bank write bursts +system.physmem.perBankWrBursts::14 17714 # Per bank write bursts +system.physmem.perBankWrBursts::15 17796 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 458512983000 # Total gap between requests +system.physmem.totGap 456433277000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385568 # Read request sizes (log2) +system.physmem.readPktSize::6 385918 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293631 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293695 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,45 +144,45 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17435 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -193,340 +193,339 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.052173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.726027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.657452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54056 36.84% 36.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40668 27.71% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13398 9.13% 73.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7234 4.93% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5377 3.66% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3862 2.63% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3026 2.06% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2779 1.89% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16343 11.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146743 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17400 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.138621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.351810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17386 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.532446 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.978677 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.931077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54105 36.91% 36.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40284 27.48% 64.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13640 9.30% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7345 5.01% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5124 3.50% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3885 2.65% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3054 2.08% 86.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16360 11.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146599 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17413 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.143169 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.002812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17400 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17400 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.873678 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.805032 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.403017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17211 98.91% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 144 0.83% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 22 0.13% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 3 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17413 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.865216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.791721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.763276 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17216 98.87% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 134 0.77% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 42 0.24% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 4 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17400 # Writes before turning the bus around for reads -system.physmem.totQLat 4188887000 # Total ticks spent queuing -system.physmem.totMemAccLat 11411855750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1926125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10873.87 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17413 # Writes before turning the bus around for reads +system.physmem.totQLat 4238739250 # Total ticks spent queuing +system.physmem.totMemAccLat 11468458000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1927925000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10993.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29623.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 53.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 40.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 40.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29743.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.18 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.82 # Average write queue length when enqueuing -system.physmem.readRowHits 316892 # Number of row buffer hits during reads -system.physmem.writeRowHits 215180 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes -system.physmem.avgGap 675079.00 # Average gap between requests -system.physmem.pageHitRate 78.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 318092069500 # Time in different power states -system.physmem.memoryStateTime::REF 15310620000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing +system.physmem.readRowHits 317362 # Number of row buffer hits during reads +system.physmem.writeRowHits 215286 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes +system.physmem.avgGap 671607.63 # Average gap between requests +system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 317298172500 # Time in different power states +system.physmem.memoryStateTime::REF 15241200000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 125106520750 # Time in different power states +system.physmem.memoryStateTime::ACT 123890904750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 94803436 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178732 # Transaction distribution -system.membus.trans_dist::ReadResp 178730 # Transaction distribution -system.membus.trans_dist::Writeback 293631 # Transaction distribution -system.membus.trans_dist::UpgradeReq 136756 # Transaction distribution -system.membus.trans_dist::UpgradeResp 136756 # Transaction distribution -system.membus.trans_dist::ReadExReq 206836 # Transaction distribution -system.membus.trans_dist::ReadExResp 206836 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1338277 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1338277 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1338277 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43468608 # Total data (bytes) +system.membus.throughput 95293725 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 179074 # Transaction distribution +system.membus.trans_dist::ReadResp 179074 # Transaction distribution +system.membus.trans_dist::Writeback 293695 # Transaction distribution +system.membus.trans_dist::UpgradeReq 143951 # Transaction distribution +system.membus.trans_dist::UpgradeResp 143951 # Transaction distribution +system.membus.trans_dist::ReadExReq 206844 # Transaction distribution +system.membus.trans_dist::ReadExResp 206844 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1353433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1353433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1353433 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43495232 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43495232 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43495232 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43495232 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3392871500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3409046000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3899245261 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3919297073 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 205578466 # Number of BP lookups -system.cpu.branchPred.condPredicted 205578466 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9901534 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117029392 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114680074 # Number of BTB hits +system.cpu.branchPred.lookups 214172576 # Number of BP lookups +system.cpu.branchPred.condPredicted 214172576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 10017048 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 122104582 # Number of BTB lookups +system.cpu.branchPred.BTBHits 119561484 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.992540 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25067972 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1805738 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.917279 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25755339 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1811393 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 917184655 # number of cpu cycles simulated +system.cpu.numCycles 913134033 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167397549 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131555944 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205578466 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139748046 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352223186 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71069558 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 304555909 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253720 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161997167 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2518791 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 885395126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.377906 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324319 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 172957677 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1180093576 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214172576 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 145316823 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 366593738 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 80936667 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 266990637 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 326654 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 167839999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2941367 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 877562871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.500418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.366055 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 537236750 60.68% 60.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23398648 2.64% 63.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25254202 2.85% 66.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27875613 3.15% 69.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17735392 2.00% 71.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22920767 2.59% 73.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29423422 3.32% 77.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26636426 3.01% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174913906 19.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 515232459 58.71% 58.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24457756 2.79% 61.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25984112 2.96% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28771124 3.28% 67.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18396810 2.10% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 23701764 2.70% 72.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30460841 3.47% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 27790154 3.17% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 182767851 20.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 885395126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224141 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.233728 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222654978 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 259567656 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295344640 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46911146 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60916706 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071122559 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60916706 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256101136 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 115302026 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17668 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306678759 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146378831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2034998452 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20313 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24722090 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106340501 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2137925960 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150186774 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273147321 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 41991 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 877562871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.234547 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.292355 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 214899100 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 235918889 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 323832333 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 32275243 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70637306 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2159083489 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 22 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70637306 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 235683125 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 99102790 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23033 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 334766565 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 137350052 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2116178959 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 79091 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 86333515 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 11675978 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 34385645 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2221828274 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5358350843 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3404407883 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 44462 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523885106 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1288 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1219 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 345625652 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495840221 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194409464 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195351813 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54649414 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975275020 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13975 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772033700 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 489443 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441377933 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734704744 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13423 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 885395126 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.001404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883479 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 607787420 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1530 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1409 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 224967788 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 514990281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 202517058 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 220543258 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 63035338 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2048951027 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 18335 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1800520380 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 873481 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 514890445 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 886881463 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17783 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 877562871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.051728 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.961101 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 268930520 30.37% 30.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151513258 17.11% 47.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137639902 15.55% 63.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131544541 14.86% 77.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91741507 10.36% 88.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55934371 6.32% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34425935 3.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11907214 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1757878 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278621882 31.75% 31.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 139650345 15.91% 47.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 122145227 13.92% 61.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 121221287 13.81% 75.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 101661945 11.58% 86.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58080162 6.62% 93.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39790509 4.53% 98.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14008036 1.60% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2383478 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 885395126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 877562871 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4908226 32.44% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7617033 50.35% 82.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2603803 17.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8996464 42.62% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9189518 43.53% 86.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2923144 13.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2622809 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165654727 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353604 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880790 0.22% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 51 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429257765 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170263954 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2650510 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1189351111 66.06% 66.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 365099 0.02% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880777 0.22% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 71 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 432328086 24.01% 90.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171944726 9.55% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772033700 # Type of FU issued -system.cpu.iq.rate 1.932036 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15129062 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008538 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4445065609 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2416869316 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744809668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15422 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 52952 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3677 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784532643 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7310 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172476568 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1800520380 # Type of FU issued +system.cpu.iq.rate 1.971803 # Inst issue rate +system.cpu.iq.fu_busy_cnt 21109126 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011724 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4500567659 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2564101057 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1771520383 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18579 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 42290 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4796 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1818970082 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8914 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 181603573 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111739174 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 389536 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 327115 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45249278 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 130889258 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 280840 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 356982 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 53356872 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14923 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 606 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17048 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 593 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60916706 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 67511680 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7160873 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975288995 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 782662 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495841331 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194409464 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3475 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4447984 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83109 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 327115 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5905027 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4421064 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10326091 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752917365 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424127416 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19116335 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70637306 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60567761 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9830463 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2048969362 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 565538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 514991415 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 202517058 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4133 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4684109 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2987973 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 356982 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5998592 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4475905 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10474497 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780058647 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 427019742 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 20461733 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590948442 # number of memory reference insts executed -system.cpu.iew.exec_branches 167460417 # Number of branches executed -system.cpu.iew.exec_stores 166821026 # Number of stores executed -system.cpu.iew.exec_rate 1.911194 # Inst execution rate -system.cpu.iew.wb_sent 1749660983 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744813345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1324821434 # num instructions producing a value -system.cpu.iew.wb_consumers 1945562364 # num instructions consuming a value +system.cpu.iew.exec_refs 595482816 # number of memory reference insts executed +system.cpu.iew.exec_branches 169731635 # Number of branches executed +system.cpu.iew.exec_stores 168463074 # Number of stores executed +system.cpu.iew.exec_rate 1.949395 # Inst execution rate +system.cpu.iew.wb_sent 1776808975 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1771525179 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1358454852 # num instructions producing a value +system.cpu.iew.wb_consumers 2034017500 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.902358 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680945 # average fanout of values written-back +system.cpu.iew.wb_rate 1.940049 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667868 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446329306 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 520066569 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9930052 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 824478420 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.854492 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.436428 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 10054119 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 806925565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.894832 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.501115 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 332514113 40.33% 40.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193200456 23.43% 63.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63249703 7.67% 71.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92516022 11.22% 82.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24944995 3.03% 85.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27441019 3.33% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9353308 1.13% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11434582 1.39% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69824222 8.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 332217224 41.17% 41.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181470930 22.49% 63.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 58010021 7.19% 70.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87470883 10.84% 81.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24768584 3.07% 84.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27525249 3.41% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9963607 1.23% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11389679 1.41% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 74109388 9.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 824478420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 806925565 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -572,244 +571,245 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 69824222 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 74109388 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729972205 # The number of ROB reads -system.cpu.rob.rob_writes 4011712950 # The number of ROB writes -system.cpu.timesIdled 3360559 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31789529 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2781871447 # The number of ROB reads +system.cpu.rob.rob_writes 4168935238 # The number of ROB writes +system.cpu.timesIdled 4004498 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35571162 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.109215 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.109215 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901538 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.901538 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716307472 # number of integer regfile reads -system.cpu.int_regfile_writes 1420359444 # number of integer regfile writes -system.cpu.fp_regfile_reads 3689 # number of floating regfile reads -system.cpu.fp_regfile_writes 68 # number of floating regfile writes -system.cpu.cc_regfile_reads 597203936 # number of cc regfile reads -system.cpu.cc_regfile_writes 405421760 # number of cc regfile writes -system.cpu.misc_regfile_reads 964666021 # number of misc regfile reads +system.cpu.cpi 1.104316 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.104316 # CPI: Total CPI of All Threads +system.cpu.ipc 0.905537 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.905537 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2740022491 # number of integer regfile reads +system.cpu.int_regfile_writes 1443498634 # number of integer regfile writes +system.cpu.fp_regfile_reads 4829 # number of floating regfile reads +system.cpu.fp_regfile_writes 113 # number of floating regfile writes +system.cpu.cc_regfile_reads 599382503 # number of cc regfile reads +system.cpu.cc_regfile_writes 407768692 # number of cc regfile writes +system.cpu.misc_regfile_reads 978269285 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 699262879 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1907311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1907308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330645 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 138184 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 138184 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771752 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771752 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 151977 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7674879 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7826856 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 438272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311332928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311771200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311771200 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8849920 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4908820525 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 703796459 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1916652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1916650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2331152 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 145500 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 145500 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771513 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160475 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7692392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7852867 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 475520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311441408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311916928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311916928 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 9319232 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4920349397 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 218162491 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3952575691 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 230044243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3958184582 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5306 # number of replacements -system.cpu.icache.tags.tagsinuse 1035.768369 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161848074 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6885 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23507.345534 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5899 # number of replacements +system.cpu.icache.tags.tagsinuse 1053.974853 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 167683081 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7506 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22339.872236 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1035.768369 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.505746 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.505746 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1579 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1053.974853 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.514636 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.514636 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 250 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1221 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.770996 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 324139462 # Number of tag accesses -system.cpu.icache.tags.data_accesses 324139462 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 161850058 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161850058 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161850058 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161850058 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161850058 # number of overall hits -system.cpu.icache.overall_hits::total 161850058 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 147109 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 147109 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 147109 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 147109 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 147109 # number of overall misses -system.cpu.icache.overall_misses::total 147109 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 933905482 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 933905482 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 933905482 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 933905482 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 933905482 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 933905482 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161997167 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161997167 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161997167 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161997167 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161997167 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161997167 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000908 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000908 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000908 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000908 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000908 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000908 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.391207 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6348.391207 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6348.391207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6348.391207 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1203 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 335833041 # Number of tag accesses +system.cpu.icache.tags.data_accesses 335833041 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 167684909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 167684909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 167684909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 167684909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 167684909 # number of overall hits +system.cpu.icache.overall_hits::total 167684909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 155090 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 155090 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 155090 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 155090 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 155090 # number of overall misses +system.cpu.icache.overall_misses::total 155090 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 984545992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 984545992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 984545992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 984545992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 984545992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 984545992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 167839999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 167839999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 167839999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 167839999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 167839999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 167839999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000924 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000924 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000924 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000924 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000924 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000924 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.223561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6348.223561 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6348.223561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6348.223561 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 296 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # 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number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1980 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 145129 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 145129 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 145129 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 145129 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 145129 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 145129 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558373758 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 558373758 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558373758 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 558373758 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558373758 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 558373758 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000896 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000896 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000896 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3847.430617 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3847.430617 # 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number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 153045 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 153045 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 153045 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 153045 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 153045 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 588350757 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 588350757 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 588350757 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 588350757 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 588350757 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 588350757 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3844.299108 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3844.299108 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352885 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29666.734110 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3697072 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385254 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.596453 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 198759422000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21121.357308 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 222.494139 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61477.487070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59755.213538 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59769.881876 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529836 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.247019 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396128893 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2533932 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.329725 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1791176250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247019 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2531024 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.627952 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 389841381 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535120 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.776303 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1681469250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.627952 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998200 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998200 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 741 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 738 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3313 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 801380064 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 801380064 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 247376910 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247376910 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148233547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148233547 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395610457 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395610457 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395610457 # number of overall hits -system.cpu.dcache.overall_hits::total 395610457 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2885954 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2885954 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 926655 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 926655 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3812609 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3812609 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3812609 # number of overall misses -system.cpu.dcache.overall_misses::total 3812609 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57615846746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57615846746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26561972442 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26561972442 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84177819188 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84177819188 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84177819188 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84177819188 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250262864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250262864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 788808720 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 788808720 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 241135682 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 241135682 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148226318 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148226318 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 389362000 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 389362000 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 389362000 # number of overall hits +system.cpu.dcache.overall_hits::total 389362000 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2840916 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2840916 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 933884 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 933884 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3774800 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3774800 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3774800 # number of overall misses +system.cpu.dcache.overall_misses::total 3774800 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57099614849 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57099614849 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26803520330 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26803520330 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83903135179 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83903135179 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83903135179 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83903135179 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 243976598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 243976598 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399423066 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399423066 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399423066 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399423066 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011532 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011532 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006212 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19964.229072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19964.229072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28664.359920 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28664.359920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22078.796747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22078.796747 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6778 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 393136800 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 393136800 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 393136800 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 393136800 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011644 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011644 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006261 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006261 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009602 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009602 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009602 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009602 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20099.015546 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20099.015546 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28701.123833 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28701.123833 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22227.173673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22227.173673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6549 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 684 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 751 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.909357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.720373 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330645 # number of writebacks -system.cpu.dcache.writebacks::total 2330645 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123517 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1123517 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16974 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16974 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1140491 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1140491 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1140491 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1140491 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762437 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762437 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909681 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 909681 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2672118 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2672118 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2672118 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2672118 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30508505001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30508505001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24438286308 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24438286308 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54946791309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54946791309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54946791309 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54946791309 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007042 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007042 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006690 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17310.408827 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17310.408827 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26864.677077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26864.677077 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331152 # number of writebacks +system.cpu.dcache.writebacks::total 2331152 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1077049 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1077049 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17132 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17132 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1094181 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1094181 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1094181 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1094181 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763867 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1763867 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 916752 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 916752 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2680619 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2680619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2680619 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2680619 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30539375250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30539375250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24659789417 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24659789417 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55199164667 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55199164667 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55199164667 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55199164667 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007230 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007230 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006146 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006819 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17313.876415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17313.876415 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26899.084395 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26899.084395 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 0f18e6f39..f722ba576 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/alpha/tru64/eon +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 987d9ef76..9a57c805e 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,14 +1,16 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 17:48:27 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 11:54:16 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 77516381000 because target called exit() +Exiting @ tick 72880000500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 3dc3e1150..a85c15115 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077558 # Number of seconds simulated -sim_ticks 77558022000 # Number of ticks simulated -final_tick 77558022000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.072880 # Number of seconds simulated +sim_ticks 72880000500 # Number of ticks simulated +final_tick 72880000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184821 # Simulator instruction rate (inst/s) -host_op_rate 184821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38166348 # Simulator tick rate (ticks/s) -host_mem_usage 274476 # Number of bytes of host memory used -host_seconds 2032.10 # Real time elapsed on the host +host_inst_rate 218596 # Simulator instruction rate (inst/s) +host_op_rate 218596 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42418396 # Simulator tick rate (ticks/s) +host_mem_usage 228344 # Number of bytes of host memory used +host_seconds 1718.12 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 476544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2851852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6144355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2851852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2851852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2851852 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6144355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7446 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory +system.physmem.bytes_read::total 476992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7453 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3041932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3502964 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6544896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3041932 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3041932 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3041932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3502964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6544896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7453 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7453 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476544 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 476992 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476544 # Total read bytes from the system interface side +system.physmem.bytesReadSys 476992 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 526 # Per bank write bursts +system.physmem.perBankRdBursts::0 527 # Per bank write bursts system.physmem.perBankRdBursts::1 653 # Per bank write bursts system.physmem.perBankRdBursts::2 448 # Per bank write bursts -system.physmem.perBankRdBursts::3 600 # Per bank write bursts +system.physmem.perBankRdBursts::3 602 # Per bank write bursts system.physmem.perBankRdBursts::4 447 # Per bank write bursts system.physmem.perBankRdBursts::5 455 # Per bank write bursts -system.physmem.perBankRdBursts::6 516 # Per bank write bursts +system.physmem.perBankRdBursts::6 515 # Per bank write bursts system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 439 # Per bank write bursts +system.physmem.perBankRdBursts::8 438 # Per bank write bursts system.physmem.perBankRdBursts::9 405 # Per bank write bursts -system.physmem.perBankRdBursts::10 339 # Per bank write bursts +system.physmem.perBankRdBursts::10 337 # Per bank write bursts system.physmem.perBankRdBursts::11 306 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts -system.physmem.perBankRdBursts::13 543 # Per bank write bursts -system.physmem.perBankRdBursts::14 452 # Per bank write bursts -system.physmem.perBankRdBursts::15 379 # Per bank write bursts +system.physmem.perBankRdBursts::13 544 # Per bank write bursts +system.physmem.perBankRdBursts::14 457 # Per bank write bursts +system.physmem.perBankRdBursts::15 381 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 77557932500 # Total gap between requests +system.physmem.totGap 72879898500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7446 # Read request sizes (log2) +system.physmem.readPktSize::6 7453 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1343 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.356664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.733129 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.313012 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 424 31.57% 31.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 321 23.90% 55.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 148 11.02% 66.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 81 6.03% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 60 4.47% 76.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 47 3.50% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 36 2.68% 83.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 32 2.38% 85.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 194 14.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1343 # Bytes accessed per row activation -system.physmem.totQLat 64732500 # Total ticks spent queuing -system.physmem.totMemAccLat 204345000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8693.59 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.520710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 211.357899 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.521013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 414 30.62% 30.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 333 24.63% 55.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 156 11.54% 66.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 86 6.36% 73.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 58 4.29% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 2.66% 80.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.44% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 35 2.59% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 201 14.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1352 # Bytes accessed per row activation +system.physmem.totQLat 65605500 # Total ticks spent queuing +system.physmem.totMemAccLat 205349250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37265000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8802.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27443.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27552.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.14 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6090 # Number of row buffer hits during reads +system.physmem.readRowHits 6099 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.79 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10416053.25 # Average gap between requests -system.physmem.pageHitRate 81.79 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 73756071000 # Time in different power states -system.physmem.memoryStateTime::REF 2589600000 # Time in different power states +system.physmem.avgGap 9778599.02 # Average gap between requests +system.physmem.pageHitRate 81.83 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 69326847500 # Time in different power states +system.physmem.memoryStateTime::REF 2433600000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1205652750 # Time in different power states +system.physmem.memoryStateTime::ACT 1119126250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6144355 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4314 # Transaction distribution -system.membus.trans_dist::ReadResp 4314 # Transaction distribution -system.membus.trans_dist::ReadExReq 3132 # Transaction distribution -system.membus.trans_dist::ReadExResp 3132 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476544 # Total data (bytes) +system.membus.throughput 6544896 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4323 # Transaction distribution +system.membus.trans_dist::ReadResp 4323 # Transaction distribution +system.membus.trans_dist::ReadExReq 3130 # Transaction distribution +system.membus.trans_dist::ReadExResp 3130 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14906 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476992 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 476992 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9331000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9314500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69621500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69584750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 50345417 # Number of BP lookups -system.cpu.branchPred.condPredicted 29291104 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1215969 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26826828 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23310375 # Number of BTB hits +system.cpu.branchPred.lookups 50777064 # Number of BP lookups +system.cpu.branchPred.condPredicted 29451932 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1209851 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26262147 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23434234 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 86.892028 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9011574 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1048 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.231981 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9219036 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1140 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101817662 # DTB read hits -system.cpu.dtb.read_misses 78218 # DTB read misses +system.cpu.dtb.read_hits 102450301 # DTB read hits +system.cpu.dtb.read_misses 84837 # DTB read misses system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 101895880 # DTB read accesses -system.cpu.dtb.write_hits 78432784 # DTB write hits -system.cpu.dtb.write_misses 1485 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78434269 # DTB write accesses -system.cpu.dtb.data_hits 180250446 # DTB hits -system.cpu.dtb.data_misses 79703 # DTB misses -system.cpu.dtb.data_acv 48607 # DTB access violations -system.cpu.dtb.data_accesses 180330149 # DTB accesses -system.cpu.itb.fetch_hits 50303452 # ITB hits -system.cpu.itb.fetch_misses 374 # ITB misses +system.cpu.dtb.read_accesses 102535138 # DTB read accesses +system.cpu.dtb.write_hits 78798145 # DTB write hits +system.cpu.dtb.write_misses 1517 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 78799662 # DTB write accesses +system.cpu.dtb.data_hits 181248446 # DTB hits +system.cpu.dtb.data_misses 86354 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 181334800 # DTB accesses +system.cpu.itb.fetch_hits 50876988 # ITB hits +system.cpu.itb.fetch_misses 370 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50303826 # ITB accesses +system.cpu.itb.fetch_accesses 50877358 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,238 +285,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 155116046 # number of cpu cycles simulated +system.cpu.numCycles 145760003 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51199541 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449368258 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50345417 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32321949 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78906536 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6198249 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19757533 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10530 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50303452 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 417357 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154817464 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.902568 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324801 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 51716425 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 453983948 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50777064 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32653270 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79737605 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6706722 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8534058 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10415 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 50876988 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 470753 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 145449114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.121256 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.346528 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75910928 49.03% 49.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4292900 2.77% 51.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6887952 4.45% 56.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5378426 3.47% 59.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11777021 7.61% 67.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7819850 5.05% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5605225 3.62% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1835804 1.19% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35309358 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65711509 45.18% 45.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4353129 2.99% 48.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6951535 4.78% 52.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5417508 3.72% 56.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11887137 8.17% 64.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7943266 5.46% 70.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5717445 3.93% 74.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1835003 1.26% 75.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35632582 24.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154817464 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324566 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.896981 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56574106 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15095997 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74265148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3943304 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4938909 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9501741 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4271 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445384778 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12171 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4938909 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59715078 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4876409 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 419715 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75168099 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9699254 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440873304 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26337 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8019570 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287561386 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579637001 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 414043720 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 165593280 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 145449114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.348361 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.114599 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53474843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7565433 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 78027173 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 935486 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5446179 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9541832 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4276 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 449545046 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12399 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5446179 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 54745977 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 756567 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 422703 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77638167 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6439521 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 445569466 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 326953 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1035803 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1822362 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2964059 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 290831608 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 586091926 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 418076358 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168015567 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28029057 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36796 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 273 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27775978 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104708247 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80640808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8927201 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6403621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408496151 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 259 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401987429 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 970780 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32786458 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15509808 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154817464 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.596525 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995719 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31299279 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36843 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 279 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7560708 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105663529 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81235477 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11146516 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7815881 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 412301107 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 261 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 404056264 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1312815 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35808008 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18428665 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 145449114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.777991 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.042688 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28475792 18.39% 18.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25868593 16.71% 35.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25622739 16.55% 51.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24250418 15.66% 67.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21294797 13.75% 81.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15492171 10.01% 91.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8526240 5.51% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3969091 2.56% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1317623 0.85% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25098996 17.26% 17.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 21117633 14.52% 31.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22669138 15.59% 47.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22701668 15.61% 62.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23036562 15.84% 78.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15514820 10.67% 89.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8774349 6.03% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 5158675 3.55% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1377273 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154817464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 145449114 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 33961 0.29% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 60734 0.51% 0.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 4893 0.04% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5332 0.05% 0.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1940982 16.38% 17.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1755182 14.82% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5081532 42.89% 74.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2964138 25.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 102079 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 61666 0.50% 1.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 48308 0.39% 1.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3198 0.03% 1.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1785372 14.39% 16.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1353790 10.91% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5374985 43.31% 70.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3681074 29.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155819959 38.76% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126233 0.53% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32858833 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7513495 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793143 0.69% 50.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16555819 4.12% 54.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584570 0.39% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103403919 25.72% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79297877 19.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 156664975 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2127225 0.53% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32964847 8.16% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7504684 1.86% 49.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2799878 0.69% 50.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16685729 4.13% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1581715 0.39% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 104147450 25.78% 80.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79546180 19.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401987429 # Type of FU issued -system.cpu.iq.rate 2.591527 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11846754 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029470 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634443309 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260407475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234772020 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 337166547 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180924376 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161447715 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241509351 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172291251 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15019191 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 404056264 # Type of FU issued +system.cpu.iq.rate 2.772065 # Inst issue rate +system.cpu.iq.fu_busy_cnt 12410472 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.030715 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 628197329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 263376555 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 235877430 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 339087600 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 184792904 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162158669 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 243128966 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 173304189 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17056087 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9953760 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 111699 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 48994 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7120079 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10909042 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 154314 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 60406 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7714748 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260856 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3918 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 360272 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4287 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4938909 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2515248 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 368703 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 433326930 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 121866 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104708247 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80640808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 259 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 84 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 84 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 48994 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 963874 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 408153 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1372027 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398387733 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101944518 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3599696 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5446179 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1032 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 211342 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 437229791 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 59050 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105663529 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81235477 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 261 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4770 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 204982 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 60406 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 953368 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 408257 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1361625 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 400360320 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 102583778 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3695944 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24830520 # number of nop insts executed -system.cpu.iew.exec_refs 180378816 # number of memory reference insts executed -system.cpu.iew.exec_branches 46578472 # Number of branches executed -system.cpu.iew.exec_stores 78434298 # Number of stores executed -system.cpu.iew.exec_rate 2.568321 # Inst execution rate -system.cpu.iew.wb_sent 396855480 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396219735 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193571599 # num instructions producing a value -system.cpu.iew.wb_consumers 271152784 # num instructions consuming a value +system.cpu.iew.exec_nop 24928423 # number of nop insts executed +system.cpu.iew.exec_refs 181383470 # number of memory reference insts executed +system.cpu.iew.exec_branches 46799473 # Number of branches executed +system.cpu.iew.exec_stores 78799692 # Number of stores executed +system.cpu.iew.exec_rate 2.746709 # Inst execution rate +system.cpu.iew.wb_sent 398772945 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 398036099 # cumulative count of insts written-back +system.cpu.iew.wb_producers 201124096 # num instructions producing a value +system.cpu.iew.wb_consumers 293988661 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.554344 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713884 # average fanout of values written-back +system.cpu.iew.wb_rate 2.730764 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.684122 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34693909 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 38564789 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1211780 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149878555 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.659917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.995453 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1205629 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 140002935 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.847544 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.108853 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55522565 37.05% 37.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22544256 15.04% 52.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13057076 8.71% 60.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11473348 7.66% 68.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8182798 5.46% 73.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5442795 3.63% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5157024 3.44% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3290724 2.20% 83.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25207969 16.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50426990 36.02% 36.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 20519996 14.66% 50.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11173587 7.98% 58.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9865184 7.05% 65.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7560021 5.40% 71.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4963241 3.55% 74.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4885893 3.49% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3033970 2.17% 80.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 27574053 19.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149878555 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 140002935 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -562,227 +563,227 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 25207969 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 27574053 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 558026101 # The number of ROB reads -system.cpu.rob.rob_writes 871664409 # The number of ROB writes -system.cpu.timesIdled 3592 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 298582 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 549655277 # The number of ROB reads +system.cpu.rob.rob_writes 879919465 # The number of ROB writes +system.cpu.timesIdled 3916 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 310889 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.413010 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.413010 # CPI: Total CPI of All Threads -system.cpu.ipc 2.421251 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.421251 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398150942 # number of integer regfile reads -system.cpu.int_regfile_writes 170167166 # number of integer regfile writes -system.cpu.fp_regfile_reads 156627293 # number of floating regfile reads -system.cpu.fp_regfile_writes 104100522 # number of floating regfile writes +system.cpu.cpi 0.388098 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.388098 # CPI: Total CPI of All Threads +system.cpu.ipc 2.576666 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.576666 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 400324800 # number of integer regfile reads +system.cpu.int_regfile_writes 170964393 # number of integer regfile writes +system.cpu.fp_regfile_reads 157088507 # number of floating regfile reads +system.cpu.fp_regfile_writes 104631166 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7339228 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3191 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3191 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8126 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9007 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17133 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 569216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 569216 # Total data (bytes) +system.cpu.toL2Bus.throughput 7854226 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5074 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5074 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 670 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17218 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 572416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 572416 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5102000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5142000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6747750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6782500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6677500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2136 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.591331 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50297811 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4063 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12379.476003 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2155 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.273556 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50871213 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4083 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12459.273328 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.591331 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.893843 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.893843 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1340 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 100610967 # Number of tag accesses -system.cpu.icache.tags.data_accesses 100610967 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 50297811 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50297811 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50297811 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50297811 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50297811 # number of overall hits -system.cpu.icache.overall_hits::total 50297811 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5641 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5641 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5641 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5641 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5641 # number of overall misses -system.cpu.icache.overall_misses::total 5641 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 335074000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 335074000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 335074000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 335074000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 335074000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 335074000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50303452 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50303452 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50303452 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50303452 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50303452 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50303452 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59399.751817 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59399.751817 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59399.751817 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59399.751817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59399.751817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59399.751817 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 446 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.555556 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.273556 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 101758059 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101758059 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 50871213 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50871213 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50871213 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50871213 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50871213 # number of overall hits +system.cpu.icache.overall_hits::total 50871213 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5775 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5775 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5775 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5775 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5775 # number of overall misses +system.cpu.icache.overall_misses::total 5775 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 343384000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 343384000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 343384000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 343384000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 343384000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 343384000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50876988 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50876988 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50876988 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50876988 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50876988 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50876988 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000114 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000114 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000114 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000114 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000114 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000114 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59460.432900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59460.432900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59460.432900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59460.432900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59460.432900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59460.432900 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 389 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 400 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.571429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 400 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1578 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1578 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1578 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1578 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1578 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1578 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4063 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4063 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4063 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4063 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4063 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4063 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249433250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249433250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249433250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249433250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249433250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249433250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61391.397982 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61391.397982 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61391.397982 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61391.397982 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61391.397982 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61391.397982 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1692 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1692 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1692 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1692 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1692 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1692 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4083 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4083 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4083 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4083 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4083 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4083 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250419500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 250419500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250419500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 250419500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250419500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 250419500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61332.231203 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61332.231203 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61332.231203 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61332.231203 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61332.231203 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61332.231203 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4004.954677 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 821 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4850 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.169278 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4014.278169 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 853 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4857 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.175623 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.321858 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2975.631846 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 658.000972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011332 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020081 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122222 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4850 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 573 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4031 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148010 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 79193 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 79193 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 607 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 127 # 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Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804822 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804822 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3294.829760 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 320114012 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 320114012 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86532394 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86532394 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500878 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500878 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3117 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830322 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 317106037 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 317106037 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 85028391 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 85028391 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501342 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501342 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 160033272 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 160033272 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 160033272 # number of overall hits -system.cpu.dcache.overall_hits::total 160033272 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1791 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1791 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19851 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19851 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21642 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21642 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21642 # number of overall misses -system.cpu.dcache.overall_misses::total 21642 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 112278750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 112278750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1112532070 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1112532070 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1224810820 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1224810820 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1224810820 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1224810820 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86534185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86534185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 158529733 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 158529733 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 158529733 # number of overall hits +system.cpu.dcache.overall_hits::total 158529733 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1799 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1799 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19387 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19387 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21186 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21186 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21186 # number of overall misses +system.cpu.dcache.overall_misses::total 21186 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 115077500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 115077500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1124516028 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1124516028 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239593528 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239593528 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239593528 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239593528 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85030190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85030190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 160054914 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 160054914 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 160054914 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 160054914 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 158550919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 158550919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 158550919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 158550919 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62690.536013 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62690.536013 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56044.132286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56044.132286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56594.160429 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56594.160429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56594.160429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56594.160429 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 40644 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000264 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000264 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63967.481934 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63967.481934 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58003.612111 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58003.612111 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58510.031530 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58510.031530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58510.031530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58510.031530 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 44616 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 797 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.682819 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.979925 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 806 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 806 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16660 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16660 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17466 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17466 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17466 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17466 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 985 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 985 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67500250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67500250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 233649750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 233649750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 301150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 301150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 301150000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 301150000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 670 # number of writebacks +system.cpu.dcache.writebacks::total 670 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 808 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 808 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16187 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16187 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 991 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 991 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4191 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4191 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4191 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4191 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67828000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67828000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235012500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 235012500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 302840500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 302840500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 302840500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 302840500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68528.172589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68528.172589 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73221.482294 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73221.482294 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72114.463602 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72114.463602 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72114.463602 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72114.463602 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68443.995964 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68443.995964 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73441.406250 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73441.406250 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72259.723216 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72259.723216 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72259.723216 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72259.723216 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 2cd58faa0..1aa11a694 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,7 +699,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/eon +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr index cce4a65d9..a25196116 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -warn: CP14 unimplemented crn[15], opc1[7], crm[4], opc2[6] getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index d9e911681..35d0eb5ad 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:23:42 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:42:59 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x4718040 + 0: system.cpu.isa: ISA system set to: 0 0x6560400 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 @@ -14,4 +14,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.060000 -Exiting @ tick 68503867000 because target called exit() +Exiting @ tick 64766858000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index c61e70c3d..dff7f3d85 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068540 # Number of seconds simulated -sim_ticks 68540241500 # Number of ticks simulated -final_tick 68540241500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064767 # Number of seconds simulated +sim_ticks 64766858000 # Number of ticks simulated +final_tick 64766858000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122061 # Simulator instruction rate (inst/s) -host_op_rate 156050 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30641006 # Simulator tick rate (ticks/s) -host_mem_usage 321880 # Number of bytes of host memory used -host_seconds 2236.88 # Real time elapsed on the host +host_inst_rate 139181 # Simulator instruction rate (inst/s) +host_op_rate 177937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33015138 # Simulator tick rate (ticks/s) +host_mem_usage 270440 # Number of bytes of host memory used +host_seconds 1961.73 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory -system.physmem.bytes_read::total 466368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7287 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2829287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3975008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6804295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2829287 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2829287 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2829287 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3975008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6804295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7287 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272960 # Number of bytes read from this memory +system.physmem.bytes_read::total 467648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4265 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3005982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4214501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7220483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3005982 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3005982 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3005982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4214501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7220483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7307 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7287 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7307 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466368 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 467648 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466368 # Total read bytes from the system interface side +system.physmem.bytesReadSys 467648 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 604 # Per bank write bursts -system.physmem.perBankRdBursts::1 802 # Per bank write bursts -system.physmem.perBankRdBursts::2 607 # Per bank write bursts -system.physmem.perBankRdBursts::3 525 # Per bank write bursts -system.physmem.perBankRdBursts::4 444 # Per bank write bursts -system.physmem.perBankRdBursts::5 349 # Per bank write bursts -system.physmem.perBankRdBursts::6 161 # Per bank write bursts +system.physmem.perBankRdBursts::1 805 # Per bank write bursts +system.physmem.perBankRdBursts::2 608 # Per bank write bursts +system.physmem.perBankRdBursts::3 526 # Per bank write bursts +system.physmem.perBankRdBursts::4 446 # Per bank write bursts +system.physmem.perBankRdBursts::5 361 # Per bank write bursts +system.physmem.perBankRdBursts::6 162 # Per bank write bursts system.physmem.perBankRdBursts::7 221 # Per bank write bursts -system.physmem.perBankRdBursts::8 206 # Per bank write bursts -system.physmem.perBankRdBursts::9 292 # Per bank write bursts -system.physmem.perBankRdBursts::10 324 # Per bank write bursts -system.physmem.perBankRdBursts::11 416 # Per bank write bursts -system.physmem.perBankRdBursts::12 533 # Per bank write bursts -system.physmem.perBankRdBursts::13 685 # Per bank write bursts -system.physmem.perBankRdBursts::14 612 # Per bank write bursts -system.physmem.perBankRdBursts::15 506 # Per bank write bursts +system.physmem.perBankRdBursts::8 208 # Per bank write bursts +system.physmem.perBankRdBursts::9 290 # Per bank write bursts +system.physmem.perBankRdBursts::10 326 # Per bank write bursts +system.physmem.perBankRdBursts::11 415 # Per bank write bursts +system.physmem.perBankRdBursts::12 530 # Per bank write bursts +system.physmem.perBankRdBursts::13 688 # Per bank write bursts +system.physmem.perBankRdBursts::14 613 # Per bank write bursts +system.physmem.perBankRdBursts::15 504 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68540041000 # Total gap between requests +system.physmem.totGap 64766656000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7287 # Read request sizes (log2) +system.physmem.readPktSize::6 7307 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,74 +186,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1441 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.087439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.561369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.705535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 517 35.88% 35.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 362 25.12% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 132 9.16% 70.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 71 4.93% 75.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 61 4.23% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 42 2.91% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 2.43% 84.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 1.80% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 195 13.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1441 # Bytes accessed per row activation -system.physmem.totQLat 60227500 # Total ticks spent queuing -system.physmem.totMemAccLat 196858750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8265.06 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.430917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.825713 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.055999 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 519 35.50% 35.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 381 26.06% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 138 9.44% 71.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 81 5.54% 76.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 49 3.35% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 2.80% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 1.85% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 24 1.64% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 202 13.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1462 # Bytes accessed per row activation +system.physmem.totQLat 61897500 # Total ticks spent queuing +system.physmem.totMemAccLat 198903750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8470.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27015.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27220.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.80 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.22 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5834 # Number of row buffer hits during reads +system.physmem.readRowHits 5841 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.94 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9405796.76 # Average gap between requests -system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 64419207500 # Time in different power states -system.physmem.memoryStateTime::REF 2288520000 # Time in different power states +system.physmem.avgGap 8863645.27 # Average gap between requests +system.physmem.pageHitRate 79.94 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 60826618500 # Time in different power states +system.physmem.memoryStateTime::REF 2162680000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1827118750 # Time in different power states +system.physmem.memoryStateTime::ACT 1777002750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6804295 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4468 # Transaction distribution -system.membus.trans_dist::ReadResp 4468 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.throughput 7220483 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4488 # Transaction distribution +system.membus.trans_dist::ReadResp 4488 # Transaction distribution +system.membus.trans_dist::UpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution system.membus.trans_dist::ReadExReq 2819 # Transaction distribution system.membus.trans_dist::ReadExResp 2819 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14578 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14578 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466368 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466368 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14620 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 467648 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 467648 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8924000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8747000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67911998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67869997 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 35427097 # Number of BP lookups -system.cpu.branchPred.condPredicted 21222481 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1662305 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19504890 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16830620 # Number of BTB hits +system.cpu.branchPred.lookups 36489443 # Number of BP lookups +system.cpu.branchPred.condPredicted 21873029 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1677086 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19094793 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17269038 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 86.289233 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6785276 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8391 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 90.438467 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7051020 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 13969 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,239 +339,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137080484 # number of cpu cycles simulated +system.cpu.numCycles 129533717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39013094 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 318011666 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35427097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23615896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70957700 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6891338 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21536315 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 110 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1697 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 56 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37608451 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 511125 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136726497 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983044 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454276 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 40065447 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 327212599 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36489443 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24320058 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 72959266 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8220576 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 9614052 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 38688978 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 553522 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 129167933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.246487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.483221 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66399200 48.56% 48.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6788638 4.97% 53.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5707530 4.17% 57.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6111990 4.47% 62.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4922665 3.60% 65.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4080012 2.98% 68.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3180881 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4139139 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35396442 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 56843632 44.01% 44.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6961373 5.39% 49.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5946764 4.60% 54.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6307392 4.88% 58.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5037669 3.90% 62.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4117601 3.19% 65.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3252291 2.52% 68.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4297115 3.33% 71.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36404096 28.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136726497 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258440 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.319890 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45526376 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16684464 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66829825 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2537018 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5148814 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7346336 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401912579 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 214046 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5148814 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51079671 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1913308 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 333807 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63753347 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14497550 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394307650 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1657315 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10195595 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 22429 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432708181 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2738145852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575813049 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200323476 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 129167933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.281698 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.526081 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 43040295 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8294549 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70704377 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 671384 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6457328 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7532389 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70819 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 413867422 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 226829 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6457328 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45867800 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 237018 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 350499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68547941 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7707347 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 406294876 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2372159 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1808118 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3023073 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 35743 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 447044512 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2837901709 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1622364142 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 210216215 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48141988 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11963 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11962 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36553940 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103619662 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91398989 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4293575 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5309451 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384641768 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22898 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374271543 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1203075 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34859337 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 100548351 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 778 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136726497 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.737374 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024550 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 62478319 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 12155 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12154 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14556867 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106022236 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93881214 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5184446 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5926802 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 394612578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23007 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378124394 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2730874 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 45321613 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 166213653 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 887 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 129167933 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.927386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.138502 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25150398 18.39% 18.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19938048 14.58% 32.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20598425 15.07% 48.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18168946 13.29% 61.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24025170 17.57% 78.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15741501 11.51% 90.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8821837 6.45% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3366776 2.46% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 915396 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23289729 18.03% 18.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17219322 13.33% 31.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17000952 13.16% 44.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 16863081 13.06% 57.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22471092 17.40% 74.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15547625 12.04% 87.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10749417 8.32% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4018790 3.11% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2007925 1.55% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136726497 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 129167933 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8454 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4686 0.03% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46141 0.26% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 3549 0.02% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 438 0.00% 0.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 186673 1.05% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 3981 0.02% 1.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241129 1.36% 2.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9262679 52.30% 55.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7952866 44.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 70479 0.37% 0.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4864 0.03% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 116556 0.60% 1.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 10208 0.05% 1.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 2498 0.01% 1.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 1.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 192000 1.00% 2.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6622 0.03% 2.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 104426 0.54% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10354293 53.72% 56.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8412591 43.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126495771 33.80% 33.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175574 0.58% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6778108 1.81% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8473024 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3429632 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595745 0.43% 39.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20862309 5.57% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172511 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7129172 1.90% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101679299 27.17% 76.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88305111 23.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 127925021 33.83% 33.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175908 0.58% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 6 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6792348 1.80% 36.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8524841 2.25% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3465145 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600581 0.42% 39.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21035851 5.56% 45.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175261 1.90% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134800 1.89% 49.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103072110 27.26% 76.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 89047235 23.55% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374271543 # Type of FU issued -system.cpu.iq.rate 2.730305 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17710599 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047320 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654796096 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289211293 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250149926 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249387161 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130326745 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118060008 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263377407 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128604735 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11093990 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378124394 # Type of FU issued +system.cpu.iq.rate 2.919119 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19274540 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.050974 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653351237 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 300092831 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252502629 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 254070898 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 139884609 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118704168 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266903131 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 130495803 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12681428 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8970914 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108859 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14127 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9023406 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11373488 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 85866 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20564 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11505631 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 175522 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1863 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 299397 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2800 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5148814 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 279698 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35585 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384666248 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 872586 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103619662 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91398989 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11864 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 344 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14127 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1301679 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370144 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1671823 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370317109 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100386827 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3954434 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6457328 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4758 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17342 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 394637253 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 715920 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106022236 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93881214 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11972 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 602 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17793 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20564 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1298443 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 381522 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1679965 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373834206 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101210545 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4290188 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1582 # number of nop insts executed -system.cpu.iew.exec_refs 187618668 # number of memory reference insts executed -system.cpu.iew.exec_branches 32015275 # Number of branches executed -system.cpu.iew.exec_stores 87231841 # Number of stores executed -system.cpu.iew.exec_rate 2.701458 # Inst execution rate -system.cpu.iew.wb_sent 368883883 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368209934 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183051685 # num instructions producing a value -system.cpu.iew.wb_consumers 363776414 # num instructions consuming a value +system.cpu.iew.exec_nop 1668 # number of nop insts executed +system.cpu.iew.exec_refs 189079864 # number of memory reference insts executed +system.cpu.iew.exec_branches 32211788 # Number of branches executed +system.cpu.iew.exec_stores 87869319 # Number of stores executed +system.cpu.iew.exec_rate 2.885999 # Inst execution rate +system.cpu.iew.wb_sent 372104883 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371206797 # cumulative count of insts written-back +system.cpu.iew.wb_producers 194146455 # num instructions producing a value +system.cpu.iew.wb_consumers 400678068 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.686086 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503198 # average fanout of values written-back +system.cpu.iew.wb_rate 2.865716 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.484545 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35601258 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 45577363 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1593594 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131577683 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.652920 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.658674 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1607073 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122710605 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.844620 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.797026 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34743119 26.41% 26.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28469178 21.64% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13363377 10.16% 58.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11438386 8.69% 66.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13773451 10.47% 77.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7412867 5.63% 82.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3865563 2.94% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3891482 2.96% 88.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14620260 11.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31366686 25.56% 25.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25118346 20.47% 46.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 12977285 10.58% 56.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10004590 8.15% 64.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11874018 9.68% 74.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6164142 5.02% 79.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4197962 3.42% 82.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3586787 2.92% 85.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 17420789 14.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131577683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122710605 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -617,237 +618,237 @@ system.cpu.commit.op_class_0::MemWrite 82375583 23.60% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 349065061 # Class of committed instruction -system.cpu.commit.bw_lim_events 14620260 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 17420789 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501621219 # The number of ROB reads -system.cpu.rob.rob_writes 774485510 # The number of ROB writes -system.cpu.timesIdled 6746 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 353987 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 499929717 # The number of ROB reads +system.cpu.rob.rob_writes 795751266 # The number of ROB writes +system.cpu.timesIdled 6646 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 365784 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.502059 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.502059 # CPI: Total CPI of All Threads -system.cpu.ipc 1.991799 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.991799 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1770130874 # number of integer regfile reads -system.cpu.int_regfile_writes 233038396 # number of integer regfile writes -system.cpu.fp_regfile_reads 188133896 # number of floating regfile reads -system.cpu.fp_regfile_writes 132498519 # number of floating regfile writes -system.cpu.misc_regfile_reads 1201060026 # number of misc regfile reads +system.cpu.cpi 0.474419 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.474419 # CPI: Total CPI of All Threads +system.cpu.ipc 2.107843 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.107843 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1785673756 # number of integer regfile reads +system.cpu.int_regfile_writes 235086257 # number of integer regfile writes +system.cpu.fp_regfile_reads 188627632 # number of floating regfile reads +system.cpu.fp_regfile_writes 133402932 # number of floating regfile writes +system.cpu.misc_regfile_reads 1210936846 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20063659 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1041 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2837 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41933 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 362304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1374912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1374912 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11785500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 21331404 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17706 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17706 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1042 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2839 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31825 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 42135 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1018304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 363072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1381376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1381376 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11837000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24279239 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24407489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7466709 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7420712 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13936 # number of replacements -system.cpu.icache.tags.tagsinuse 1847.607729 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37591137 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15825 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2375.427299 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 14019 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.281625 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 38671572 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15912 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2430.340121 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1847.607729 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902152 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902152 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1525 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 75232724 # Number of tag accesses -system.cpu.icache.tags.data_accesses 75232724 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37591137 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37591137 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37591137 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37591137 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37591137 # number of overall hits -system.cpu.icache.overall_hits::total 37591137 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17312 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17312 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17312 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17312 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17312 # number of overall misses -system.cpu.icache.overall_misses::total 17312 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 452091985 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 452091985 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 452091985 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 452091985 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 452091985 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 452091985 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37608449 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37608449 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37608449 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37608449 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37608449 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37608449 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000460 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000460 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000460 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000460 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000460 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000460 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26114.370668 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26114.370668 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26114.370668 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26114.370668 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26114.370668 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26114.370668 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 970 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.281625 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904434 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904434 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1893 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.924316 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 77393866 # Number of tag accesses +system.cpu.icache.tags.data_accesses 77393866 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 38671572 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 38671572 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 38671572 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 38671572 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 38671572 # number of overall hits +system.cpu.icache.overall_hits::total 38671572 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17404 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17404 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17404 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17404 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17404 # number of overall misses +system.cpu.icache.overall_misses::total 17404 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 452089736 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 452089736 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 452089736 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 452089736 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 452089736 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 452089736 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 38688976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 38688976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 38688976 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 38688976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 38688976 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 38688976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000450 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000450 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000450 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000450 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000450 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000450 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25976.197196 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25976.197196 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25976.197196 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25976.197196 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1041 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 51.052632 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.318182 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15826 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15826 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15826 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15826 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15826 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 356931509 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 356931509 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 356931509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 356931509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 356931509 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 356931509 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22553.488500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22553.488500 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22553.488500 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22553.488500 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22553.488500 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22553.488500 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15914 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15914 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15914 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359079759 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359079759 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359079759 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359079759 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359079759 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359079759 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000411 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000411 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000411 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22563.765175 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22563.765175 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3938.278477 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13178 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.443085 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3952.099762 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13258 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5413 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.449289 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 377.930800 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2772.496816 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 787.850861 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011534 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084610 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.024043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120187 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5394 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4004 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164612 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180111 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180111 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12781 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 302 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13083 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1041 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1041 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.920967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355710 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.920967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355710 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57754.520053 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61704.875519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59027.295009 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58135.331678 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58135.331678 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57610.891089 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59277.190510 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58584.328256 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57610.891089 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59277.190510 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58584.328256 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58728.804541 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58728.804541 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57754.520053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59737.807737 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.139045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57754.520053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59737.807737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.139045 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1423 # number of replacements -system.cpu.dcache.tags.tagsinuse 3106.690369 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170987022 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4620 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37010.177922 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1426 # number of replacements +system.cpu.dcache.tags.tagsinuse 3109.599416 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170089338 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4631 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36728.425394 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3106.690369 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.758469 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.758469 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 683 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2448 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342028974 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342028974 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88933648 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88933648 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031473 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10994 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10994 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3109.599416 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.759180 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.759180 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3205 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 688 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.782471 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 340235219 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 340235219 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88036573 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88036573 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82030829 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82030829 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11027 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11027 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170965121 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170965121 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170965121 # number of overall hits -system.cpu.dcache.overall_hits::total 170965121 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3973 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3973 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21192 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21192 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170067402 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170067402 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170067402 # number of overall hits +system.cpu.dcache.overall_hits::total 170067402 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4132 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4132 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21836 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21836 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25165 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25165 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25165 # number of overall misses -system.cpu.dcache.overall_misses::total 25165 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 236002703 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 236002703 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1249306876 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1249306876 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25968 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25968 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25968 # number of overall misses +system.cpu.dcache.overall_misses::total 25968 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 240617705 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 240617705 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1280155018 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1280155018 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1485309579 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1485309579 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1485309579 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1485309579 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88937621 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88937621 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1520772723 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1520772723 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1520772723 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1520772723 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88040705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88040705 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10996 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10996 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11029 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170990286 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170990286 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170990286 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170990286 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59401.636798 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59401.636798 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58951.815591 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58951.815591 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 170093370 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170093370 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170093370 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170093370 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000266 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000266 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58232.745644 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58232.745644 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58625.893845 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58625.893845 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59022.832466 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59022.832466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59022.832466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59022.832466 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25911 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1248 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 444 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.358108 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58563.336530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58563.336530 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30153 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1162 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 553 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.526221 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.833333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks -system.cpu.dcache.writebacks::total 1041 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2189 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2189 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18354 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18354 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1042 # number of writebacks +system.cpu.dcache.writebacks::total 1042 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2339 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2339 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18995 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18995 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20543 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20543 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20543 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20543 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1784 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1784 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2838 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2838 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4622 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4622 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4622 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4622 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114103043 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 114103043 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201967248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 201967248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316070291 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 316070291 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316070291 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 316070291 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 21334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21334 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1793 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1793 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4634 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4634 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4634 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4634 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115097041 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 115097041 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203424247 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 203424247 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 318521288 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 318521288 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318521288 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 318521288 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -1044,14 +1045,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63959.104821 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63959.104821 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71165.344609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71165.344609 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68383.879489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68383.879489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68383.879489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68383.879489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64192.437814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64192.437814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71603.043647 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71603.043647 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 328cf1d6a..fac3ae4a0 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 722b9bf34..e5189014f 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 17:50:38 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 21:27:33 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 631518097500 because target called exit() +Exiting @ tick 635929494500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 2a5fe76f4..ea32f292f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629061 # Number of seconds simulated -sim_ticks 629060517500 # Number of ticks simulated -final_tick 629060517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.635929 # Number of seconds simulated +sim_ticks 635929494500 # Number of ticks simulated +final_tick 635929494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141618 # Simulator instruction rate (inst/s) -host_op_rate 141618 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48866772 # Simulator tick rate (ticks/s) -host_mem_usage 278492 # Number of bytes of host memory used -host_seconds 12872.97 # Real time elapsed on the host +host_inst_rate 162504 # Simulator instruction rate (inst/s) +host_op_rate 162504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56685894 # Simulator tick rate (ticks/s) +host_mem_usage 228544 # Number of bytes of host memory used +host_seconds 11218.48 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 177024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295744 # Number of bytes read from this memory -system.physmem.bytes_read::total 30472768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 177024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 177024 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295616 # Number of bytes read from this memory +system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176704 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2766 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473371 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476137 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2761 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473369 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 281410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48160301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48441711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 281410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 281410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6807154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6807154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6807154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 281410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48160301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55248866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476137 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 277867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47639898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47917765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 277867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 277867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6733627 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6733627 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6733627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 277867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47639898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54651392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476130 # Number of read requests accepted system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476137 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 476130 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30454016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18752 # Total number of bytes read from write queue -system.physmem.bytesWritten 4280576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30472768 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30454144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue +system.physmem.bytesWritten 4280960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30472320 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 293 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29448 # Per bank write bursts -system.physmem.perBankRdBursts::1 29785 # Per bank write bursts -system.physmem.perBankRdBursts::2 29839 # Per bank write bursts -system.physmem.perBankRdBursts::3 29775 # Per bank write bursts -system.physmem.perBankRdBursts::4 29682 # Per bank write bursts -system.physmem.perBankRdBursts::5 29757 # Per bank write bursts -system.physmem.perBankRdBursts::6 29851 # Per bank write bursts -system.physmem.perBankRdBursts::7 29843 # Per bank write bursts -system.physmem.perBankRdBursts::8 29760 # Per bank write bursts -system.physmem.perBankRdBursts::9 29872 # Per bank write bursts -system.physmem.perBankRdBursts::10 29842 # Per bank write bursts -system.physmem.perBankRdBursts::11 29921 # Per bank write bursts -system.physmem.perBankRdBursts::12 29772 # Per bank write bursts -system.physmem.perBankRdBursts::13 29569 # Per bank write bursts +system.physmem.perBankRdBursts::0 29443 # Per bank write bursts +system.physmem.perBankRdBursts::1 29787 # Per bank write bursts +system.physmem.perBankRdBursts::2 29841 # Per bank write bursts +system.physmem.perBankRdBursts::3 29778 # Per bank write bursts +system.physmem.perBankRdBursts::4 29678 # Per bank write bursts +system.physmem.perBankRdBursts::5 29749 # Per bank write bursts +system.physmem.perBankRdBursts::6 29855 # Per bank write bursts +system.physmem.perBankRdBursts::7 29842 # Per bank write bursts +system.physmem.perBankRdBursts::8 29764 # Per bank write bursts +system.physmem.perBankRdBursts::9 29879 # Per bank write bursts +system.physmem.perBankRdBursts::10 29841 # Per bank write bursts +system.physmem.perBankRdBursts::11 29912 # Per bank write bursts +system.physmem.perBankRdBursts::12 29773 # Per bank write bursts +system.physmem.perBankRdBursts::13 29578 # Per bank write bursts system.physmem.perBankRdBursts::14 29495 # Per bank write bursts -system.physmem.perBankRdBursts::15 29633 # Per bank write bursts +system.physmem.perBankRdBursts::15 29631 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6 4262 # Pe system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4224 # Per bank write bursts +system.physmem.perBankWrBursts::10 4230 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 629060434500 # Total gap between requests +system.physmem.totGap 635929412000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476137 # Read request sizes (log2) +system.physmem.readPktSize::6 476130 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 408324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,23 +144,23 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see @@ -193,111 +193,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 186678 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 186.061046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.793811 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 215.276022 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 65820 35.26% 35.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 88170 47.23% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20719 11.10% 93.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 470 0.25% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 393 0.21% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 522 0.28% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 523 0.28% 94.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 573 0.31% 94.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9488 5.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 186678 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 115.896168 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.909110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1130.293958 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4026 99.53% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 6 0.15% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 12 0.30% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 185909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 186.826200 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.409449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 215.527814 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 65070 35.00% 35.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 87777 47.22% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 21119 11.36% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 448 0.24% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 430 0.23% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 462 0.25% 94.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 533 0.29% 94.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 575 0.31% 94.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9495 5.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 185909 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 117.004698 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.982691 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1132.774880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4024 99.51% 99.51% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 3 0.07% 99.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 15 0.37% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.534981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.885131 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2961 73.20% 73.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 5 0.12% 73.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1078 26.65% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 5368112500 # Total ticks spent queuing -system.physmem.totMemAccLat 14290187500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2379220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11281.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.540554 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.517518 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.888872 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2948 72.90% 72.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 11 0.27% 73.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1080 26.71% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads +system.physmem.totQLat 4824243250 # Total ticks spent queuing +system.physmem.totMemAccLat 13746355750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2379230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10138.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30031.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28888.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 47.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 47.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 305539 # Number of row buffer hits during reads -system.physmem.writeRowHits 50504 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.48 # Row buffer hit rate for writes -system.physmem.avgGap 1158394.67 # Average gap between requests -system.physmem.pageHitRate 65.60 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 166526885000 # Time in different power states -system.physmem.memoryStateTime::REF 21005660000 # Time in different power states +system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing +system.physmem.readRowHits 306274 # Number of row buffer hits during reads +system.physmem.writeRowHits 50544 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes +system.physmem.avgGap 1171058.77 # Average gap between requests +system.physmem.pageHitRate 65.74 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 176454220250 # Time in different power states +system.physmem.memoryStateTime::REF 21234980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 441526652500 # Time in different power states +system.physmem.memoryStateTime::ACT 438237480500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 55248866 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409283 # Transaction distribution -system.membus.trans_dist::ReadResp 409283 # Transaction distribution +system.membus.throughput 54651392 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409276 # Transaction distribution +system.membus.trans_dist::ReadResp 409276 # Transaction distribution system.membus.trans_dist::Writeback 66908 # Transaction distribution system.membus.trans_dist::ReadExReq 66854 # Transaction distribution system.membus.trans_dist::ReadExResp 66854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019182 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019182 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34754880 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34754880 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019168 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34754432 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34754432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1216375500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1134499000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4475214250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4452935500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 388838415 # Number of BP lookups -system.cpu.branchPred.condPredicted 256496026 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25500542 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 313163608 # Number of BTB lookups -system.cpu.branchPred.BTBHits 257889708 # Number of BTB hits +system.cpu.branchPred.lookups 402497188 # Number of BP lookups +system.cpu.branchPred.condPredicted 262794086 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25809520 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 329924346 # Number of BTB lookups +system.cpu.branchPred.BTBHits 269779526 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.349833 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 56962894 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6655 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.770118 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 58338435 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6772 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 520477201 # DTB read hits -system.cpu.dtb.read_misses 601468 # DTB read misses +system.cpu.dtb.read_hits 522325129 # DTB read hits +system.cpu.dtb.read_misses 599769 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 521078669 # DTB read accesses -system.cpu.dtb.write_hits 282725842 # DTB write hits -system.cpu.dtb.write_misses 50160 # DTB write misses +system.cpu.dtb.read_accesses 522924898 # DTB read accesses +system.cpu.dtb.write_hits 290323928 # DTB write hits +system.cpu.dtb.write_misses 50170 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 282776002 # DTB write accesses -system.cpu.dtb.data_hits 803203043 # DTB hits -system.cpu.dtb.data_misses 651628 # DTB misses +system.cpu.dtb.write_accesses 290374098 # DTB write accesses +system.cpu.dtb.data_hits 812649057 # DTB hits +system.cpu.dtb.data_misses 649939 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 803854671 # DTB accesses -system.cpu.itb.fetch_hits 392472204 # ITB hits -system.cpu.itb.fetch_misses 553 # ITB misses +system.cpu.dtb.data_accesses 813298996 # DTB accesses +system.cpu.itb.fetch_hits 408884134 # ITB hits +system.cpu.itb.fetch_misses 679 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 392472757 # ITB accesses +system.cpu.itb.fetch_accesses 408884813 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,238 +312,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1258121036 # number of cpu cycles simulated +system.cpu.numCycles 1271858990 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 407549546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3264335293 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388838415 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 314852602 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 627934120 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 156719825 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 76880186 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6672 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 392472204 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11052250 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1243100397 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.625963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.139695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 427176335 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3374139678 # Number of instructions fetch has processed +system.cpu.fetch.Branches 402497188 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 328117961 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 650903682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 174116050 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 24391105 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7638 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 408884134 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8158289 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1250296288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.698672 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.147490 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 615166277 49.49% 49.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57172656 4.60% 54.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43000211 3.46% 57.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71551989 5.76% 63.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 128968214 10.37% 73.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45505183 3.66% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41223100 3.32% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8333259 0.67% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 232179508 18.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 599392606 47.94% 47.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 59914511 4.79% 52.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43339464 3.47% 56.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 76172685 6.09% 62.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 135820925 10.86% 73.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46245373 3.70% 76.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41570756 3.32% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7626661 0.61% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 240213307 19.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1243100397 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309063 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.594611 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 435930978 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62933874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 604150213 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9367719 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 130717613 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31718395 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12462 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3186570357 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46425 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 130717613 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 465229496 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27790939 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27122 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 583871323 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35463904 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3087907389 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 154 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15123 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 29163905 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2049179896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3572157572 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3486780085 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85377486 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1250296288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.652920 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 437590524 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 25041136 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 638845250 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1014076 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 147805302 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33122555 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12366 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3318032791 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46593 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 147805302 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 458553010 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7909851 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27396 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 618894367 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 17106362 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3208538957 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6484 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32278 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17594215 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 887362 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2130246681 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3706452753 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3620701555 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 85751197 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 664210826 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4225 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 110011827 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 740901505 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 350460770 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68439311 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8785014 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2617226795 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 84 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2156646647 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17944068 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 794119367 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 722832560 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1243100397 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.734893 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803138 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 745277611 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4240 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12056800 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 776684532 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 361655801 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 80427234 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13113632 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2720222433 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 90 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2182396478 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17917271 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 897142134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 813907304 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1250296288 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.745503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.834496 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 448302243 36.06% 36.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 195655717 15.74% 51.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 250740933 20.17% 71.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121021830 9.74% 81.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 105318972 8.47% 90.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 78084268 6.28% 96.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24856581 2.00% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17351964 1.40% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767889 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 456063276 36.48% 36.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196937863 15.75% 52.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 246215948 19.69% 71.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 118632312 9.49% 81.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96039549 7.68% 89.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 85322198 6.82% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 31637786 2.53% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19044967 1.52% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 402389 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1243100397 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1250296288 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146209 3.14% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25356136 69.42% 72.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10022815 27.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1147020 2.84% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25333961 62.75% 65.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 13891524 34.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1232880422 57.17% 57.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17089 0.00% 57.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851287 1.29% 58.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254693 0.38% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204650 0.33% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587626615 27.25% 86.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 292809135 13.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1250439249 57.30% 57.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17094 0.00% 57.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851471 1.28% 58.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 592678275 27.16% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 295948284 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2156646647 # Type of FU issued -system.cpu.iq.rate 1.714181 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36525160 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016936 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5459761542 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3323347360 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1987047608 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101377 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88072510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73609915 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2115719202 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449853 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62169429 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2182396478 # Type of FU issued +system.cpu.iq.rate 1.715911 # Inst issue rate +system.cpu.iq.fu_busy_cnt 40372505 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018499 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5521594502 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3528574475 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2004997019 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151784518 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88865161 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73949462 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2144972289 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77793942 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63261686 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 229831479 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 44309 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76170 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 139665874 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 265614506 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19945 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 77572 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 150860905 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2971 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4433 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3083 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 130717613 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13757635 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540247 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2980698105 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 730543 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 740901505 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 350460770 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 137779 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1477 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76170 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25493824 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 28812 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25522636 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2062857125 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 521078821 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 93789522 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 147805302 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7602167 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 279549 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3087695808 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 56386 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 776684532 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 361655801 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 90 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 141634 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 84137 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 77572 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25803318 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 28659 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25831977 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2081430874 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 522925034 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 100965604 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363471226 # number of nop insts executed -system.cpu.iew.exec_refs 803855281 # number of memory reference insts executed -system.cpu.iew.exec_branches 277329051 # Number of branches executed -system.cpu.iew.exec_stores 282776460 # Number of stores executed -system.cpu.iew.exec_rate 1.639633 # Inst execution rate -system.cpu.iew.wb_sent 2062712429 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2060657523 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180065693 # num instructions producing a value -system.cpu.iew.wb_consumers 1751826527 # num instructions consuming a value +system.cpu.iew.exec_nop 367473285 # number of nop insts executed +system.cpu.iew.exec_refs 813299641 # number of memory reference insts executed +system.cpu.iew.exec_branches 277669733 # Number of branches executed +system.cpu.iew.exec_stores 290374607 # Number of stores executed +system.cpu.iew.exec_rate 1.636526 # Inst execution rate +system.cpu.iew.wb_sent 2081298559 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2078946481 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1190563677 # num instructions producing a value +system.cpu.iew.wb_consumers 1779120207 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.637885 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673620 # average fanout of values written-back +system.cpu.iew.wb_rate 1.634573 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.669187 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 954754652 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1061256381 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25488461 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1112382784 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.806022 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513006 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25797472 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1102490986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.822226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.529076 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 494456583 44.45% 44.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227533438 20.45% 64.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120160218 10.80% 75.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 59129443 5.32% 81.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 49651229 4.46% 85.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24161906 2.17% 87.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18831378 1.69% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16326025 1.47% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102132564 9.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 487378417 44.21% 44.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227745323 20.66% 64.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 117618714 10.67% 75.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58023945 5.26% 80.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49786654 4.52% 85.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22711490 2.06% 87.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18023785 1.63% 89.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18535022 1.68% 90.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102667636 9.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1112382784 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1102490986 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -588,228 +590,228 @@ system.cpu.commit.op_class_0::MemWrite 210794896 10.49% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2008987604 # Class of committed instruction -system.cpu.commit.bw_lim_events 102132564 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102667636 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3968356066 # The number of ROB reads -system.cpu.rob.rob_writes 6058204314 # The number of ROB writes -system.cpu.timesIdled 347595 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15020639 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4064430925 # The number of ROB reads +system.cpu.rob.rob_writes 6288295371 # The number of ROB writes +system.cpu.timesIdled 345316 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21562702 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.690121 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.690121 # CPI: Total CPI of All Threads -system.cpu.ipc 1.449021 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.449021 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2624396322 # number of integer regfile reads -system.cpu.int_regfile_writes 1493942666 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811215 # number of floating regfile reads -system.cpu.fp_regfile_writes 52660991 # number of floating regfile writes +system.cpu.cpi 0.697657 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.697657 # CPI: Total CPI of All Threads +system.cpu.ipc 1.433369 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.433369 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2650222632 # number of integer regfile reads +system.cpu.int_regfile_writes 1504597172 # number of integer regfile writes +system.cpu.fp_regfile_reads 79149378 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661639 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 166637932 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470284 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71642 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20095 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159727 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3179822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104182336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104825344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104825344 # Total data (bytes) +system.cpu.toL2Bus.throughput 164848262 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71643 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 71643 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159913 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3180016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104188608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 104831872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104831872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914919500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 914980500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15573249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 15576999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2360853250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2360120750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8332 # number of replacements -system.cpu.icache.tags.tagsinuse 1660.987430 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 392459292 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10047 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39062.336220 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 8337 # number of replacements +system.cpu.icache.tags.tagsinuse 1659.365799 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 408871331 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 40679.666799 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1660.987430 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.811029 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.811029 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1715 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1659.365799 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.810237 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.810237 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1714 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1559 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.837402 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 784954455 # Number of tag accesses -system.cpu.icache.tags.data_accesses 784954455 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 392459292 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 392459292 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 392459292 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 392459292 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 392459292 # number of overall hits -system.cpu.icache.overall_hits::total 392459292 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12912 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12912 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12912 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12912 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12912 # number of overall misses -system.cpu.icache.overall_misses::total 12912 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 385616248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 385616248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 385616248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 385616248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 385616248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 385616248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 392472204 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 392472204 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 392472204 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 392472204 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 392472204 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 392472204 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29864.951053 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29864.951053 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29864.951053 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29864.951053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29864.951053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29864.951053 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 750 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 129 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.875000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.836914 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 817778319 # Number of tag accesses +system.cpu.icache.tags.data_accesses 817778319 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 408871331 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 408871331 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 408871331 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 408871331 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 408871331 # number of overall hits +system.cpu.icache.overall_hits::total 408871331 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12803 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12803 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12803 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12803 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12803 # number of overall misses +system.cpu.icache.overall_misses::total 12803 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 381292998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 381292998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 381292998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 381292998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 381292998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 381292998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 408884134 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 408884134 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 408884134 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 408884134 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 408884134 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 408884134 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000031 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000031 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000031 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000031 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000031 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000031 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29781.535421 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29781.535421 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29781.535421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29781.535421 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72009.322954 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72105.472158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72104.914404 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -820,181 +822,171 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2767 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406517 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409284 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2762 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406515 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409277 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2767 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 473371 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476138 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2767 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473371 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476138 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163545500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24343035750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24506581250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4426416000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4426416000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163545500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28769451750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28932997250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163545500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28769451750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28932997250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.275378 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278391 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278371 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.275378 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308794 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.275378 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308794 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59105.710155 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59881.962501 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.714580 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66210.189368 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66210.189368 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59105.710155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60775.695490 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60765.990637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59105.710155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60775.695490 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60765.990637 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473369 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476131 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2762 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473369 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476131 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164041750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23797651250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23961693000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4425694500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4425694500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164041750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28223345750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28387387500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164041750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28223345750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28387387500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278373 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278349 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933155 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933155 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308994 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308771 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308994 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308771 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59392.378711 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58540.647332 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58546.395229 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66199.397194 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66199.397194 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59392.378711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59622.294130 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59620.960408 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59392.378711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59622.294130 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59620.960408 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1527782 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.589786 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 666108987 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1531878 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 434.831616 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 407842250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.589786 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999656 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999656 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1527870 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.609891 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 666862520 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531966 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 435.298512 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 407274250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.609891 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999661 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999661 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2366 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2348 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 409 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1339722798 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1339722798 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 456374888 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 456374888 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209734080 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209734080 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 19 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 19 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 666108968 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 666108968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 666108968 # number of overall hits -system.cpu.dcache.overall_hits::total 666108968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925656 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925656 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1060816 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1060816 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2986472 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2986472 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2986472 # number of overall misses -system.cpu.dcache.overall_misses::total 2986472 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77376197750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77376197750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 46509308117 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 46509308117 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 74750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 74750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 123885505867 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 123885505867 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 123885505867 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 123885505867 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 458300544 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 458300544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1341234178 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1341234178 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 457128371 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 457128371 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209734126 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209734126 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 666862497 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666862497 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666862497 # number of overall hits +system.cpu.dcache.overall_hits::total 666862497 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1927816 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1927816 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1060770 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1060770 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2988586 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2988586 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2988586 # number of overall misses +system.cpu.dcache.overall_misses::total 2988586 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76893359750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76893359750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 46482150765 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 46482150765 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 123375510515 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 123375510515 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 123375510515 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 123375510515 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 459056187 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 459056187 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 669095440 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 669095440 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 669095440 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 669095440 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 23 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 23 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669851083 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669851083 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669851083 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669851083 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004200 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004200 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005032 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005032 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.050000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.050000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004463 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004463 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40181.734302 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40181.734302 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43842.954968 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43842.954968 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41482.225806 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41482.225806 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41482.225806 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41482.225806 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18571 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 133 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 384 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.004462 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004462 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004462 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004462 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39886.254575 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39886.254575 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43819.254659 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43819.254659 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41282.235316 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41282.235316 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41282.235316 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41282.235316 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19699 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 140 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 433 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.361979 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 133 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.494226 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 140 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks -system.cpu.dcache.writebacks::total 95971 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465420 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465420 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 989174 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 989174 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1454594 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1454594 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1454594 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1454594 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460236 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460236 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531878 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531878 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531878 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531878 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41467915750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41467915750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5351919500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5351919500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46819835250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46819835250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46819835250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46819835250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003186 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003186 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 95981 # number of writebacks +system.cpu.dcache.writebacks::total 95981 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467493 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467493 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 989127 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 989127 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1456620 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1456620 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1456620 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1456620 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460323 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460323 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71643 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71643 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531966 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531966 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531966 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531966 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40901282750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40901282750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5350796500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5350796500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46252079250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46252079250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46252079250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46252079250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003181 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002289 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002289 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28398.091644 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28398.091644 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74703.658468 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74703.658468 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30563.684086 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30563.684086 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30563.684086 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30563.684086 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002287 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002287 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002287 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002287 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28008.380851 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28008.380851 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74686.940804 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74686.940804 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30191.322294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30191.322294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30191.322294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30191.322294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 1aaeea9d1..48782c31e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,7 +699,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 542867b6f..8802e13a7 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:31:04 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:43:02 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x4c3a340 + 0: system.cpu.isa: ISA system set to: 0 0x5c9e4b0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -1386,4 +1386,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 629535413500 because target called exit() +Exiting @ tick 634728078000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e51d34500..fbd52f02a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.628792 # Number of seconds simulated -sim_ticks 628791732500 # Number of ticks simulated -final_tick 628791732500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.634728 # Number of seconds simulated +sim_ticks 634728078000 # Number of ticks simulated +final_tick 634728078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86286 # Simulator instruction rate (inst/s) -host_op_rate 117510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39191918 # Simulator tick rate (ticks/s) -host_mem_usage 321468 # Number of bytes of host memory used -host_seconds 16043.91 # Real time elapsed on the host +host_inst_rate 97161 # Simulator instruction rate (inst/s) +host_op_rate 132320 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44547849 # Simulator tick rate (ticks/s) +host_mem_usage 267228 # Number of bytes of host memory used +host_seconds 14248.23 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242560 # Number of bytes read from this memory -system.physmem.bytes_read::total 30397504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 156032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30243456 # Number of bytes read from this memory +system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156032 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472540 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472554 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 246415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48096307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48342722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 246415 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246415 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6727620 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6727620 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6727620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 246415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48096307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55070342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474962 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 245825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47647894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47893719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 245825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 245825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6664700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6664700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6664700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 245825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47647894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54558418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474992 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474962 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 474992 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30374848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30397568 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30375808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23680 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30399488 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 370 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4292 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29853 # Per bank write bursts -system.physmem.perBankRdBursts::1 29663 # Per bank write bursts -system.physmem.perBankRdBursts::2 29734 # Per bank write bursts -system.physmem.perBankRdBursts::3 29691 # Per bank write bursts -system.physmem.perBankRdBursts::4 29781 # Per bank write bursts -system.physmem.perBankRdBursts::5 29812 # Per bank write bursts -system.physmem.perBankRdBursts::6 29626 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4530 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29868 # Per bank write bursts +system.physmem.perBankRdBursts::1 29664 # Per bank write bursts +system.physmem.perBankRdBursts::2 29737 # Per bank write bursts +system.physmem.perBankRdBursts::3 29712 # Per bank write bursts +system.physmem.perBankRdBursts::4 29799 # Per bank write bursts +system.physmem.perBankRdBursts::5 29810 # Per bank write bursts +system.physmem.perBankRdBursts::6 29625 # Per bank write bursts system.physmem.perBankRdBursts::7 29426 # Per bank write bursts -system.physmem.perBankRdBursts::8 29463 # Per bank write bursts -system.physmem.perBankRdBursts::9 29476 # Per bank write bursts -system.physmem.perBankRdBursts::10 29540 # Per bank write bursts -system.physmem.perBankRdBursts::11 29638 # Per bank write bursts -system.physmem.perBankRdBursts::12 29686 # Per bank write bursts -system.physmem.perBankRdBursts::13 29802 # Per bank write bursts -system.physmem.perBankRdBursts::14 29621 # Per bank write bursts -system.physmem.perBankRdBursts::15 29795 # Per bank write bursts -system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankRdBursts::8 29475 # Per bank write bursts +system.physmem.perBankRdBursts::9 29463 # Per bank write bursts +system.physmem.perBankRdBursts::10 29528 # Per bank write bursts +system.physmem.perBankRdBursts::11 29636 # Per bank write bursts +system.physmem.perBankRdBursts::12 29682 # Per bank write bursts +system.physmem.perBankRdBursts::13 29788 # Per bank write bursts +system.physmem.perBankRdBursts::14 29619 # Per bank write bursts +system.physmem.perBankRdBursts::15 29790 # Per bank write bursts +system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::3 4147 # Per bank write bursts system.physmem.perBankWrBursts::4 4225 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4090 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4139 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 628791712500 # Total gap between requests +system.physmem.totGap 634728009000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474962 # Read request sizes (log2) +system.physmem.readPktSize::6 474992 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66616 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -146,22 +146,22 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4014 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,93 +193,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 194074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.290755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.832062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.398992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 73771 38.01% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 88634 45.67% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20233 10.43% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 463 0.24% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 411 0.21% 94.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 515 0.27% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 585 0.30% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 564 0.29% 95.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8898 4.58% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 194074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 192766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 179.514147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 129.738688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 208.062403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 72454 37.59% 37.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 88147 45.73% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 20712 10.74% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 450 0.23% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 454 0.24% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 512 0.27% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 512 0.27% 95.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 605 0.31% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8920 4.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 192766 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.655603 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.114528 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 505.912792 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.628151 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.096624 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.030557 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.491390 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.469672 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863565 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.491141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.469437 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.863273 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 75.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 975 24.33% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2 0.05% 75.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 974 24.31% 99.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 5771153000 # Total ticks spent queuing -system.physmem.totMemAccLat 14670034250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2373035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12159.86 # Average queueing delay per DRAM burst +system.physmem.totQLat 4985394000 # Total ticks spent queuing +system.physmem.totMemAccLat 13884556500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2373110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10503.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30909.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29253.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 47.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 47.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 18.42 # Average write queue length when enqueuing -system.physmem.readRowHits 296657 # Number of row buffer hits during reads -system.physmem.writeRowHits 49944 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.56 # Row buffer hit rate for writes -system.physmem.avgGap 1162147.84 # Average gap between requests -system.physmem.pageHitRate 64.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 162139876750 # Time in different power states -system.physmem.memoryStateTime::REF 20996560000 # Time in different power states +system.physmem.avgWrQLen 19.25 # Average write queue length when enqueuing +system.physmem.readRowHits 298015 # Number of row buffer hits during reads +system.physmem.writeRowHits 49917 # Number of row buffer hits during writes +system.physmem.readRowHitRate 62.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes +system.physmem.avgGap 1173054.41 # Average gap between requests +system.physmem.pageHitRate 64.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 171675355500 # Time in different power states +system.physmem.memoryStateTime::REF 21194940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 445650242000 # Time in different power states +system.physmem.memoryStateTime::ACT 441857292000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 55070241 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408884 # Transaction distribution -system.membus.trans_dist::ReadResp 408882 # Transaction distribution +system.membus.throughput 54558418 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408916 # Transaction distribution +system.membus.trans_dist::ReadResp 408916 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4292 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4292 # Transaction distribution -system.membus.trans_dist::ReadExReq 66078 # Transaction distribution -system.membus.trans_dist::ReadExResp 66078 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024604 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024604 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627712 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34627712 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34627712 # Total data (bytes) +system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4530 # Transaction distribution +system.membus.trans_dist::ReadExReq 66076 # Transaction distribution +system.membus.trans_dist::ReadExResp 66076 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1025142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1025142 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34629760 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34629760 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1214449500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1216030000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4441072458 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4441818720 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 439434227 # Number of BP lookups -system.cpu.branchPred.condPredicted 352242826 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30627071 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 250632586 # Number of BTB lookups -system.cpu.branchPred.BTBHits 230940186 # Number of BTB hits +system.cpu.branchPred.lookups 478607550 # Number of BP lookups +system.cpu.branchPred.condPredicted 378292816 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30666231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 334166811 # Number of BTB lookups +system.cpu.branchPred.BTBHits 254063804 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.142921 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52229993 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2805540 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 76.029036 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 60780885 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806336 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -365,239 +365,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1257583466 # number of cpu cycles simulated +system.cpu.numCycles 1269456157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 355252330 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2281557009 # Number of instructions fetch has processed -system.cpu.fetch.Branches 439434227 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 283170179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601713503 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 156847289 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133155767 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 595 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11076 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 125 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 335955320 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11758504 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1216301526 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.576674 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.174492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 382172768 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2398528075 # Number of instructions fetch has processed +system.cpu.fetch.Branches 478607550 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 314844689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 646500630 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 176126555 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 55590458 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12318 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 358033766 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6993732 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1229682095 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.711139 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.182068 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614632846 50.53% 50.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42470987 3.49% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 96126752 7.90% 61.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 57281313 4.71% 66.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 72527941 5.96% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45003441 3.70% 76.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31089370 2.56% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31572340 2.60% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 225596536 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 583226842 47.43% 47.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47324489 3.85% 51.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105202734 8.56% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 59348034 4.83% 64.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82117278 6.68% 71.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 49221552 4.00% 75.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 36109976 2.94% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30221135 2.46% 80.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 236910055 19.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1216301526 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.349427 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.814239 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405937331 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105620938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561845304 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16741500 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 126156453 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44653834 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11972 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3026383079 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27573 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 126156453 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441649817 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37679339 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 449718 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540872152 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 69494047 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2944559238 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4802711 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54195204 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 788 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2928884357 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14250328437 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12163279231 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 83987601 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1229682095 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.377018 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.889414 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 407354221 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 47938688 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 625726372 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3270610 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 145392204 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 52977001 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 97525 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3244658117 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31782 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 145392204 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 431843071 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 21602754 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 464275 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 603219561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27160230 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3179170609 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6664902 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 18155043 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 78588 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2271 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3142601872 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 15333387016 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13133730346 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 83988681 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 935744267 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20476 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 177752072 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 970380112 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 488270478 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36212412 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40741930 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792865970 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2433397099 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13404605 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 895018158 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2348989049 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6466 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1216301526 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.000653 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.872636 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1149461782 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 21762 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19092 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48856011 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1039047790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 516447707 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 54890431 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 57377876 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2969017113 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28780 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2494321710 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 29655363 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1083496611 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2947742555 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 7396 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1229682095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.028428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.901891 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 380324245 31.27% 31.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183454055 15.08% 46.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204117167 16.78% 63.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169768830 13.96% 77.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132683622 10.91% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92575300 7.61% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37909888 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12415448 1.02% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3052971 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 391713450 31.85% 31.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 177167826 14.41% 46.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 194208889 15.79% 62.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 164750014 13.40% 75.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 152000166 12.36% 87.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 91333270 7.43% 95.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42323460 3.44% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 13601870 1.11% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2583150 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1216301526 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1229682095 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 714605 0.81% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24383 0.03% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55145870 62.89% 63.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31799244 36.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1141867 1.24% 1.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24392 0.03% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 58632065 63.67% 64.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 32290785 35.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1104322039 45.38% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223967 0.46% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502004 0.23% 46.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23392771 0.96% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838298218 34.45% 81.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442406331 18.18% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1135683319 45.53% 45.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11247917 0.45% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502263 0.22% 46.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23390431 0.94% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 860090981 34.48% 81.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 450155032 18.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2433397099 # Type of FU issued -system.cpu.iq.rate 1.934979 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87684102 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036034 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6061689588 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3605336566 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2248845458 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122494843 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82642602 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56425705 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2457771318 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63309883 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84349734 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2494321710 # Type of FU issued +system.cpu.iq.rate 1.964874 # Inst issue rate +system.cpu.iq.fu_busy_cnt 92089109 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036919 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6216205899 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3969996640 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2305202146 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 123864088 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82618605 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56425277 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2521728263 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 64682556 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 98529432 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 338992931 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10163 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1428185 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 211275181 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 407660609 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5276533 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 2500816 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 239452410 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 448 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 420 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 126156453 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15953141 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1561672 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792906296 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1415032 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 970380112 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 488270478 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 17864 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555530 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1428185 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32514856 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1483129 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33997985 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2358061254 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792590559 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75335845 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 145392204 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15914893 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1611898 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2969058590 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2618613 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1039047790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 516447707 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18794 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1555522 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56228 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 2500816 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 33181152 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1519240 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 34700392 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2424200983 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 818208051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 70120727 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12476 # number of nop insts executed -system.cpu.iew.exec_refs 1216220468 # number of memory reference insts executed -system.cpu.iew.exec_branches 319843836 # Number of branches executed -system.cpu.iew.exec_stores 423629909 # Number of stores executed -system.cpu.iew.exec_rate 1.875073 # Inst execution rate -system.cpu.iew.wb_sent 2330961284 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2305271163 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347649196 # num instructions producing a value -system.cpu.iew.wb_consumers 2523801543 # num instructions consuming a value +system.cpu.iew.exec_nop 12697 # number of nop insts executed +system.cpu.iew.exec_refs 1248100004 # number of memory reference insts executed +system.cpu.iew.exec_branches 329019811 # Number of branches executed +system.cpu.iew.exec_stores 429891953 # Number of stores executed +system.cpu.iew.exec_rate 1.909637 # Inst execution rate +system.cpu.iew.wb_sent 2388820620 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2361627423 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1389701712 # num instructions producing a value +system.cpu.iew.wb_consumers 2644997142 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833096 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533976 # average fanout of values written-back +system.cpu.iew.wb_rate 1.860346 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.525408 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 907570051 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1083730173 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30615394 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1090145073 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.729436 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.397108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30653233 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1084289891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.738775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.404247 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449857024 41.27% 41.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288588820 26.47% 67.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95106380 8.72% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70218402 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46473981 4.26% 87.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22183134 2.03% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15845043 1.45% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10980592 1.01% 91.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90891697 8.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 445713482 41.11% 41.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 287271007 26.49% 67.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 94862412 8.75% 76.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 69719327 6.43% 82.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46233776 4.26% 87.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22314720 2.06% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15854088 1.46% 90.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11019318 1.02% 91.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 91301761 8.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1090145073 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1084289891 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -643,239 +644,239 @@ system.cpu.commit.op_class_0::MemWrite 276995297 14.69% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction -system.cpu.commit.bw_lim_events 90891697 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 91301761 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3792141440 # The number of ROB reads -system.cpu.rob.rob_writes 5711980108 # The number of ROB writes -system.cpu.timesIdled 352856 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41281940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3962036316 # The number of ROB reads +system.cpu.rob.rob_writes 6083536675 # The number of ROB writes +system.cpu.timesIdled 355726 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 39774062 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.908415 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.908415 # CPI: Total CPI of All Threads -system.cpu.ipc 1.100818 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.100818 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11756762903 # number of integer regfile reads -system.cpu.int_regfile_writes 2218718479 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads -system.cpu.fp_regfile_writes 49537143 # number of floating regfile writes -system.cpu.misc_regfile_reads 1677857394 # number of misc regfile reads +system.cpu.cpi 0.916992 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.916992 # CPI: Total CPI of All Threads +system.cpu.ipc 1.090523 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.090523 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12060176633 # number of integer regfile reads +system.cpu.int_regfile_writes 2272688052 # number of integer regfile writes +system.cpu.fp_regfile_reads 68797676 # number of floating regfile reads +system.cpu.fp_regfile_writes 49536165 # number of floating regfile writes +system.cpu.misc_regfile_reads 1701422665 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 169149196 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1493034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1493032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52723 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3231718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1549696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104535104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106084800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106084800 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 274816 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929401499 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 167841675 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1495790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1495789 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96290 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72512 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72512 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179527 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3237427 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1707776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106243776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106243776 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 290048 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 930852999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 43182746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 47253245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2371256268 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2371526007 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 22529 # number of replacements -system.cpu.icache.tags.tagsinuse 1644.627190 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 335917634 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24213 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13873.441292 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 24993 # number of replacements +system.cpu.icache.tags.tagsinuse 1647.783456 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 357995053 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 26684 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13416.094026 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1644.627190 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.803041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.803041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1684 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.783456 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804582 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804582 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1691 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1552 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 671939144 # Number of tag accesses -system.cpu.icache.tags.data_accesses 671939144 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 335924107 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 335924107 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 335924107 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 335924107 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 335924107 # number of overall hits -system.cpu.icache.overall_hits::total 335924107 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 31211 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 31211 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 31211 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 31211 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 31211 # number of overall misses -system.cpu.icache.overall_misses::total 31211 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 530208992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 530208992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 530208992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 530208992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 530208992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 530208992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 335955318 # 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Cycle average of tags in use +system.cpu.dcache.tags.total_refs 981387634 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1537085 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 638.473236 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 399634250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.399228 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999609 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999609 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 978 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 980 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2382 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 428 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1947074947 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1947074947 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 693859178 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693859178 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276090749 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276090749 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10001 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10001 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1969885597 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1969885597 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 705264252 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 705264252 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276089331 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276089331 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969949927 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969949927 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969949927 # number of overall hits -system.cpu.dcache.overall_hits::total 969949927 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1954107 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1954107 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 844929 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 844929 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 981353583 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 981353583 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 981353583 # number of overall hits +system.cpu.dcache.overall_hits::total 981353583 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1954339 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1954339 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 846347 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 846347 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2799036 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2799036 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2799036 # number of overall misses -system.cpu.dcache.overall_misses::total 2799036 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79576585056 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79576585056 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58758638704 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58758638704 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 210750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 210750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 138335223760 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 138335223760 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 138335223760 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 138335223760 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695813285 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695813285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2800686 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2800686 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2800686 # number of overall misses +system.cpu.dcache.overall_misses::total 2800686 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78948283141 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78948283141 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58782925343 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58782925343 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 464000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 464000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137731208484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137731208484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137731208484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137731208484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 707218591 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 707218591 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10004 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10004 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972748963 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972748963 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972748963 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972748963 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003051 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003051 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 984154269 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 984154269 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 984154269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 984154269 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002763 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002763 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003056 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003056 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002877 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002877 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002877 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002877 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40722.736808 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40722.736808 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69542.693770 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69542.693770 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49422.452502 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49422.452502 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49422.452502 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49422.452502 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2414 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 988 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 54 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.703704 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.739130 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002846 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002846 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002846 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002846 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49177.668787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49177.668787 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2986 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 861 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 79 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.766667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.898734 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96318 # number of writebacks -system.cpu.dcache.writebacks::total 96318 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489582 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489582 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 768115 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 768115 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96290 # number of writebacks +system.cpu.dcache.writebacks::total 96290 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489763 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489763 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769304 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769304 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1257697 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1257697 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1257697 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1257697 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464525 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464525 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541339 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541339 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541339 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541339 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42200288024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42200288024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993959708 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993959708 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47194247732 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47194247732 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47194247732 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47194247732 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28815.000102 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28815.000102 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65013.665582 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65013.665582 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30618.992793 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30618.992793 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30618.992793 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30618.992793 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1259067 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1259067 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1259067 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1259067 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464576 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464576 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77043 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 77043 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541619 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541619 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541619 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41415183522 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41415183522 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4998292971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4998292971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46413476493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46413476493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46413476493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46413476493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002071 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002071 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001566 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001566 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28277.934038 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28277.934038 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64876.665901 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64876.665901 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index f15dfa96f..2fdef1249 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 86191115c..6187ab612 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 18:24:06 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 12:22:04 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24876941500 because target called exit() +Exiting @ tick 24220559500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 118121be3..b325b70f4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024636 # Number of seconds simulated -sim_ticks 24636200500 # Number of ticks simulated -final_tick 24636200500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024221 # Number of seconds simulated +sim_ticks 24220559500 # Number of ticks simulated +final_tick 24220559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166481 # Simulator instruction rate (inst/s) -host_op_rate 166481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51531279 # Simulator tick rate (ticks/s) -host_mem_usage 277620 # Number of bytes of host memory used -host_seconds 478.08 # Real time elapsed on the host +host_inst_rate 197323 # Simulator instruction rate (inst/s) +host_op_rate 197323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60047490 # Simulator tick rate (ticks/s) +host_mem_usage 230944 # Number of bytes of host memory used +host_seconds 403.36 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 491136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153600 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 491136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 491136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296704 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7674 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158650 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166324 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114011 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114011 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19935542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 412141474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 432077016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19935542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19935542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 296178138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 296178138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 296178138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19935542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 412141474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 728255154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166324 # Number of read requests accepted -system.physmem.writeReqs 114011 # Number of write requests accepted -system.physmem.readBursts 166324 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114011 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10644224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7295040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10644736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7296704 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 490880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153984 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158656 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166326 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20267079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 419229952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 439497031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20267079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20267079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 301273965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 301273965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 301273965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20267079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 419229952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 740770997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166326 # Number of read requests accepted +system.physmem.writeReqs 114016 # Number of write requests accepted +system.physmem.readBursts 166326 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114016 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10644288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7295168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10644864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10435 # Per bank write bursts -system.physmem.perBankRdBursts::1 10464 # Per bank write bursts -system.physmem.perBankRdBursts::2 10314 # Per bank write bursts +system.physmem.perBankRdBursts::0 10433 # Per bank write bursts +system.physmem.perBankRdBursts::1 10462 # Per bank write bursts +system.physmem.perBankRdBursts::2 10311 # Per bank write bursts system.physmem.perBankRdBursts::3 10058 # Per bank write bursts -system.physmem.perBankRdBursts::4 10432 # Per bank write bursts -system.physmem.perBankRdBursts::5 10406 # Per bank write bursts -system.physmem.perBankRdBursts::6 9849 # Per bank write bursts -system.physmem.perBankRdBursts::7 10311 # Per bank write bursts -system.physmem.perBankRdBursts::8 10614 # Per bank write bursts -system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10549 # Per bank write bursts +system.physmem.perBankRdBursts::4 10424 # Per bank write bursts +system.physmem.perBankRdBursts::5 10410 # Per bank write bursts +system.physmem.perBankRdBursts::6 9846 # Per bank write bursts +system.physmem.perBankRdBursts::7 10316 # Per bank write bursts +system.physmem.perBankRdBursts::8 10611 # Per bank write bursts +system.physmem.perBankRdBursts::9 10645 # Per bank write bursts +system.physmem.perBankRdBursts::10 10555 # Per bank write bursts system.physmem.perBankRdBursts::11 10230 # Per bank write bursts -system.physmem.perBankRdBursts::12 10275 # Per bank write bursts -system.physmem.perBankRdBursts::13 10619 # Per bank write bursts -system.physmem.perBankRdBursts::14 10489 # Per bank write bursts -system.physmem.perBankRdBursts::15 10628 # Per bank write bursts +system.physmem.perBankRdBursts::12 10281 # Per bank write bursts +system.physmem.perBankRdBursts::13 10621 # Per bank write bursts +system.physmem.perBankRdBursts::14 10488 # Per bank write bursts +system.physmem.perBankRdBursts::15 10626 # Per bank write bursts system.physmem.perBankWrBursts::0 7082 # Per bank write bursts -system.physmem.perBankWrBursts::1 7254 # Per bank write bursts +system.physmem.perBankWrBursts::1 7257 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts system.physmem.perBankWrBursts::5 7170 # Per bank write bursts -system.physmem.perBankWrBursts::6 6770 # Per bank write bursts -system.physmem.perBankWrBursts::7 7085 # Per bank write bursts -system.physmem.perBankWrBursts::8 7222 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 7086 # Per bank write bursts +system.physmem.perBankWrBursts::8 7220 # Per bank write bursts system.physmem.perBankWrBursts::9 6941 # Per bank write bursts system.physmem.perBankWrBursts::10 7083 # Per bank write bursts -system.physmem.perBankWrBursts::11 6990 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts -system.physmem.perBankWrBursts::13 7286 # Per bank write bursts -system.physmem.perBankWrBursts::14 7286 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts +system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::13 7288 # Per bank write bursts +system.physmem.perBankWrBursts::14 7285 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24636167000 # Total gap between requests +system.physmem.totGap 24220526000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166324 # Read request sizes (log2) +system.physmem.readPktSize::6 166326 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114011 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 69812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9786 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114016 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 68881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 45477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14195 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -193,114 +193,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52591 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.105360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 200.170415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.733138 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18652 35.47% 35.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10746 20.43% 55.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5782 10.99% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3058 5.81% 72.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2757 5.24% 77.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1645 3.13% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1894 3.60% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1108 2.11% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6949 13.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52591 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6971 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.856692 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.122530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6970 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.720229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.667520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.624937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18531 35.30% 35.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10783 20.54% 55.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5620 10.71% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3233 6.16% 72.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2663 5.07% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1771 3.37% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1746 3.33% 84.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1279 2.44% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6867 13.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52493 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6963 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.883814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.440327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6961 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6971 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6971 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.351313 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.323948 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.004197 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6065 87.00% 87.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.43% 87.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 507 7.27% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 200 2.87% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 92 1.32% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 44 0.63% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 23 0.33% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 4 0.06% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6971 # Writes before turning the bus around for reads -system.physmem.totQLat 4932812500 # Total ticks spent queuing -system.physmem.totMemAccLat 8051237500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831580000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29659.28 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6963 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6963 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.370386 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.340039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.063738 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6043 86.79% 86.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 33 0.47% 87.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 485 6.97% 94.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 209 3.00% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 93 1.34% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 61 0.88% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.30% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 6 0.09% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.11% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6963 # Writes before turning the bus around for reads +system.physmem.totQLat 4923415500 # Total ticks spent queuing +system.physmem.totMemAccLat 8041859250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831585000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29602.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48409.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 432.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 296.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 432.08 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 296.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48352.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 439.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 301.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 439.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 301.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.69 # Data bus utilization in percentage -system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 145935 # Number of row buffer hits during reads -system.physmem.writeRowHits 81773 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.72 # Row buffer hit rate for writes -system.physmem.avgGap 87881.17 # Average gap between requests -system.physmem.pageHitRate 81.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 10235619000 # Time in different power states -system.physmem.memoryStateTime::REF 822640000 # Time in different power states +system.physmem.busUtil 5.79 # Data bus utilization in percentage +system.physmem.busUtilRead 3.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.35 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 145967 # Number of row buffer hits during reads +system.physmem.writeRowHits 81830 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.77 # Row buffer hit rate for writes +system.physmem.avgGap 86396.35 # Average gap between requests +system.physmem.pageHitRate 81.26 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 10036891500 # Time in different power states +system.physmem.memoryStateTime::REF 808600000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13577715750 # Time in different power states +system.physmem.memoryStateTime::ACT 13370021250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 728255154 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35531 # Transaction distribution -system.membus.trans_dist::ReadResp 35531 # Transaction distribution -system.membus.trans_dist::Writeback 114011 # Transaction distribution -system.membus.trans_dist::ReadExReq 130793 # Transaction distribution -system.membus.trans_dist::ReadExResp 130793 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446659 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446659 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17941440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17941440 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17941440 # Total data (bytes) +system.membus.throughput 740770997 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35544 # Transaction distribution +system.membus.trans_dist::ReadResp 35544 # Transaction distribution +system.membus.trans_dist::Writeback 114016 # Transaction distribution +system.membus.trans_dist::ReadExReq 130782 # Transaction distribution +system.membus.trans_dist::ReadExResp 130782 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446668 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17941888 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17941888 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17941888 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1239417000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1541901750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1251548500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1536730000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16532258 # Number of BP lookups -system.cpu.branchPred.condPredicted 10678400 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 414272 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11254854 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7335293 # Number of BTB hits +system.cpu.branchPred.lookups 16751824 # Number of BP lookups +system.cpu.branchPred.condPredicted 10815024 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 427504 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12114862 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7449714 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.174484 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1985053 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41515 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.492355 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 2011177 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42536 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22389116 # DTB read hits -system.cpu.dtb.read_misses 220601 # DTB read misses -system.cpu.dtb.read_acv 47 # DTB read access violations -system.cpu.dtb.read_accesses 22609717 # DTB read accesses -system.cpu.dtb.write_hits 15701492 # DTB write hits -system.cpu.dtb.write_misses 40930 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15742422 # DTB write accesses -system.cpu.dtb.data_hits 38090608 # DTB hits -system.cpu.dtb.data_misses 261531 # DTB misses -system.cpu.dtb.data_acv 51 # DTB access violations -system.cpu.dtb.data_accesses 38352139 # DTB accesses -system.cpu.itb.fetch_hits 13899561 # ITB hits -system.cpu.itb.fetch_misses 35223 # ITB misses +system.cpu.dtb.read_hits 22508658 # DTB read hits +system.cpu.dtb.read_misses 223827 # DTB read misses +system.cpu.dtb.read_acv 56 # DTB read access violations +system.cpu.dtb.read_accesses 22732485 # DTB read accesses +system.cpu.dtb.write_hits 15810202 # DTB write hits +system.cpu.dtb.write_misses 43571 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 15853773 # DTB write accesses +system.cpu.dtb.data_hits 38318860 # DTB hits +system.cpu.dtb.data_misses 267398 # DTB misses +system.cpu.dtb.data_acv 59 # DTB access violations +system.cpu.dtb.data_accesses 38586258 # DTB accesses +system.cpu.itb.fetch_hits 14110575 # ITB hits +system.cpu.itb.fetch_misses 33841 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13934784 # ITB accesses +system.cpu.itb.fetch_accesses 14144416 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -314,238 +316,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49272404 # number of cpu cycles simulated +system.cpu.numCycles 48441123 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15777525 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105311558 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16532258 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9320346 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19533612 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1991452 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7584858 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7736 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 311235 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 81 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13899561 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44661692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.357984 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15991541 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106726758 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16751824 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9460891 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19798045 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2119165 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5548537 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 330003 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14110575 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 235048 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43228418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.468903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.149982 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25128080 56.26% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1526401 3.42% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1371052 3.07% 62.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1506745 3.37% 66.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4140649 9.27% 75.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1845293 4.13% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 672736 1.51% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1068547 2.39% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7402189 16.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23430373 54.20% 54.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1549768 3.59% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1389630 3.21% 61.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1530327 3.54% 64.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4182492 9.68% 74.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1877886 4.34% 78.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 686601 1.59% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1082983 2.51% 82.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7498358 17.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44661692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.335528 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.137333 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16866897 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7111825 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18558707 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 782025 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1342238 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3745907 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 106790 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103587056 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304363 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1342238 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17337019 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4756497 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85160 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18837400 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2303378 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102332178 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 523 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2649 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2191032 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61618182 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123319781 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123000606 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319174 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43228418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.345818 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.203226 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16783976 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5410543 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19277752 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 307681 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1448466 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3794458 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108182 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104881075 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 317541 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1448466 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17188880 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4589733 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 87878 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19270658 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 642803 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103574244 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2041 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 123118 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 133246 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 383447 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 62411257 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124921798 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124593189 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 328608 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9071301 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5539 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5537 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4823048 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23221608 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16268601 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1205921 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 453901 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90714313 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5368 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88410610 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95528 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10671258 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4645313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 785 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44661692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.979562 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.108908 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9864376 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5611 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5609 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1424158 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23418596 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16455537 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1234609 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 506012 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91610357 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5443 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89041530 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 152798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11549535 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5161371 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 860 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43228418 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.059792 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.166400 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16438268 36.81% 36.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6883864 15.41% 52.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5570491 12.47% 64.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4772833 10.69% 75.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4726674 10.58% 85.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2623655 5.87% 91.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1921880 4.30% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1281202 2.87% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442825 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16020950 37.06% 37.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5899567 13.65% 50.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5167698 11.95% 62.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4624013 10.70% 73.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4881657 11.29% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2705075 6.26% 90.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2091187 4.84% 95.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1370765 3.17% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 467506 1.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44661692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43228418 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 125753 6.74% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 787939 42.23% 48.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 952099 51.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 122844 6.34% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 826331 42.62% 48.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 989497 51.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49354396 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43843 0.05% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121164 0.14% 56.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 56.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120950 0.14% 56.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 59 0.00% 56.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22839676 25.83% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15891479 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49689736 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43878 0.05% 55.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121254 0.14% 55.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121079 0.14% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38922 0.04% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22993595 25.82% 81.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16032920 18.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88410610 # Type of FU issued -system.cpu.iq.rate 1.794323 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1865791 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021104 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222840563 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 100994037 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86537266 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603668 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414920 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294049 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89974489 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301912 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1467836 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89041530 # Type of FU issued +system.cpu.iq.rate 1.838139 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1938672 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021773 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222789760 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102752204 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87020411 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 613188 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 432642 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299262 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90673556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 306646 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1613513 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2944970 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5006 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18410 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1655224 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3141958 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5326 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19773 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1842160 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2933 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 89330 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3009 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 163446 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1342238 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3674629 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 72016 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100198527 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23221608 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16268601 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5368 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49821 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6531 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18410 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 194109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 159104 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 353213 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87568841 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22612881 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 841769 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1448466 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3237152 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1283757 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101157149 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 209803 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23418596 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16455537 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5443 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41968 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1233080 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19773 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 207340 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 162214 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 369554 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88099058 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22735868 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 942472 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9478846 # number of nop insts executed -system.cpu.iew.exec_refs 38355645 # number of memory reference insts executed -system.cpu.iew.exec_branches 15084252 # Number of branches executed -system.cpu.iew.exec_stores 15742764 # Number of stores executed -system.cpu.iew.exec_rate 1.777239 # Inst execution rate -system.cpu.iew.wb_sent 87220375 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86831315 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33345689 # num instructions producing a value -system.cpu.iew.wb_consumers 43460058 # num instructions consuming a value +system.cpu.iew.exec_nop 9541349 # number of nop insts executed +system.cpu.iew.exec_refs 38590030 # number of memory reference insts executed +system.cpu.iew.exec_branches 15163094 # Number of branches executed +system.cpu.iew.exec_stores 15854162 # Number of stores executed +system.cpu.iew.exec_rate 1.818683 # Inst execution rate +system.cpu.iew.wb_sent 87723103 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87319673 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33922471 # num instructions producing a value +system.cpu.iew.wb_consumers 44377340 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.762271 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767272 # average fanout of values written-back +system.cpu.iew.wb_rate 1.802594 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764410 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8854011 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9580594 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 309865 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43319454 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.039284 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791171 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 321519 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41779952 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.114427 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.873182 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20467997 47.25% 47.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7041159 16.25% 63.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3392321 7.83% 71.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2059744 4.75% 76.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2024611 4.67% 80.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1169642 2.70% 83.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1101426 2.54% 86.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 720003 1.66% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5342551 12.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19839464 47.49% 47.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6575552 15.74% 63.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3029914 7.25% 70.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1889529 4.52% 75.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1770667 4.24% 79.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1150899 2.75% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1116698 2.67% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 758478 1.82% 86.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5648751 13.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43319454 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41779952 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -591,228 +594,229 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5342551 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5648751 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133854244 # The number of ROB reads -system.cpu.rob.rob_writes 195734344 # The number of ROB writes -system.cpu.timesIdled 83887 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4610712 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132735125 # The number of ROB reads +system.cpu.rob.rob_writes 197294055 # The number of ROB writes +system.cpu.timesIdled 86991 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5212705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.619064 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.619064 # CPI: Total CPI of All Threads -system.cpu.ipc 1.615341 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.615341 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115895624 # number of integer regfile reads -system.cpu.int_regfile_writes 57505324 # number of integer regfile writes -system.cpu.fp_regfile_reads 249507 # number of floating regfile reads -system.cpu.fp_regfile_writes 239755 # number of floating regfile writes -system.cpu.misc_regfile_reads 38031 # number of misc regfile reads +system.cpu.cpi 0.608620 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.608620 # CPI: Total CPI of All Threads +system.cpu.ipc 1.643062 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.643062 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116607972 # number of integer regfile reads +system.cpu.int_regfile_writes 57833573 # number of integer regfile writes +system.cpu.fp_regfile_reads 254535 # number of floating regfile reads +system.cpu.fp_regfile_writes 240366 # number of floating regfile writes +system.cpu.misc_regfile_reads 38019 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1215125035 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143416 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186521 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 766565 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5968640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29936064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29936064 # Total data (bytes) +system.cpu.toL2Bus.throughput 1241063981 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 157229 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 169024 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143424 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189945 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 770329 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6078208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23981056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 30059264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30059264 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402814000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141250965 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 403862500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 143810707 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 328598748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 325706997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91212 # number of replacements -system.cpu.icache.tags.tagsinuse 1925.511317 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13793650 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93260 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.905318 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19818994250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1925.511317 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940191 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940191 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 92924 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.308876 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14002846 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 94972 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.441835 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19458186000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.308876 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940581 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940581 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1531 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 356 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1533 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 355 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27892378 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27892378 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13793650 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13793650 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13793650 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13793650 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13793650 # number of overall hits -system.cpu.icache.overall_hits::total 13793650 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105909 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105909 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105909 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105909 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105909 # number of overall misses -system.cpu.icache.overall_misses::total 105909 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1976186457 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1976186457 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1976186457 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1976186457 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1976186457 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1976186457 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13899559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13899559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13899559 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13899559 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13899559 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13899559 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007620 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007620 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007620 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007620 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007620 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007620 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18659.287284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18659.287284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18659.287284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18659.287284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18659.287284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18659.287284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 681 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 28316122 # Number of tag accesses +system.cpu.icache.tags.data_accesses 28316122 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 14002846 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14002846 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14002846 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14002846 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14002846 # number of overall hits +system.cpu.icache.overall_hits::total 14002846 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 107729 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 107729 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 107729 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 107729 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 107729 # number of overall misses +system.cpu.icache.overall_misses::total 107729 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1994925704 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1994925704 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1994925704 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1994925704 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1994925704 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1994925704 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14110575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14110575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14110575 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14110575 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14110575 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14110575 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007635 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007635 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007635 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007635 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007635 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007635 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18518.000761 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18518.000761 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18518.000761 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18518.000761 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18518.000761 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18518.000761 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 21 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -821,171 +825,171 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114011 # number of writebacks -system.cpu.l2cache.writebacks::total 114011 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7675 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27857 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35532 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130793 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130793 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7675 # 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Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34149208 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205680 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.030766 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 220256000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4073.453777 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994496 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994496 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2926 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1087 # 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miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036818 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036818 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59951.390854 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59951.390854 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82026.539078 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82026.539078 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77506.281574 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77506.281574 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77506.281574 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77506.281574 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4834178 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35456138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35456138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35456138 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35456138 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012854 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012854 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071106 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071106 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036862 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036862 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036862 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036862 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60056.369788 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60056.369788 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81640.039430 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81640.039430 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77215.879185 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77215.879185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77215.879185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77215.879185 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5326980 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 104486 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116355 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.266275 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.782132 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168938 # number of writebacks -system.cpu.dcache.writebacks::total 168938 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205464 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205464 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895855 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895855 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 169024 # number of writebacks +system.cpu.dcache.writebacks::total 169024 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205645 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205645 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895674 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895674 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1101319 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1101319 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1101319 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1101319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62140 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62140 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143413 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143413 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205553 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205553 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205553 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205553 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2476433502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2476433502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13394078745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13394078745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15870512247 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15870512247 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15870512247 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15870512247 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62260 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62260 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143420 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143420 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205680 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205680 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205680 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205680 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2479695502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2479695502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13310863495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13310863495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15790558997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15790558997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15790558997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15790558997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002987 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002987 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39852.486353 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39852.486353 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93395.150684 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93395.150684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77208.857312 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77208.857312 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77208.857312 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77208.857312 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005801 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005801 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005801 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005801 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39828.067812 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39828.067812 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92810.371601 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92810.371601 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76772.457201 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76772.457201 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76772.457201 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76772.457201 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 20429e4aa..b90a29164 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,7 +699,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index 78695e4f1..1a4f96712 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 0fe32cbd7..72ee44be5 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:54:40 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:43:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5a6c340 + 0: system.cpu.isa: ISA system set to: 0 0x62769a0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 26790388000 because target called exit() +Exiting @ tick 25431292500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index ee5d7b3a8..8bf0c37c9 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026655 # Number of seconds simulated -sim_ticks 26655046000 # Number of ticks simulated -final_tick 26655046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025431 # Number of seconds simulated +sim_ticks 25431292500 # Number of ticks simulated +final_tick 25431292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108502 # Simulator instruction rate (inst/s) -host_op_rate 153979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40787374 # Simulator tick rate (ticks/s) -host_mem_usage 322284 # Number of bytes of host memory used -host_seconds 653.51 # Real time elapsed on the host +host_inst_rate 123125 # Simulator instruction rate (inst/s) +host_op_rate 174730 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44159257 # Simulator tick rate (ticks/s) +host_mem_usage 270444 # Number of bytes of host memory used +host_seconds 575.90 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 298176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372544 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372544 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4659 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128775 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83946 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83946 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11186475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 298008265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 309194739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11186475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11186475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 201558234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 201558234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 201558234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11186475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 298008265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 510752973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128776 # Number of read requests accepted -system.physmem.writeReqs 83946 # Number of write requests accepted -system.physmem.readBursts 128776 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83946 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8241344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8241664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372544 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 300416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942976 # Number of bytes read from this memory +system.physmem.bytes_read::total 8243392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 300416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 300416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128803 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11812848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 312330803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 324143651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11812848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11812848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 211249664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 211249664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 211249664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11812848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 312330803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 535393315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128804 # Number of read requests accepted +system.physmem.writeReqs 83943 # Number of write requests accepted +system.physmem.readBursts 128804 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83943 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8243072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8243456 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372352 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 320 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8145 # Per bank write bursts -system.physmem.perBankRdBursts::1 8395 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 342 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8140 # Per bank write bursts +system.physmem.perBankRdBursts::1 8383 # Per bank write bursts system.physmem.perBankRdBursts::2 8248 # Per bank write bursts -system.physmem.perBankRdBursts::3 8167 # Per bank write bursts -system.physmem.perBankRdBursts::4 8288 # Per bank write bursts -system.physmem.perBankRdBursts::5 8447 # Per bank write bursts -system.physmem.perBankRdBursts::6 8087 # Per bank write bursts -system.physmem.perBankRdBursts::7 7963 # Per bank write bursts -system.physmem.perBankRdBursts::8 8065 # Per bank write bursts +system.physmem.perBankRdBursts::3 8172 # Per bank write bursts +system.physmem.perBankRdBursts::4 8304 # Per bank write bursts +system.physmem.perBankRdBursts::5 8450 # Per bank write bursts +system.physmem.perBankRdBursts::6 8104 # Per bank write bursts +system.physmem.perBankRdBursts::7 7960 # Per bank write bursts +system.physmem.perBankRdBursts::8 8081 # Per bank write bursts system.physmem.perBankRdBursts::9 7608 # Per bank write bursts system.physmem.perBankRdBursts::10 7787 # Per bank write bursts -system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::11 7813 # Per bank write bursts system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7885 # Per bank write bursts -system.physmem.perBankRdBursts::14 7978 # Per bank write bursts -system.physmem.perBankRdBursts::15 8011 # Per bank write bursts -system.physmem.perBankWrBursts::0 5180 # Per bank write bursts -system.physmem.perBankWrBursts::1 5377 # Per bank write bursts +system.physmem.perBankRdBursts::13 7882 # Per bank write bursts +system.physmem.perBankRdBursts::14 7972 # Per bank write bursts +system.physmem.perBankRdBursts::15 8012 # Per bank write bursts +system.physmem.perBankWrBursts::0 5177 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5291 # Per bank write bursts -system.physmem.perBankWrBursts::3 5157 # Per bank write bursts +system.physmem.perBankWrBursts::3 5156 # Per bank write bursts system.physmem.perBankWrBursts::4 5265 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5199 # Per bank write bursts -system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::6 5200 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts system.physmem.perBankWrBursts::8 5030 # Per bank write bursts -system.physmem.perBankWrBursts::9 5091 # Per bank write bursts -system.physmem.perBankWrBursts::10 5246 # Per bank write bursts -system.physmem.perBankWrBursts::11 5144 # Per bank write bursts -system.physmem.perBankWrBursts::12 5342 # Per bank write bursts +system.physmem.perBankWrBursts::9 5089 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5142 # Per bank write bursts +system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5225 # Per bank write bursts +system.physmem.perBankWrBursts::15 5223 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26655030500 # Total gap between requests +system.physmem.totGap 25431274000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128776 # Read request sizes (log2) +system.physmem.readPktSize::6 128804 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83946 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 74138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 53140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83943 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 74268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 52779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5202 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,98 +193,97 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.014390 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.175335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.156707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12089 31.98% 31.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7874 20.83% 52.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3781 10.00% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2728 7.22% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2397 6.34% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1617 4.28% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1220 3.23% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1066 2.82% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5032 13.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37804 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5144 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.030132 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 392.032521 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5142 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5144 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5144 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.315513 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.292869 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.917660 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4492 87.33% 87.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.12% 87.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 431 8.38% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 161 3.13% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 33 0.64% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 11 0.21% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 6 0.12% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5144 # Writes before turning the bus around for reads -system.physmem.totQLat 2471536000 # Total ticks spent queuing -system.physmem.totMemAccLat 4885992250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19193.27 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 37764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.466900 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.757090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.203142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11986 31.74% 31.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7964 21.09% 52.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3753 9.94% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2738 7.25% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2422 6.41% 76.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1565 4.14% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1215 3.22% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1119 2.96% 86.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5002 13.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37764 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5143 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.040249 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.430137 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5140 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5143 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.318102 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.295777 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.900493 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4492 87.34% 87.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.17% 87.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 404 7.86% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 175 3.40% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 41 0.80% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 14 0.27% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 4 0.08% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5143 # Writes before turning the bus around for reads +system.physmem.totQLat 2477042500 # Total ticks spent queuing +system.physmem.totMemAccLat 4892005000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643990000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19232.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37943.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 309.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 201.51 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 309.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 201.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37982.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 324.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 211.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 324.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 211.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.99 # Data bus utilization in percentage -system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.52 # Average write queue length when enqueuing -system.physmem.readRowHits 112800 # Number of row buffer hits during reads -system.physmem.writeRowHits 62083 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.96 # Row buffer hit rate for writes -system.physmem.avgGap 125304.53 # Average gap between requests -system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11333884750 # Time in different power states -system.physmem.memoryStateTime::REF 889980000 # Time in different power states +system.physmem.busUtil 4.18 # Data bus utilization in percentage +system.physmem.busUtilRead 2.53 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.65 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.78 # Average write queue length when enqueuing +system.physmem.readRowHits 112907 # Number of row buffer hits during reads +system.physmem.writeRowHits 62042 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.91 # Row buffer hit rate for writes +system.physmem.avgGap 119537.64 # Average gap between requests +system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 10352020250 # Time in different power states +system.physmem.memoryStateTime::REF 849160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 14428773750 # Time in different power states +system.physmem.memoryStateTime::ACT 14228986000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 510752973 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26520 # Transaction distribution -system.membus.trans_dist::ReadResp 26519 # Transaction distribution -system.membus.trans_dist::Writeback 83946 # Transaction distribution -system.membus.trans_dist::UpgradeReq 320 # Transaction distribution -system.membus.trans_dist::UpgradeResp 320 # Transaction distribution -system.membus.trans_dist::ReadExReq 102256 # Transaction distribution -system.membus.trans_dist::ReadExResp 102256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342137 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342137 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614144 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13614144 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13614144 # Total data (bytes) +system.membus.throughput 535393315 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26553 # Transaction distribution +system.membus.trans_dist::ReadResp 26552 # Transaction distribution +system.membus.trans_dist::Writeback 83943 # Transaction distribution +system.membus.trans_dist::UpgradeReq 342 # Transaction distribution +system.membus.trans_dist::UpgradeResp 342 # Transaction distribution +system.membus.trans_dist::ReadExReq 102251 # Transaction distribution +system.membus.trans_dist::ReadExResp 102251 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342234 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13615744 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13615744 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13615744 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 932451500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 901934500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1211794930 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1187807158 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16636502 # Number of BP lookups -system.cpu.branchPred.condPredicted 12767541 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 605249 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10577266 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7776939 # Number of BTB hits +system.cpu.branchPred.lookups 17001662 # Number of BP lookups +system.cpu.branchPred.condPredicted 13020210 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 614898 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10708539 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7958691 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.525039 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1824082 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113194 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 74.320979 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1855518 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113838 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -370,239 +369,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53310093 # number of cpu cycles simulated +system.cpu.numCycles 50862586 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12544266 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85245132 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16636502 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9601021 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21203621 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2373453 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10826846 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 346 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11685368 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 181941 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46316681 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.577051 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.331362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12841579 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87379296 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17001662 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9814209 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21679126 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2704202 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6435967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11938705 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 201875 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43012606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.839331 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389146 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25133357 54.26% 54.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2139356 4.62% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1964088 4.24% 63.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042720 4.41% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1470632 3.18% 70.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1380684 2.98% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958438 2.07% 75.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1191046 2.57% 78.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10036360 21.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21356489 49.65% 49.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2172665 5.05% 54.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2009321 4.67% 59.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2081413 4.84% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1500240 3.49% 67.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1419840 3.30% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 985272 2.29% 73.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1219233 2.83% 76.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10268133 23.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46316681 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.312070 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.599043 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14641724 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9163742 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19491129 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1382035 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1638051 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3333190 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105248 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116897409 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363517 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1638051 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16359930 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2678860 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1013546 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19105164 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5521130 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115000815 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 16720 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4660350 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 282 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115331621 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529914525 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476510410 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2776 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43012606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.334267 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.717948 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13769056 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5959303 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20895341 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 441693 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1947213 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3430949 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 110387 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119589480 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 395300 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1947213 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14636498 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 284865 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1020852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20468957 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4654221 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117623188 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 544 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 181856 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2734092 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1628680 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 1673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117928367 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541896046 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 487330730 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3427 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16198949 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20436 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20434 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13095384 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29625138 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22434042 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3869725 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4362550 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111565619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36058 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107262004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 275498 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10829281 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25946611 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2272 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46316681 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.315840 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990470 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 18795695 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20563 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20550 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5392644 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30100241 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22927452 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5590192 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5698921 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113818479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36102 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108240105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 379531 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13068972 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32214297 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2316 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43012606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.516474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.084237 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11030019 23.81% 23.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8138803 17.57% 41.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7430883 16.04% 57.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7110857 15.35% 72.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5417654 11.70% 84.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3891349 8.40% 92.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1848302 3.99% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 878821 1.90% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 569993 1.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9996470 23.24% 23.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6251950 14.54% 37.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6474591 15.05% 52.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6613067 15.37% 68.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5424130 12.61% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4356381 10.13% 90.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2112627 4.91% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1221535 2.84% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 561855 1.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46316681 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43012606 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 113827 4.59% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1360293 54.84% 59.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1006288 40.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 131486 5.24% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1416079 56.44% 61.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 961652 38.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56646184 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91539 0.09% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 222 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28903042 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21621010 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57280619 52.92% 52.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91502 0.08% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 249 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29070055 26.86% 79.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21797673 20.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107262004 # Type of FU issued -system.cpu.iq.rate 2.012039 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2480410 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023125 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263595997 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122458930 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105571537 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 600 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 932 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 176 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109742111 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 303 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2179776 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108240105 # Type of FU issued +system.cpu.iq.rate 2.128089 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2509218 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023182 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262380760 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 126960554 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106504533 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 805 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110748938 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 385 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2726538 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2318030 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6495 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30041 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1878304 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2793133 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5994 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 39986 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2371714 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 708 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 777 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1638051 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1126663 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45667 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111611483 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 295320 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29625138 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22434042 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20138 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6203 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5120 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30041 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 394287 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181285 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 575572 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106232062 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28604336 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1029942 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1947213 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 83242 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 154560 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113864521 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 271261 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30100241 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22927452 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20182 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 11127 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 139253 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 39986 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 397706 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 183440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 581146 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107196907 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28742416 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1043198 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9806 # number of nop insts executed -system.cpu.iew.exec_refs 49939736 # number of memory reference insts executed -system.cpu.iew.exec_branches 14601830 # Number of branches executed -system.cpu.iew.exec_stores 21335400 # Number of stores executed -system.cpu.iew.exec_rate 1.992720 # Inst execution rate -system.cpu.iew.wb_sent 105794271 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105571713 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53289529 # num instructions producing a value -system.cpu.iew.wb_consumers 103696689 # num instructions consuming a value +system.cpu.iew.exec_nop 9940 # number of nop insts executed +system.cpu.iew.exec_refs 50252614 # number of memory reference insts executed +system.cpu.iew.exec_branches 14716112 # Number of branches executed +system.cpu.iew.exec_stores 21510198 # Number of stores executed +system.cpu.iew.exec_rate 2.107579 # Inst execution rate +system.cpu.iew.wb_sent 106740577 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106504731 # cumulative count of insts written-back +system.cpu.iew.wb_producers 57038202 # num instructions producing a value +system.cpu.iew.wb_consumers 114479064 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.980333 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.513898 # average fanout of values written-back +system.cpu.iew.wb_rate 2.093970 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498241 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10980049 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13236328 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 501819 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44678630 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.252362 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.761359 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 506712 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41065393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.450541 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.921831 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15558775 34.82% 34.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11701818 26.19% 61.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3471869 7.77% 68.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2879306 6.44% 75.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1869514 4.18% 79.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1922443 4.30% 83.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 688922 1.54% 85.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 562713 1.26% 86.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6023270 13.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14078032 34.28% 34.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10319124 25.13% 59.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2761047 6.72% 66.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2619650 6.38% 72.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1508272 3.67% 76.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1822351 4.44% 80.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 663911 1.62% 82.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 540097 1.32% 83.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6752909 16.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44678630 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41065393 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -648,242 +648,242 @@ system.cpu.commit.op_class_0::MemWrite 20555738 20.43% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 100632428 # Class of committed instruction -system.cpu.commit.bw_lim_events 6023270 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6752909 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150242538 # The number of ROB reads -system.cpu.rob.rob_writes 224871982 # The number of ROB writes -system.cpu.timesIdled 79510 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6993412 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 148155941 # The number of ROB reads +system.cpu.rob.rob_writes 229697127 # The number of ROB writes +system.cpu.timesIdled 83826 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7849980 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.751825 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.751825 # CPI: Total CPI of All Threads -system.cpu.ipc 1.330098 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.330098 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511631717 # number of integer regfile reads -system.cpu.int_regfile_writes 103353872 # number of integer regfile writes -system.cpu.fp_regfile_reads 846 # number of floating regfile reads -system.cpu.fp_regfile_writes 710 # number of floating regfile writes -system.cpu.misc_regfile_reads 49341635 # number of misc regfile reads +system.cpu.cpi 0.717308 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.717308 # CPI: Total CPI of All Threads +system.cpu.ipc 1.394102 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.394102 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 515806241 # number of integer regfile reads +system.cpu.int_regfile_writes 104262317 # number of integer regfile writes +system.cpu.fp_regfile_reads 1054 # number of floating regfile reads +system.cpu.fp_regfile_writes 938 # number of floating regfile writes +system.cpu.misc_regfile_reads 49641533 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 775139386 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 86625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 86624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129165 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107045 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62039 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454624 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 516663 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1968896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20628672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20628672 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 32704 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290752497 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 820945141 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 90021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 90020 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68737 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454707 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 523444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2182208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20843008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20843008 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 34688 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 292444997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47657477 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 52710982 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 267144007 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 261104274 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 28917 # number of replacements -system.cpu.icache.tags.tagsinuse 1807.865134 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11650266 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 30950 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 376.422165 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 32259 # number of replacements +system.cpu.icache.tags.tagsinuse 1808.767041 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11900174 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 34296 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 346.984313 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1807.865134 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.882747 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.882747 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2033 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1259 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.992676 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23402009 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23402009 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11650274 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11650274 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11650274 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11650274 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11650274 # number of overall hits -system.cpu.icache.overall_hits::total 11650274 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35093 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35093 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35093 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35093 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35093 # number of overall misses -system.cpu.icache.overall_misses::total 35093 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 796173972 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 796173972 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 796173972 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 796173972 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 796173972 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 796173972 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11685367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11685367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11685367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11685367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11685367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11685367 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003003 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003003 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22687.543727 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22687.543727 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22687.543727 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22687.543727 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22687.543727 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22687.543727 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1584 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1808.767041 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.883187 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.883187 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2037 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 674 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.994629 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 23912047 # Number of tag accesses +system.cpu.icache.tags.data_accesses 23912047 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 11900181 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11900181 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11900181 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11900181 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11900181 # number of overall hits +system.cpu.icache.overall_hits::total 11900181 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38523 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38523 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38523 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38523 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38523 # number of overall misses +system.cpu.icache.overall_misses::total 38523 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 840683730 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 840683730 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 840683730 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 840683730 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 840683730 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 840683730 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11938704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11938704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11938704 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11938704 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11938704 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11938704 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003227 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003227 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003227 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003227 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003227 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003227 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21822.903979 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21822.903979 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21822.903979 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21822.903979 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21822.903979 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21822.903979 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1168 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60.923077 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.275862 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3818 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3818 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3818 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3818 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3818 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3818 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31275 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31275 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31275 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31275 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31275 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31275 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 647196022 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 647196022 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 647196022 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 647196022 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 647196022 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 647196022 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.717730 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.717730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.717730 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.717730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.717730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.717730 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3883 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3883 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3883 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3883 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3883 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3883 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34640 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 34640 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 34640 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 34640 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 34640 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 34640 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 683348518 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 683348518 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 683348518 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 683348518 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 683348518 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 683348518 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002901 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002901 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002901 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19727.151212 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19727.151212 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19727.151212 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19727.151212 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19727.151212 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19727.151212 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95645 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29867.639929 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 88414 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126758 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.697502 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95674 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29835.516778 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 91740 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126786 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.723581 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26665.630532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1369.813019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1832.196377 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.813770 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.055914 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.911488 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1847 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20513 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8219 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949493 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2815092 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2815092 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26089 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59518 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129165 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129165 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26089 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38217 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 64306 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26089 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38217 # number of overall hits -system.cpu.l2cache.overall_hits::total 64306 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4675 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21921 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26596 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 319 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 319 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4675 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124178 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128853 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124178 # number of overall misses -system.cpu.l2cache.overall_misses::total 128853 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 354274500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1813961250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2168235750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8348408999 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8348408999 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 354274500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10162370249 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10516644749 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8644275750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8938473500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.137691 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394684 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.296751 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.957983 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.957983 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955286 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955286 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.137691 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.655438 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.137691 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.655438 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62661.927583 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70426.651569 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69053.722743 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10036.087719 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10036.087719 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69484.797215 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69484.797215 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62661.927583 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69650.676019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69395.931027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62661.927583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69650.676019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69395.931027 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158298 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.579596 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44367951 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162394 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 273.211763 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 366659250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.579596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 158322 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.859586 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43957323 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162418 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 270.643174 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 358577250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.859586 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993130 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1762 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1830 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 92310952 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 92310952 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 26067775 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26067775 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18267649 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18267649 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15993 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15993 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 91492426 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91492426 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 25658218 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 25658218 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266460 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266460 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 16005 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 16005 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44335424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44335424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44335424 # number of overall hits -system.cpu.dcache.overall_hits::total 44335424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124650 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124650 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1582252 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1582252 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1706902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1706902 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1706902 # number of overall misses -system.cpu.dcache.overall_misses::total 1706902 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5082447470 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5082447470 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 124553146004 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 124553146004 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 917250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 917250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 129635593474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 129635593474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 129635593474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 129635593474 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26192425 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26192425 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 43924678 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 43924678 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 43924678 # number of overall hits +system.cpu.dcache.overall_hits::total 43924678 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124918 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124918 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583441 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583441 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708359 # number of overall misses +system.cpu.dcache.overall_misses::total 1708359 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5184955254 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5184955254 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 125206065525 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 125206065525 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 993000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 993000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 130391020779 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 130391020779 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 130391020779 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 130391020779 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 25783136 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 25783136 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16034 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16034 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16048 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16048 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46042326 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46042326 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46042326 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46042326 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004759 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004759 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079711 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079711 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002557 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002557 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037072 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037072 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037072 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037072 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40773.746249 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40773.746249 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78718.905714 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 78718.905714 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22371.951220 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22371.951220 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75947.883050 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75947.883050 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75947.883050 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75947.883050 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3831 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1303 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 134 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.589552 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81.437500 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 45633037 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 45633037 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 45633037 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 45633037 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004845 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004845 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079771 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079771 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002679 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002679 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037437 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037437 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037437 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037437 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41506.870539 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41506.870539 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79072.138163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79072.138163 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23093.023256 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23093.023256 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76325.304447 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76325.304447 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76325.304447 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76325.304447 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4253 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1744 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.597122 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.272727 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129165 # number of writebacks -system.cpu.dcache.writebacks::total 129165 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69269 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69269 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1474904 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1474904 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544173 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544173 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544173 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544173 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55381 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55381 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107348 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107348 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 129157 # number of writebacks +system.cpu.dcache.writebacks::total 129157 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69501 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69501 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1476084 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1476084 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545585 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545585 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545585 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545585 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107357 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107357 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162729 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162729 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162729 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162729 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2206437312 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2206437312 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8512084920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8512084920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 11500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 11500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10718522232 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10718522232 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10718522232 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10718522232 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002114 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002114 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 162774 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162774 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162774 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162774 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2210443817 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2210443817 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8528691900 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8528691900 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 11000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 11000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10739135717 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10739135717 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10739135717 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10739135717 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002149 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.000062 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000062 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003534 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003534 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003534 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003534 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39841.052202 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39841.052202 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79294.303760 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79294.303760 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65867.314566 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65867.314566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65867.314566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65867.314566 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003567 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39887.468051 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39887.468051 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79442.345632 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79442.345632 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65975.743774 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65975.743774 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65975.743774 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65975.743774 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 20db05a32..b1e14ff22 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index b7f8b903e..5b5bf25c6 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 18:30:51 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 16:50:46 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +25,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 685386545000 because target called exit() +Exiting @ tick 679349778000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index aae431db6..e324bc13d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.680209 # Number of seconds simulated -sim_ticks 680209231000 # Number of ticks simulated -final_tick 680209231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.679350 # Number of seconds simulated +sim_ticks 679349778000 # Number of ticks simulated +final_tick 679349778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134123 # Simulator instruction rate (inst/s) -host_op_rate 134123 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52551522 # Simulator tick rate (ticks/s) -host_mem_usage 268516 # Number of bytes of host memory used -host_seconds 12943.66 # Real time elapsed on the host +host_inst_rate 165098 # Simulator instruction rate (inst/s) +host_op_rate 165098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64606302 # Simulator tick rate (ticks/s) +host_mem_usage 222340 # Number of bytes of host memory used +host_seconds 10515.22 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125794880 # Number of bytes read from this memory -system.physmem.bytes_read::total 125856448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65262848 # Number of bytes written to this memory -system.physmem.bytes_written::total 65262848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965545 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966507 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019732 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019732 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 184935567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 185026081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90513 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90513 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95945255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95945255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95945255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 184935567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 280971335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966507 # Number of read requests accepted -system.physmem.writeReqs 1019732 # Number of write requests accepted -system.physmem.readBursts 1966507 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019732 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125774784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81664 # Total number of bytes read from write queue -system.physmem.bytesWritten 65260864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125856448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65262848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1276 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125814720 # Number of bytes read from this memory +system.physmem.bytes_read::total 125876544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265856 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965855 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966821 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019779 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019779 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 185198736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 185289740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91005 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91005 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96071064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96071064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96071064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 185198736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 281360804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966821 # Number of read requests accepted +system.physmem.writeReqs 1019779 # Number of write requests accepted +system.physmem.readBursts 1966821 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019779 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125795136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81408 # Total number of bytes read from write queue +system.physmem.bytesWritten 65264000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125876544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65265856 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1272 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118983 # Per bank write bursts -system.physmem.perBankRdBursts::1 114362 # Per bank write bursts -system.physmem.perBankRdBursts::2 116533 # Per bank write bursts -system.physmem.perBankRdBursts::3 118021 # Per bank write bursts -system.physmem.perBankRdBursts::4 118095 # Per bank write bursts -system.physmem.perBankRdBursts::5 117780 # Per bank write bursts -system.physmem.perBankRdBursts::6 120157 # Per bank write bursts -system.physmem.perBankRdBursts::7 124901 # Per bank write bursts -system.physmem.perBankRdBursts::8 127484 # Per bank write bursts -system.physmem.perBankRdBursts::9 130413 # Per bank write bursts -system.physmem.perBankRdBursts::10 129050 # Per bank write bursts -system.physmem.perBankRdBursts::11 130729 # Per bank write bursts -system.physmem.perBankRdBursts::12 126632 # Per bank write bursts -system.physmem.perBankRdBursts::13 125586 # Per bank write bursts -system.physmem.perBankRdBursts::14 122901 # Per bank write bursts -system.physmem.perBankRdBursts::15 123604 # Per bank write bursts -system.physmem.perBankWrBursts::0 61270 # Per bank write bursts -system.physmem.perBankWrBursts::1 61551 # Per bank write bursts -system.physmem.perBankWrBursts::2 60668 # Per bank write bursts -system.physmem.perBankWrBursts::3 61328 # Per bank write bursts -system.physmem.perBankWrBursts::4 61752 # Per bank write bursts -system.physmem.perBankWrBursts::5 63187 # Per bank write bursts -system.physmem.perBankWrBursts::6 64234 # Per bank write bursts -system.physmem.perBankWrBursts::7 65693 # Per bank write bursts -system.physmem.perBankWrBursts::8 65471 # Per bank write bursts -system.physmem.perBankWrBursts::9 65863 # Per bank write bursts -system.physmem.perBankWrBursts::10 65411 # Per bank write bursts -system.physmem.perBankWrBursts::11 65720 # Per bank write bursts -system.physmem.perBankWrBursts::12 64318 # Per bank write bursts -system.physmem.perBankWrBursts::13 64300 # Per bank write bursts -system.physmem.perBankWrBursts::14 64642 # Per bank write bursts -system.physmem.perBankWrBursts::15 64293 # Per bank write bursts +system.physmem.perBankRdBursts::0 118990 # Per bank write bursts +system.physmem.perBankRdBursts::1 114401 # Per bank write bursts +system.physmem.perBankRdBursts::2 116526 # Per bank write bursts +system.physmem.perBankRdBursts::3 118038 # Per bank write bursts +system.physmem.perBankRdBursts::4 118100 # Per bank write bursts +system.physmem.perBankRdBursts::5 117781 # Per bank write bursts +system.physmem.perBankRdBursts::6 120191 # Per bank write bursts +system.physmem.perBankRdBursts::7 124916 # Per bank write bursts +system.physmem.perBankRdBursts::8 127523 # Per bank write bursts +system.physmem.perBankRdBursts::9 130444 # Per bank write bursts +system.physmem.perBankRdBursts::10 129055 # Per bank write bursts +system.physmem.perBankRdBursts::11 130769 # Per bank write bursts +system.physmem.perBankRdBursts::12 126629 # Per bank write bursts +system.physmem.perBankRdBursts::13 125625 # Per bank write bursts +system.physmem.perBankRdBursts::14 122929 # Per bank write bursts +system.physmem.perBankRdBursts::15 123632 # Per bank write bursts +system.physmem.perBankWrBursts::0 61276 # Per bank write bursts +system.physmem.perBankWrBursts::1 61573 # Per bank write bursts +system.physmem.perBankWrBursts::2 60655 # Per bank write bursts +system.physmem.perBankWrBursts::3 61329 # Per bank write bursts +system.physmem.perBankWrBursts::4 61751 # Per bank write bursts +system.physmem.perBankWrBursts::5 63183 # Per bank write bursts +system.physmem.perBankWrBursts::6 64216 # Per bank write bursts +system.physmem.perBankWrBursts::7 65714 # Per bank write bursts +system.physmem.perBankWrBursts::8 65484 # Per bank write bursts +system.physmem.perBankWrBursts::9 65866 # Per bank write bursts +system.physmem.perBankWrBursts::10 65407 # Per bank write bursts +system.physmem.perBankWrBursts::11 65735 # Per bank write bursts +system.physmem.perBankWrBursts::12 64310 # Per bank write bursts +system.physmem.perBankWrBursts::13 64307 # Per bank write bursts +system.physmem.perBankWrBursts::14 64646 # Per bank write bursts +system.physmem.perBankWrBursts::15 64298 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 680209108500 # Total gap between requests +system.physmem.totGap 679349688500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966507 # Read request sizes (log2) +system.physmem.readPktSize::6 1966821 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019732 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1643607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 226349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 73697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019779 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1643770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 225726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 72200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 63111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 50000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 63137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see @@ -193,130 +193,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1771936 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.810521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.950451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.949127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1375751 77.64% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 273384 15.43% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53057 2.99% 96.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21092 1.19% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12942 0.73% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6638 0.37% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4973 0.28% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3952 0.22% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20147 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1771936 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59540 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.963117 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 163.210264 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59503 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1771721 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.836103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.953832 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.029832 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1375665 77.65% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 272762 15.40% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53440 3.02% 96.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21316 1.20% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12827 0.72% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6576 0.37% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5044 0.28% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3861 0.22% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20230 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1771721 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.942421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 164.012858 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59550 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 13 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59540 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59540 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.126318 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.084701 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.213811 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29197 49.04% 49.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1546 2.60% 51.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 22630 38.01% 89.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4967 8.34% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 921 1.55% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 191 0.32% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 48 0.08% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59540 # Writes before turning the bus around for reads -system.physmem.totQLat 40008960000 # Total ticks spent queuing -system.physmem.totMemAccLat 76857041250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9826155000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20358.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59588 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59588 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.113345 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.071670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.230173 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 30977 51.99% 51.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 27509 46.17% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 1030 1.73% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 43 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 11 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59588 # Writes before turning the bus around for reads +system.physmem.totQLat 40014194750 # Total ticks spent queuing +system.physmem.totMemAccLat 76868238500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9827745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20357.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39108.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 184.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 185.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39107.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 185.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 185.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.19 # Data bus utilization in percentage -system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.20 # Data bus utilization in percentage +system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing -system.physmem.readRowHits 795143 # Number of row buffer hits during reads -system.physmem.writeRowHits 417847 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.98 # Row buffer hit rate for writes -system.physmem.avgGap 227781.20 # Average gap between requests -system.physmem.pageHitRate 40.64 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 135240615750 # Time in different power states -system.physmem.memoryStateTime::REF 22713600000 # Time in different power states +system.physmem.avgWrQLen 25.15 # Average write queue length when enqueuing +system.physmem.readRowHits 795833 # Number of row buffer hits during reads +system.physmem.writeRowHits 417735 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.96 # Row buffer hit rate for writes +system.physmem.avgGap 227465.91 # Average gap between requests +system.physmem.pageHitRate 40.65 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 134374460000 # Time in different power states +system.physmem.memoryStateTime::REF 22684740000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 522252858000 # Time in different power states +system.physmem.memoryStateTime::ACT 522286376500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 280971335 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191350 # Transaction distribution -system.membus.trans_dist::ReadResp 1191350 # Transaction distribution -system.membus.trans_dist::Writeback 1019732 # Transaction distribution -system.membus.trans_dist::ReadExReq 775157 # Transaction distribution -system.membus.trans_dist::ReadExResp 775157 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952746 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191119296 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191119296 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191119296 # Total data (bytes) +system.membus.throughput 281360804 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191893 # Transaction distribution +system.membus.trans_dist::ReadResp 1191893 # Transaction distribution +system.membus.trans_dist::Writeback 1019779 # Transaction distribution +system.membus.trans_dist::ReadExReq 774928 # Transaction distribution +system.membus.trans_dist::ReadExResp 774928 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4953421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4953421 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191142400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191142400 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191142400 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11871718000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11809306000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18474668250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18437139750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 381496982 # Number of BP lookups -system.cpu.branchPred.condPredicted 296448748 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16088801 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262281784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259596653 # Number of BTB hits +system.cpu.branchPred.lookups 390516660 # Number of BP lookups +system.cpu.branchPred.condPredicted 303583970 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16113462 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 268537122 # Number of BTB lookups +system.cpu.branchPred.BTBHits 266026822 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.976242 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24710775 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3135 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.065194 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25282995 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613956448 # DTB read hits -system.cpu.dtb.read_misses 11261576 # DTB read misses +system.cpu.dtb.read_hits 621222786 # DTB read hits +system.cpu.dtb.read_misses 11503040 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625218024 # DTB read accesses -system.cpu.dtb.write_hits 212357219 # DTB write hits -system.cpu.dtb.write_misses 7142526 # DTB write misses +system.cpu.dtb.read_accesses 632725826 # DTB read accesses +system.cpu.dtb.write_hits 213831979 # DTB write hits +system.cpu.dtb.write_misses 7254265 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219499745 # DTB write accesses -system.cpu.dtb.data_hits 826313667 # DTB hits -system.cpu.dtb.data_misses 18404102 # DTB misses +system.cpu.dtb.write_accesses 221086244 # DTB write accesses +system.cpu.dtb.data_hits 835054765 # DTB hits +system.cpu.dtb.data_misses 18757305 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844717769 # DTB accesses -system.cpu.itb.fetch_hits 391069582 # ITB hits -system.cpu.itb.fetch_misses 39 # ITB misses +system.cpu.dtb.data_accesses 853812070 # DTB accesses +system.cpu.itb.fetch_hits 400046189 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391069621 # ITB accesses +system.cpu.itb.fetch_accesses 400046233 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -330,237 +325,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1360418463 # number of cpu cycles simulated +system.cpu.numCycles 1358699557 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402539494 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3160334453 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381496982 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284307428 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574405529 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140578200 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 186557630 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1439 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 391069582 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8066485 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1280247946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.468533 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 410929991 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3243314345 # Number of instructions fetch has processed +system.cpu.fetch.Branches 390516660 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 291309817 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 589336372 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 147340013 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133548447 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1456 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 400046189 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9025513 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1257254668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.579680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.173136 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 705842417 55.13% 55.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42672657 3.33% 58.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21781408 1.70% 60.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39699602 3.10% 63.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129277672 10.10% 73.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61541075 4.81% 78.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38576961 3.01% 81.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28126887 2.20% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212729267 16.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 667918296 53.13% 53.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 44267394 3.52% 56.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22207289 1.77% 58.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40636739 3.23% 61.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 131869370 10.49% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 62966774 5.01% 77.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40227274 3.20% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28245094 2.25% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 218916438 17.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1280247946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.280426 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.323061 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434538205 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167760960 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542351250 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18854501 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116743030 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58351365 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 885 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3087789939 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2070 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116743030 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457481337 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 112438612 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7413 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535473100 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 58104454 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3005831981 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610085 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1830591 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51785017 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2247201366 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3898074686 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3897930349 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 144336 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1257254668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.287419 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.387072 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 430550615 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 129659255 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 568815009 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4792365 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 123437424 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 59500767 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 917 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3153748807 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2128 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 123437424 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 446386402 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61779163 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6860 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 557518816 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68126003 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3069486898 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1505727 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6123879 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 54202488 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 8466199 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2295837862 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3983545178 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3983398130 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 147047 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 870998403 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 181 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123645792 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679622906 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255441649 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67625349 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36837000 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2724438630 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 139 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509429146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3195077 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979206212 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 415660734 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1280247946 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.960112 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971405 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 919634899 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 203 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 202 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 44876150 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 692163471 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 260495859 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 73383628 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38808502 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2780183806 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 184 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2536585762 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4364880 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1034533664 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 460650584 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 155 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1257254668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.017559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.009997 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 438364734 34.24% 34.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203576191 15.90% 50.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185673841 14.50% 64.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153359678 11.98% 76.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133007255 10.39% 87.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80763135 6.31% 93.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65057682 5.08% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15327988 1.20% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5117442 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 428157011 34.05% 34.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 188380197 14.98% 49.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 177998596 14.16% 63.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153960413 12.25% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 135215337 10.75% 86.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80818226 6.43% 92.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 69593138 5.54% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17238172 1.37% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5893578 0.47% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1280247946 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1257254668 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2183926 11.79% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11926883 64.38% 76.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4416070 23.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2760636 13.79% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12853797 64.19% 77.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4410220 22.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643735577 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 274 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641577426 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224115520 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1663143410 65.57% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 259 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 21 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 647516942 25.53% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 225924828 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509429146 # Type of FU issued -system.cpu.iq.rate 1.844601 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18526879 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007383 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6318927693 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3702533179 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413056574 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1900501 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1218976 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 851931 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527016485 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 939540 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62611923 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2536585762 # Type of FU issued +system.cpu.iq.rate 1.866922 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20024653 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007894 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6352883505 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3813585390 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2440929650 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1932220 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1252073 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 864209 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2555655812 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 954603 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64558247 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235027243 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263015 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 108918 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94713147 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 247567808 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 343004 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 121628 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 99767357 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 189 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1519116 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1607198 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116743030 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 54024400 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1298779 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2866611550 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8938226 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679622906 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255441649 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 139 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 284739 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17925 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 108918 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10360501 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8559141 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18919642 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462113163 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625218563 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47315983 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 123437424 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22713536 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8297734 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2923674181 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8955846 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 692163471 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 260495859 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 184 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 449856 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8304684 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 121628 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10428435 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8597760 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19026195 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2492121408 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 632726353 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 44464354 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142172781 # number of nop insts executed -system.cpu.iew.exec_refs 844718328 # number of memory reference insts executed -system.cpu.iew.exec_branches 300875979 # Number of branches executed -system.cpu.iew.exec_stores 219499765 # Number of stores executed -system.cpu.iew.exec_rate 1.809820 # Inst execution rate -system.cpu.iew.wb_sent 2441867145 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413908505 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388259644 # num instructions producing a value -system.cpu.iew.wb_consumers 1764197986 # num instructions consuming a value +system.cpu.iew.exec_nop 143490191 # number of nop insts executed +system.cpu.iew.exec_refs 853812632 # number of memory reference insts executed +system.cpu.iew.exec_branches 304222027 # Number of branches executed +system.cpu.iew.exec_stores 221086279 # Number of stores executed +system.cpu.iew.exec_rate 1.834196 # Inst execution rate +system.cpu.iew.wb_sent 2470047897 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2441793859 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1422096892 # num instructions producing a value +system.cpu.iew.wb_consumers 1830175974 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.774387 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back +system.cpu.iew.wb_rate 1.797155 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.777027 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 826160079 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 873443731 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16088003 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1163504916 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.564050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.502160 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16112643 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1133817244 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.605003 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541695 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 649463962 55.82% 55.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174969107 15.04% 70.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86152065 7.40% 78.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53532710 4.60% 82.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34727147 2.98% 85.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26083842 2.24% 88.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21573250 1.85% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22881203 1.97% 91.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94121630 8.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 625261340 55.15% 55.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 171314027 15.11% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86268180 7.61% 77.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54871559 4.84% 82.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 31288205 2.76% 85.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20767631 1.83% 87.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 23576751 2.08% 89.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22892827 2.02% 91.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 97576724 8.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1163504916 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1133817244 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -606,223 +603,224 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 94121630 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 97576724 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3629544291 # The number of ROB reads -system.cpu.rob.rob_writes 5408721730 # The number of ROB writes -system.cpu.timesIdled 949757 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80170517 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3643685177 # The number of ROB reads +system.cpu.rob.rob_writes 5509997541 # The number of ROB writes +system.cpu.timesIdled 1119552 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 101444889 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.783631 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.783631 # CPI: Total CPI of All Threads -system.cpu.ipc 1.276110 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.276110 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3317990648 # number of integer regfile reads -system.cpu.int_regfile_writes 1931970641 # number of integer regfile writes -system.cpu.fp_regfile_reads 30869 # number of floating regfile reads -system.cpu.fp_regfile_writes 545 # number of floating regfile writes +system.cpu.cpi 0.782641 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.782641 # CPI: Total CPI of All Threads +system.cpu.ipc 1.277725 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.277725 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3354502671 # number of integer regfile reads +system.cpu.int_regfile_writes 1955490145 # number of integer regfile writes +system.cpu.fp_regfile_reads 31250 # number of floating regfile reads +system.cpu.fp_regfile_writes 519 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1214348707 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725127 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883613 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1924 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085799 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087723 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825949632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826011200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826011200 # Total data (bytes) +system.cpu.toL2Bus.throughput 1216162152 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7299986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7299986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883584 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22091005 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22092937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826137664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 826199488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 826199488 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178394945 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10180553427 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1603000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1609000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14072846750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14076007750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 772.655537 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391068098 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 962 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 406515.694387 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 775.530288 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 400044658 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 414124.904762 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 772.655537 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377273 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377273 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 961 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 902 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.469238 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 782140126 # Number of tag accesses -system.cpu.icache.tags.data_accesses 782140126 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 391068098 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391068098 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391068098 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391068098 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391068098 # number of overall hits -system.cpu.icache.overall_hits::total 391068098 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses -system.cpu.icache.overall_misses::total 1484 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 102456750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 102456750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 102456750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 102456750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 102456750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 102456750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391069582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391069582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391069582 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391069582 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391069582 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391069582 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 775.530288 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.378677 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.378677 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 912 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 800093342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 800093342 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 400044658 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 400044658 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 400044658 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 400044658 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 400044658 # number of overall hits +system.cpu.icache.overall_hits::total 400044658 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1530 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1530 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1530 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1530 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1530 # number of overall misses +system.cpu.icache.overall_misses::total 1530 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 107584749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 107584749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 107584749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 107584749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 107584749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 107584749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 400046188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 400046188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 400046188 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 400046188 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 400046188 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 400046188 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69040.936658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69040.936658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69040.936658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69040.936658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69040.936658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69040.936658 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70316.829412 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70316.829412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70316.829412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70316.829412 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 203.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48.833333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 522 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 522 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 522 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 522 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 522 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 522 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 71417000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 71417000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 71417000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 71417000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 71417000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 71417000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 564 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 564 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 564 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 564 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 564 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73366499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 73366499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73366499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 73366499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73366499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 73366499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74238.045738 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74238.045738 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74238.045738 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74238.045738 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74238.045738 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74238.045738 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75948.756729 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75948.756729 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75948.756729 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75948.756729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75948.756729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75948.756729 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933800 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31420.392793 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058700 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963581 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613357 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28339083250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14569.495652 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.490666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16824.406475 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.444626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000808 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513440 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958874 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29781 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 975 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17306 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10757 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908844 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107098594 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107098594 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6106335 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106335 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725127 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725127 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108456 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108456 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214791 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214791 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214791 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214791 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 962 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190388 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191350 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775157 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775157 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 962 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965545 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966507 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 962 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965545 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966507 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 70450000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 97815753000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 97886203000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63988346750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 63988346750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 70450000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 161804099750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 161874549750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 70450000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 161804099750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 161874549750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296723 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297685 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725127 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725127 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883613 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28109033750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14558.709173 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.630498 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16838.516639 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.444297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000813 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.513871 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 973 # 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average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82548.885903 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82548.885903 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73232.848233 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82320.221491 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82315.776018 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73232.848233 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82320.221491 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82315.776018 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214085 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214167 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74938.923395 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82197.835594 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82191.952424 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82493.114196 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82493.114196 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74938.923395 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82314.232610 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82310.610243 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74938.923395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82314.232610 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82310.610243 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -831,188 +829,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019732 # number of writebacks -system.cpu.l2cache.writebacks::total 1019732 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191350 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775157 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775157 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58345500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137137860250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 137196205750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58345500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137137860250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 137196205750 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019779 # number of writebacks +system.cpu.l2cache.writebacks::total 1019779 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190927 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191893 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54243912498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54243912498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 60233500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137188533248 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 137248766748 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 60233500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137188533248 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 137248766748 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163250 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411527 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411527 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163163 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214186 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214085 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69770.908450 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69766.446674 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60650.207900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69770.908450 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69766.446674 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214167 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62353.519669 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69647.107463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69641.196190 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69998.648259 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69998.648259 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176240 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.503872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694248122 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180336 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.623389 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5175532250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.503872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997926 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997926 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9178508 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.552800 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 699314315 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9182604 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 76.156427 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5143328250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.552800 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997938 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997938 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 694 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2982 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 755 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2929 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1430846728 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1430846728 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 538710092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538710092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155538028 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155538028 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694248120 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694248120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694248120 # number of overall hits -system.cpu.dcache.overall_hits::total 694248120 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11394599 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11394599 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5190474 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5190474 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1441348176 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1441348176 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 543788004 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 543788004 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155526308 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155526308 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 699314312 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 699314312 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 699314312 # number of overall hits +system.cpu.dcache.overall_hits::total 699314312 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11566276 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11566276 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5202194 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5202194 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16585073 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16585073 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16585073 # number of overall misses -system.cpu.dcache.overall_misses::total 16585073 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 331603001250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 331603001250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 288972510585 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 288972510585 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 129500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 620575511835 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 620575511835 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 620575511835 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 620575511835 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550104691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550104691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16768470 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16768470 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16768470 # number of overall misses +system.cpu.dcache.overall_misses::total 16768470 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 334833749250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 334833749250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 287624135124 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 287624135124 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 622457884374 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 622457884374 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 622457884374 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 622457884374 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 555354280 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 555354280 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710833193 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710833193 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710833193 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710833193 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032293 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032293 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023332 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023332 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023332 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29101.770168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 29101.770168 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55673.626452 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55673.626452 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 129500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 129500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37417.713617 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37417.713617 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37417.713617 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37417.713617 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11561530 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8659652 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 743678 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.546419 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.949290 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 716082782 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 716082782 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 716082782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 716082782 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020827 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020827 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032366 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032366 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023417 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023417 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023417 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023417 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28949.140523 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28949.140523 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55289.005970 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55289.005970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37120.732206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37120.732206 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11998793 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8384809 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 779484 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65137 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.393251 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.725747 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725127 # number of writebacks -system.cpu.dcache.writebacks::total 3725127 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097867 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4097867 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3306871 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3306871 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7404738 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7404738 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7404738 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7404738 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296732 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296732 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883603 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883603 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725797 # number of writebacks +system.cpu.dcache.writebacks::total 3725797 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4267247 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4267247 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3318620 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3318620 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7585867 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7585867 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7585867 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7585867 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7299029 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7299029 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883574 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883574 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180335 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180335 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180335 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180335 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167014367250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 167014367250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77391574454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77391574454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244405941704 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 244405941704 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244405941704 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 244405941704 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9182603 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9182603 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9182603 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9182603 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167129067750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 167129067750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77336919371 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77336919371 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244465987121 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 244465987121 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244465987121 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 244465987121 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013143 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013143 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22888.927159 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22888.927159 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41086.988317 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41086.988317 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 127500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 127500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.769398 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.769398 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.769398 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.769398 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012823 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012823 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22897.438515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22897.438515 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41058.604213 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41058.604213 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 56ff7911f..25fa7870b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,7 +699,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index c3788cdfe..288998877 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:05:55 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:45:58 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5017340 + 0: system.cpu.isa: ISA system set to: 0 0x5287000 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data @@ -25,4 +25,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 533761922000 because target called exit() +Exiting @ tick 523063504500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 8a3d4d605..80d2ee221 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.528386 # Number of seconds simulated -sim_ticks 528386107000 # Number of ticks simulated -final_tick 528386107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.523064 # Number of seconds simulated +sim_ticks 523063504500 # Number of ticks simulated +final_tick 523063504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123376 # Simulator instruction rate (inst/s) -host_op_rate 137635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42206077 # Simulator tick rate (ticks/s) -host_mem_usage 313484 # Number of bytes of host memory used -host_seconds 12519.20 # Real time elapsed on the host +host_inst_rate 149016 # Simulator instruction rate (inst/s) +host_op_rate 166238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50463882 # Simulator tick rate (ticks/s) +host_mem_usage 261252 # Number of bytes of host memory used +host_seconds 10365.11 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 47936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143742400 # Number of bytes read from this memory -system.physmem.bytes_read::total 143790336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70434560 # Number of bytes written to this memory -system.physmem.bytes_written::total 70434560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 749 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246724 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100540 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 272040461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 272131182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90722 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90722 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 133301310 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 133301310 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 133301310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 272040461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 405432492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246724 # Number of read requests accepted -system.physmem.writeReqs 1100540 # Number of write requests accepted -system.physmem.readBursts 2246724 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100540 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143697408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 92928 # Total number of bytes read from write queue -system.physmem.bytesWritten 70433344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143790336 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70434560 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1452 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143764288 # Number of bytes read from this memory +system.physmem.bytes_read::total 143812352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70447616 # Number of bytes written to this memory +system.physmem.bytes_written::total 70447616 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246317 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2247068 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100744 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 274850543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 274942432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 134682721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 134682721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 134682721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 274850543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 409625153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2247068 # Number of read requests accepted +system.physmem.writeReqs 1100744 # Number of write requests accepted +system.physmem.readBursts 2247068 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100744 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143722368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 89984 # Total number of bytes read from write queue +system.physmem.bytesWritten 70445760 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143812352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70447616 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1406 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139707 # Per bank write bursts -system.physmem.perBankRdBursts::1 136292 # Per bank write bursts -system.physmem.perBankRdBursts::2 133767 # Per bank write bursts -system.physmem.perBankRdBursts::3 136231 # Per bank write bursts -system.physmem.perBankRdBursts::4 134692 # Per bank write bursts -system.physmem.perBankRdBursts::5 135454 # Per bank write bursts -system.physmem.perBankRdBursts::6 136225 # Per bank write bursts -system.physmem.perBankRdBursts::7 136115 # Per bank write bursts -system.physmem.perBankRdBursts::8 143769 # Per bank write bursts -system.physmem.perBankRdBursts::9 146465 # Per bank write bursts -system.physmem.perBankRdBursts::10 144332 # Per bank write bursts -system.physmem.perBankRdBursts::11 146005 # Per bank write bursts -system.physmem.perBankRdBursts::12 145798 # Per bank write bursts -system.physmem.perBankRdBursts::13 145907 # Per bank write bursts -system.physmem.perBankRdBursts::14 142108 # Per bank write bursts -system.physmem.perBankRdBursts::15 142405 # Per bank write bursts -system.physmem.perBankWrBursts::0 69150 # Per bank write bursts -system.physmem.perBankWrBursts::1 67464 # Per bank write bursts -system.physmem.perBankWrBursts::2 65717 # Per bank write bursts -system.physmem.perBankWrBursts::3 66314 # Per bank write bursts -system.physmem.perBankWrBursts::4 66158 # Per bank write bursts -system.physmem.perBankWrBursts::5 66498 # Per bank write bursts -system.physmem.perBankWrBursts::6 67950 # Per bank write bursts -system.physmem.perBankWrBursts::7 68767 # Per bank write bursts -system.physmem.perBankWrBursts::8 70393 # Per bank write bursts -system.physmem.perBankWrBursts::9 70943 # Per bank write bursts -system.physmem.perBankWrBursts::10 70514 # Per bank write bursts -system.physmem.perBankWrBursts::11 70857 # Per bank write bursts -system.physmem.perBankWrBursts::12 70359 # Per bank write bursts -system.physmem.perBankWrBursts::13 70734 # Per bank write bursts -system.physmem.perBankWrBursts::14 69641 # Per bank write bursts -system.physmem.perBankWrBursts::15 69062 # Per bank write bursts +system.physmem.perBankRdBursts::0 139750 # Per bank write bursts +system.physmem.perBankRdBursts::1 136144 # Per bank write bursts +system.physmem.perBankRdBursts::2 133842 # Per bank write bursts +system.physmem.perBankRdBursts::3 136111 # Per bank write bursts +system.physmem.perBankRdBursts::4 134906 # Per bank write bursts +system.physmem.perBankRdBursts::5 135203 # Per bank write bursts +system.physmem.perBankRdBursts::6 136131 # Per bank write bursts +system.physmem.perBankRdBursts::7 136315 # Per bank write bursts +system.physmem.perBankRdBursts::8 143809 # Per bank write bursts +system.physmem.perBankRdBursts::9 146590 # Per bank write bursts +system.physmem.perBankRdBursts::10 144423 # Per bank write bursts +system.physmem.perBankRdBursts::11 146169 # Per bank write bursts +system.physmem.perBankRdBursts::12 145711 # Per bank write bursts +system.physmem.perBankRdBursts::13 146127 # Per bank write bursts +system.physmem.perBankRdBursts::14 142010 # Per bank write bursts +system.physmem.perBankRdBursts::15 142421 # Per bank write bursts +system.physmem.perBankWrBursts::0 69157 # Per bank write bursts +system.physmem.perBankWrBursts::1 67395 # Per bank write bursts +system.physmem.perBankWrBursts::2 65690 # Per bank write bursts +system.physmem.perBankWrBursts::3 66283 # Per bank write bursts +system.physmem.perBankWrBursts::4 66211 # Per bank write bursts +system.physmem.perBankWrBursts::5 66391 # Per bank write bursts +system.physmem.perBankWrBursts::6 67933 # Per bank write bursts +system.physmem.perBankWrBursts::7 68845 # Per bank write bursts +system.physmem.perBankWrBursts::8 70389 # Per bank write bursts +system.physmem.perBankWrBursts::9 71029 # Per bank write bursts +system.physmem.perBankWrBursts::10 70577 # Per bank write bursts +system.physmem.perBankWrBursts::11 70974 # Per bank write bursts +system.physmem.perBankWrBursts::12 70326 # Per bank write bursts +system.physmem.perBankWrBursts::13 70796 # Per bank write bursts +system.physmem.perBankWrBursts::14 69605 # Per bank write bursts +system.physmem.perBankWrBursts::15 69114 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 528386038000 # Total gap between requests +system.physmem.totGap 523063435500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246724 # Read request sizes (log2) +system.physmem.readPktSize::6 2247068 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100540 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1622160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 446140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 134185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42773 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100744 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1615066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 449330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 137330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43923 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 25689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 66484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 66961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 67677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 68712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 67405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 67796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 66570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 66892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 67424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 67533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 67827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 68851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 70296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 67618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 68033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see @@ -180,10 +180,10 @@ system.physmem.wrQLenPdf::47 1 # Wh system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -193,109 +193,110 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2026945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 105.641008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.595213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.312456 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1568777 77.40% 77.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 317859 15.68% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 67458 3.33% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23638 1.17% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14371 0.71% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6663 0.33% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4947 0.24% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3635 0.18% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19597 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2026945 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 34.467994 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 154.943879 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65024 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 2025915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 105.713545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.619710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.565498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1567130 77.35% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 318929 15.74% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 67085 3.31% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23530 1.16% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13977 0.69% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6837 0.34% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5148 0.25% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3637 0.18% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19642 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2025915 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65189 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 34.403642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.850371 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65147 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65065 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65065 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.914178 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.872771 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.215883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 38677 59.44% 59.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1561 2.40% 61.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18560 28.53% 90.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4956 7.62% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 979 1.50% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 233 0.36% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 49 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 12 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 7 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 65189 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65189 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.884981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.844479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.202215 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 39520 60.62% 60.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1483 2.27% 62.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18196 27.91% 90.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4786 7.34% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 898 1.38% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 207 0.32% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 54 0.08% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 10 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65065 # Writes before turning the bus around for reads -system.physmem.totQLat 49926066500 # Total ticks spent queuing -system.physmem.totMemAccLat 92024916500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11226360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22236.09 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65189 # Writes before turning the bus around for reads +system.physmem.totQLat 50228413500 # Total ticks spent queuing +system.physmem.totMemAccLat 92334576000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11228310000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22366.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40986.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 271.96 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 133.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 272.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 133.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41116.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 274.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 134.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 274.94 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 134.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.17 # Data bus utilization in percentage -system.physmem.busUtilRead 2.12 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.15 # Average write queue length when enqueuing -system.physmem.readRowHits 904882 # Number of row buffer hits during reads -system.physmem.writeRowHits 413955 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.61 # Row buffer hit rate for writes -system.physmem.avgGap 157856.10 # Average gap between requests -system.physmem.pageHitRate 39.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 96247983250 # Time in different power states -system.physmem.memoryStateTime::REF 17643860000 # Time in different power states +system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.busUtilRead 2.15 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing +system.physmem.readRowHits 905849 # Number of row buffer hits during reads +system.physmem.writeRowHits 414601 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.67 # Row buffer hit rate for writes +system.physmem.avgGap 156240.38 # Average gap between requests +system.physmem.pageHitRate 39.46 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 94741058000 # Time in different power states +system.physmem.memoryStateTime::REF 17466020000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 414492555250 # Time in different power states +system.physmem.memoryStateTime::ACT 410854630500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 405432371 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420231 # Transaction distribution -system.membus.trans_dist::ReadResp 1420230 # Transaction distribution -system.membus.trans_dist::Writeback 1100540 # Transaction distribution -system.membus.trans_dist::ReadExReq 826493 # Transaction distribution -system.membus.trans_dist::ReadExResp 826493 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593987 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214224832 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214224832 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214224832 # Total data (bytes) +system.membus.throughput 409625031 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1419612 # Transaction distribution +system.membus.trans_dist::ReadResp 1419611 # Transaction distribution +system.membus.trans_dist::Writeback 1100744 # Transaction distribution +system.membus.trans_dist::ReadExReq 827456 # Transaction distribution +system.membus.trans_dist::ReadExResp 827456 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5594879 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5594879 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214259904 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214259904 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214259904 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12921710000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21064187250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12872956000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 21034966500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 303120066 # Number of BP lookups -system.cpu.branchPred.condPredicted 249328718 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15217036 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 172898211 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161402010 # Number of BTB hits +system.cpu.branchPred.lookups 310041872 # Number of BP lookups +system.cpu.branchPred.condPredicted 254951905 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15242132 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 177250182 # Number of BTB lookups +system.cpu.branchPred.BTBHits 164623168 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.350885 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17552010 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.876163 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17905906 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -382,238 +383,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1056772215 # number of cpu cycles simulated +system.cpu.numCycles 1046127010 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 298543809 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2186558852 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303120066 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 178954020 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435169965 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87664150 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 162830797 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 66 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289028116 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5928471 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 966231390 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.503805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.207339 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 304406506 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2237155990 # Number of instructions fetch has processed +system.cpu.fetch.Branches 310041872 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 182529074 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 444747763 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93800973 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 104367517 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 295060555 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6266924 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 929205544 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.663579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.245143 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 531061564 54.96% 54.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25270109 2.62% 57.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39059321 4.04% 61.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48280752 5.00% 66.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43652123 4.52% 71.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46384495 4.80% 75.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38400203 3.97% 79.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18890593 1.96% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175232230 18.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 484458019 52.14% 52.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25667204 2.76% 54.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39962445 4.30% 59.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 49351933 5.31% 64.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 44527866 4.79% 69.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47023403 5.06% 74.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39036338 4.20% 78.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19508250 2.10% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 179670086 19.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 966231390 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286836 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.069092 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 330688304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 140707592 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 404837901 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20311495 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69686098 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46045464 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2366336890 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2408 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69686098 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354035761 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 69333450 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19564 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400161334 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72995183 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2304279831 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 149122 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5007808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60068670 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 28 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2280029311 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10640069170 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9754807461 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 523 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 929205544 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.296371 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.138513 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 323230837 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95973570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 424273226 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10044892 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 75683019 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46957126 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 712 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2419092576 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2470 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 75683019 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 338590369 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36235131 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20070 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 418478079 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 60198876 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2357219159 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 486871 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 10439342 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 39865193 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 9487400 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 108 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2332621614 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10887738442 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9980989966 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 478 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 573709381 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 838 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160867468 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624344109 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220690096 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85895596 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71104649 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2201067148 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 872 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018188753 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4009836 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 473419118 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1122820623 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 702 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 966231390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.088722 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.905985 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 626301684 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1665 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1662 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62763220 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 637377073 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 224726985 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 97022139 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 86012676 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2244793752 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1629 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2031991177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 6410093 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 517307509 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1273036014 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 929205544 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.186805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.944442 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 283676122 29.36% 29.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153451692 15.88% 45.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160814353 16.64% 61.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120202627 12.44% 74.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123594762 12.79% 87.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73761984 7.63% 94.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38320993 3.97% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9885308 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2523549 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 266904218 28.72% 28.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 128322549 13.81% 42.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158977129 17.11% 59.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 117185502 12.61% 72.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 128428514 13.82% 86.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 72785870 7.83% 93.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42669642 4.59% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10960354 1.18% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2971766 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 966231390 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 929205544 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 893685 3.74% 3.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5601 0.02% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18261914 76.52% 80.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4703701 19.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1285844 5.85% 5.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5675 0.03% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18368199 83.62% 89.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2306433 10.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236629707 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925874 0.05% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 25 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 11 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587570237 29.11% 90.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193062842 9.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1245462856 61.29% 61.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 947392 0.05% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 592199391 29.14% 90.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193381454 9.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018188753 # Type of FU issued -system.cpu.iq.rate 1.909767 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23864901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011825 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5030483281 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2674676202 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957157350 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 352 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 748 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 2031991177 # Type of FU issued +system.cpu.iq.rate 1.942394 # Inst issue rate +system.cpu.iq.fu_busy_cnt 21966151 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010810 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5021563817 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2762296727 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1969035141 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 660 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 139 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042053478 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64607819 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 2053957167 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 66315008 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138417340 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 267938 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192339 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45843051 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 151450304 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 182572 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 197144 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 49879940 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4440345 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4648682 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69686098 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 32530520 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1603302 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2201068109 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7883109 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624344109 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220690096 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 810 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 479479 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 96880 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192339 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8149711 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9614325 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17764036 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1987581145 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573715440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30607608 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 75683019 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13889446 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17402817 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2244795480 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7970371 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 637377073 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 224726985 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1567 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 551835 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16641279 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 197144 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8164855 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9718586 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17883441 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2000301565 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 577561658 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 31689612 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 763896054 # number of memory reference insts executed -system.cpu.iew.exec_branches 238343533 # Number of branches executed -system.cpu.iew.exec_stores 190180614 # Number of stores executed -system.cpu.iew.exec_rate 1.880804 # Inst execution rate -system.cpu.iew.wb_sent 1965589817 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957157489 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295200215 # num instructions producing a value -system.cpu.iew.wb_consumers 2058841803 # num instructions consuming a value +system.cpu.iew.exec_nop 99 # number of nop insts executed +system.cpu.iew.exec_refs 768256899 # number of memory reference insts executed +system.cpu.iew.exec_branches 239583236 # Number of branches executed +system.cpu.iew.exec_stores 190695241 # Number of stores executed +system.cpu.iew.exec_rate 1.912102 # Inst execution rate +system.cpu.iew.wb_sent 1977910575 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1969035280 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1321133911 # num instructions producing a value +system.cpu.iew.wb_consumers 2129107129 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.852015 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629092 # average fanout of values written-back +system.cpu.iew.wb_rate 1.882214 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.620511 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 478093326 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 522107871 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15216382 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 896545292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.921904 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.720119 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15241473 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 853522525 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.018780 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.777115 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 407981027 45.51% 45.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193272762 21.56% 67.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72814151 8.12% 75.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35242500 3.93% 79.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18951832 2.11% 81.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30763398 3.43% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19961065 2.23% 86.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11413875 1.27% 88.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106144682 11.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 375117315 43.95% 43.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 185477330 21.73% 65.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 70116011 8.21% 73.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 33059312 3.87% 77.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18836055 2.21% 79.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30683416 3.59% 83.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20461939 2.40% 85.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11515545 1.35% 87.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 108255602 12.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 896545292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 853522525 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -659,228 +662,227 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.15% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1723073853 # Class of committed instruction -system.cpu.commit.bw_lim_events 106144682 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 108255602 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2991567190 # The number of ROB reads -system.cpu.rob.rob_writes 4472170576 # The number of ROB writes -system.cpu.timesIdled 1153872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 90540825 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2990448048 # The number of ROB reads +system.cpu.rob.rob_writes 4566229463 # The number of ROB writes +system.cpu.timesIdled 1335234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 116921466 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.684188 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.684188 # CPI: Total CPI of All Threads -system.cpu.ipc 1.461586 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.461586 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9954183829 # number of integer regfile reads -system.cpu.int_regfile_writes 1937102211 # number of integer regfile writes -system.cpu.fp_regfile_reads 137 # number of floating regfile reads -system.cpu.fp_regfile_writes 142 # number of floating regfile writes -system.cpu.misc_regfile_reads 737626428 # number of misc regfile reads +system.cpu.cpi 0.677296 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.677296 # CPI: Total CPI of All Threads +system.cpu.ipc 1.476458 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.476458 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10016037678 # number of integer regfile reads +system.cpu.int_regfile_writes 1949973157 # number of integer regfile writes +system.cpu.fp_regfile_reads 144 # number of floating regfile reads +system.cpu.fp_regfile_writes 144 # number of floating regfile writes +system.cpu.misc_regfile_reads 741547581 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1621046225 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7708753 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7708752 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3781180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893479 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893479 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984087 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22985643 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856488512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856538304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856538304 # Total data (bytes) +system.cpu.toL2Bus.throughput 1637500473 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7708273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7708272 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3780671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1894131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1894131 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22983914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22985478 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856466688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856516736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10473041845 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10472370339 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1300248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1301749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14753489741 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14750464244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 20 # number of replacements -system.cpu.icache.tags.tagsinuse 629.404083 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289026911 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 778 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 371499.885604 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 21 # number of replacements +system.cpu.icache.tags.tagsinuse 633.135504 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 295059337 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 377313.730179 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 629.404083 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.307326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.307326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 758 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 633.135504 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.309148 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.309148 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 761 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.370117 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 578057010 # Number of tag accesses -system.cpu.icache.tags.data_accesses 578057010 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289026911 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289026911 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289026911 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289026911 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289026911 # number of overall hits -system.cpu.icache.overall_hits::total 289026911 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1205 # 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number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289028116 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289028116 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 732 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.371582 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 590121892 # Number of tag accesses +system.cpu.icache.tags.data_accesses 590121892 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 295059337 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 295059337 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 295059337 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 295059337 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 295059337 # number of overall hits +system.cpu.icache.overall_hits::total 295059337 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 350608925483 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 296498774019 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296498774019 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 225500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 647107699502 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 647107699502 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 647107699502 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 647107699502 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500587831 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500587831 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17264641 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17264641 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17264641 # number of overall misses +system.cpu.dcache.overall_misses::total 17264641 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 353287122740 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 353287122740 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 298200381062 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 298200381062 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 243250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 243250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 651487503802 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 651487503802 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 651487503802 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 651487503802 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 502485347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 502485347 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673173878 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673173878 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673173878 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673173878 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032625 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025465 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025465 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025465 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025465 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30456.000147 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30456.000147 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52657.598988 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52657.598988 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37748.350214 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37748.350214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37748.350214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37748.350214 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22019527 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3996591 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1208409 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.221916 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.361405 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 675071394 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 675071394 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 675071394 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 675071394 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023074 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023074 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032855 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032855 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025575 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025575 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025575 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025575 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30470.887920 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30470.887920 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52589.042564 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52589.042564 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 81083.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 81083.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37735.363498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37735.363498 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22798709 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4000734 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1307566 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.435991 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.425957 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781180 # number of writebacks -system.cpu.dcache.writebacks::total 3781180 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3804007 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3804007 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3737214 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3737214 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3780671 # number of writebacks +system.cpu.dcache.writebacks::total 3780671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3886759 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3886759 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3776260 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3776260 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7541221 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7541221 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7541221 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7541221 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707975 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707975 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893479 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893479 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601454 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601454 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601454 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601454 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191480901509 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 191480901509 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83841557570 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83841557570 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275322459079 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 275322459079 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275322459079 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 275322459079 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015398 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015398 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24841.920415 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24841.920415 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44279.106116 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44279.106116 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28675.079741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28675.079741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28675.079741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28675.079741 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 7663019 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7663019 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7663019 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7663019 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707492 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7707492 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894130 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1894130 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601622 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601622 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601622 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601622 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191674058756 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 191674058756 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84036609462 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84036609462 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275710668218 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 275710668218 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275710668218 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 275710668218 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015339 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015339 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24868.538139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24868.538139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.864715 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.864715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 78509c3e8..104ffdb52 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index c12c73ccb..2cc52ce3f 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:15:16 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 12:55:52 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23461709500 because target called exit() +122 123 124 Exiting @ tick 23058360500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index a6580fdc8..22a3b525f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023496 # Number of seconds simulated -sim_ticks 23495860500 # Number of ticks simulated -final_tick 23495860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023058 # Number of seconds simulated +sim_ticks 23058360500 # Number of ticks simulated +final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162171 # Simulator instruction rate (inst/s) -host_op_rate 162171 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45264552 # Simulator tick rate (ticks/s) -host_mem_usage 273204 # Number of bytes of host memory used -host_seconds 519.08 # Real time elapsed on the host +host_inst_rate 185322 # Simulator instruction rate (inst/s) +host_op_rate 185322 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50763012 # Simulator tick rate (ticks/s) +host_mem_usage 226392 # Number of bytes of host memory used +host_seconds 454.24 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 196416 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 334528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3069 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8345981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5891761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14237742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8345981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8345981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8345981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5891761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14237742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5227 # Number of read requests accepted +system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8518212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6003549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14521761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8518212 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8518212 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8518212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6003549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14521761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5232 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 469 # Per bank write bursts +system.physmem.perBankRdBursts::0 471 # Per bank write bursts system.physmem.perBankRdBursts::1 291 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 226 # Per bank write bursts -system.physmem.perBankRdBursts::6 220 # Per bank write bursts -system.physmem.perBankRdBursts::7 285 # Per bank write bursts -system.physmem.perBankRdBursts::8 236 # Per bank write bursts -system.physmem.perBankRdBursts::9 280 # Per bank write bursts +system.physmem.perBankRdBursts::5 225 # Per bank write bursts +system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::7 286 # Per bank write bursts +system.physmem.perBankRdBursts::8 240 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 254 # Per bank write bursts +system.physmem.perBankRdBursts::11 253 # Per bank write bursts system.physmem.perBankRdBursts::12 398 # Per bank write bursts -system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 491 # Per bank write bursts -system.physmem.perBankRdBursts::15 447 # Per bank write bursts +system.physmem.perBankRdBursts::15 448 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23495733500 # Total gap between requests +system.physmem.totGap 23058233500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5227 # Read request sizes (log2) +system.physmem.readPktSize::6 5232 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 383.188005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.923786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.572905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 252 29.07% 29.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197 22.72% 51.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 79 9.11% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.57% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 4.84% 72.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 4.73% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 51 5.88% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 24 2.77% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 124 14.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 867 # Bytes accessed per row activation -system.physmem.totQLat 41053500 # Total ticks spent queuing -system.physmem.totMemAccLat 139059750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7854.12 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.722158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.044875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.837953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 257 29.51% 29.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 22.27% 51.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 9.64% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 7.46% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.02% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 4.13% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 31 3.56% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 43 4.94% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 14.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 871 # Bytes accessed per row activation +system.physmem.totQLat 38517250 # Total ticks spent queuing +system.physmem.totMemAccLat 136617250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7361.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26604.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26111.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4351 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4495070.50 # Average gap between requests -system.physmem.pageHitRate 83.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 21787630000 # Time in different power states -system.physmem.memoryStateTime::REF 784420000 # Time in different power states +system.physmem.avgGap 4407154.72 # Average gap between requests +system.physmem.pageHitRate 83.20 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 21416461750 # Time in different power states +system.physmem.memoryStateTime::REF 769860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 919340000 # Time in different power states +system.physmem.memoryStateTime::ACT 869038750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 14237742 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3522 # Transaction distribution -system.membus.trans_dist::ReadResp 3522 # Transaction distribution -system.membus.trans_dist::ReadExReq 1705 # Transaction distribution -system.membus.trans_dist::ReadExResp 1705 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334528 # Total data (bytes) +system.membus.throughput 14521761 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3525 # Transaction distribution +system.membus.trans_dist::ReadResp 3525 # Transaction distribution +system.membus.trans_dist::ReadExReq 1707 # Transaction distribution +system.membus.trans_dist::ReadExResp 1707 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6755000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6496500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48973500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48985000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14867597 # Number of BP lookups -system.cpu.branchPred.condPredicted 10786733 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 927657 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8507235 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6975722 # Number of BTB hits +system.cpu.branchPred.lookups 15361032 # Number of BP lookups +system.cpu.branchPred.condPredicted 11166301 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 940671 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8650721 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7195754 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.997523 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1468896 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3134 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.180974 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1505004 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3205 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23141508 # DTB read hits -system.cpu.dtb.read_misses 194908 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23336416 # DTB read accesses -system.cpu.dtb.write_hits 7073051 # DTB write hits -system.cpu.dtb.write_misses 1111 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7074162 # DTB write accesses -system.cpu.dtb.data_hits 30214559 # DTB hits -system.cpu.dtb.data_misses 196019 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 30410578 # DTB accesses -system.cpu.itb.fetch_hits 14761442 # ITB hits -system.cpu.itb.fetch_misses 106 # ITB misses +system.cpu.dtb.read_hits 23573955 # DTB read hits +system.cpu.dtb.read_misses 207074 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23781029 # DTB read accesses +system.cpu.dtb.write_hits 7120317 # DTB write hits +system.cpu.dtb.write_misses 1134 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7121451 # DTB write accesses +system.cpu.dtb.data_hits 30694272 # DTB hits +system.cpu.dtb.data_misses 208208 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30902480 # DTB accesses +system.cpu.itb.fetch_hits 15234213 # ITB hits +system.cpu.itb.fetch_misses 102 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14761548 # ITB accesses +system.cpu.itb.fetch_accesses 15234315 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,238 +285,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46991722 # number of cpu cycles simulated +system.cpu.numCycles 46116722 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15493602 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127144789 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14867597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8444618 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22164191 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4494518 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5543985 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2326 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15940932 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 131589057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15361032 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8700758 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22892353 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5007718 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2994752 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2134 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14761442 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 326314 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46736650 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720451 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375825 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 15234213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 364576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 45860852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.869311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.407633 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24572459 52.58% 52.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2364267 5.06% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1190852 2.55% 60.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1750659 3.75% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2760354 5.91% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1155374 2.47% 72.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1219764 2.61% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 773397 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10949524 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22968499 50.08% 50.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2435887 5.31% 55.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1214898 2.65% 58.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1783514 3.89% 61.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2844070 6.20% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1193047 2.60% 70.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1264346 2.76% 73.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 807487 1.76% 75.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11349104 24.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46736650 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316388 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17320813 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4244089 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20558459 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1092640 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3520649 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2518881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12242 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124135665 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32164 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3520649 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18467014 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 956444 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7682 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20482522 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3302339 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121292511 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 405307 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2418029 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89077183 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157604141 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150534696 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7069444 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 45860852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.333090 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.853391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16942268 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2554020 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21969696 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 376134 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4018734 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2597948 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12434 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 128314772 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 36360 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4018734 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17696753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 830389 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7936 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21575239 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1731801 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 125347310 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9609 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 982853 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 675750 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22720 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 92019426 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 162776933 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 155390791 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7386141 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20649822 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 718 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 707 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8775432 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25394818 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8253633 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2570331 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 907077 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105549830 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2075 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96657653 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 179218 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20902238 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15662437 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1686 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46736650 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.068134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876130 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 23592065 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 733 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3333773 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26203423 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8541215 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2901793 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1268500 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 108868755 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1841 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 97966771 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 305092 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24205687 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18927840 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1452 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 45860852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.136174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.932064 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12165151 26.03% 26.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9350062 20.01% 46.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8404811 17.98% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6298333 13.48% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4922419 10.53% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2869013 6.14% 94.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1725015 3.69% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796629 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205217 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12004778 26.18% 26.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8735781 19.05% 45.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7795942 17.00% 62.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6187579 13.49% 75.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4939987 10.77% 86.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3238381 7.06% 93.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1831298 3.99% 97.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 880120 1.92% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 246986 0.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46736650 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 45860852 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189767 12.10% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 186 0.01% 12.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7209 0.46% 12.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5897 0.38% 12.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843167 53.74% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445094 28.37% 95.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77619 4.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202355 11.05% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 107 0.01% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 8618 0.47% 11.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 9498 0.52% 12.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 955023 52.14% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 532552 29.07% 93.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 123630 6.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58783696 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479813 0.50% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802274 2.90% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115457 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387860 2.47% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311147 0.32% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760157 0.79% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23859982 24.69% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7156941 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59518834 60.75% 60.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 484423 0.49% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2816502 2.87% 64.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115449 0.12% 64.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2407923 2.46% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 312382 0.32% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763359 0.78% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24335343 24.84% 92.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7212230 7.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96657653 # Type of FU issued -system.cpu.iq.rate 2.056908 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568939 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226667825 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117702286 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87133167 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15132288 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8786528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7070448 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90230128 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7996457 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520956 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 97966771 # Type of FU issued +system.cpu.iq.rate 2.124322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1831783 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228533724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 123769088 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 88239146 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15397545 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9344200 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7119957 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91612691 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8185856 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1667830 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5398620 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18484 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34785 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1752530 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6207225 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16318 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37199 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2040112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10530 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2127 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 40236 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2728 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3520649 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133897 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18217 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115793083 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 374761 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25394818 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8253633 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2932 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 43 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34785 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 541104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495336 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1036440 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95417746 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23336859 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1239907 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4018734 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 14986 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 580703 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119442937 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 327587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26203423 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8541215 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 22416 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 558101 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37199 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 549687 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 504581 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1054268 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 96742235 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23781507 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1224536 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10241178 # number of nop insts executed -system.cpu.iew.exec_refs 30411225 # number of memory reference insts executed -system.cpu.iew.exec_branches 12030179 # Number of branches executed -system.cpu.iew.exec_stores 7074366 # Number of stores executed -system.cpu.iew.exec_rate 2.030522 # Inst execution rate -system.cpu.iew.wb_sent 94727613 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94203615 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64511907 # num instructions producing a value -system.cpu.iew.wb_consumers 89904657 # num instructions consuming a value +system.cpu.iew.exec_nop 10572341 # number of nop insts executed +system.cpu.iew.exec_refs 30903185 # number of memory reference insts executed +system.cpu.iew.exec_branches 12219901 # Number of branches executed +system.cpu.iew.exec_stores 7121678 # Number of stores executed +system.cpu.iew.exec_rate 2.097769 # Inst execution rate +system.cpu.iew.wb_sent 95961828 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 95359103 # cumulative count of insts written-back +system.cpu.iew.wb_producers 65705546 # num instructions producing a value +system.cpu.iew.wb_consumers 92226364 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004685 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717559 # average fanout of values written-back +system.cpu.iew.wb_rate 2.067777 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.712438 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23891142 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 27540320 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 915882 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43216001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.126598 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.743951 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 928822 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41842118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.196425 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.812600 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16755601 38.77% 38.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9919008 22.95% 61.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4484606 10.38% 72.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2269127 5.25% 77.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1610437 3.73% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1128955 2.61% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722092 1.67% 85.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 821021 1.90% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5505154 12.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16239554 38.81% 38.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9401519 22.47% 61.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4137637 9.89% 71.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2136234 5.11% 76.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1534088 3.67% 79.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1088589 2.60% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 699410 1.67% 84.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 798893 1.91% 86.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5806194 13.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43216001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41842118 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -562,228 +563,229 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 5505154 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5806194 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153504004 # The number of ROB reads -system.cpu.rob.rob_writes 235133069 # The number of ROB writes -system.cpu.timesIdled 5418 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 255072 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 155478259 # The number of ROB reads +system.cpu.rob.rob_writes 242937786 # The number of ROB writes +system.cpu.timesIdled 5286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 255870 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.558231 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558231 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129151691 # number of integer regfile reads -system.cpu.int_regfile_writes 70572840 # number of integer regfile writes -system.cpu.fp_regfile_reads 6193374 # number of floating regfile reads -system.cpu.fp_regfile_writes 6052358 # number of floating regfile writes -system.cpu.misc_regfile_reads 714605 # number of misc regfile reads +system.cpu.cpi 0.547837 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads +system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 130779467 # number of integer regfile reads +system.cpu.int_regfile_writes 71543363 # number of integer regfile writes +system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads +system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes +system.cpu.misc_regfile_reads 718857 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37684936 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 11995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 11995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4597 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27561 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 885440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 885440 # Total data (bytes) +system.cpu.toL2Bus.throughput 37986395 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 11847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1732 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 875904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 875904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7026500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17802750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17583000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3545000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3542750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9548 # number of replacements -system.cpu.icache.tags.tagsinuse 1597.278061 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14747183 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11482 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1284.374064 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9401 # number of replacements +system.cpu.icache.tags.tagsinuse 1598.407560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15220036 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11337 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1342.510011 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1597.278061 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 29534364 # Number of tag accesses -system.cpu.icache.tags.data_accesses 29534364 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14747183 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14747183 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14747183 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14747183 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14747183 # number of overall hits -system.cpu.icache.overall_hits::total 14747183 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14258 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14258 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14258 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14258 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14258 # number of overall misses -system.cpu.icache.overall_misses::total 14258 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 414157250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 414157250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 414157250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 414157250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 414157250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 414157250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14761441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14761441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14761441 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14761441 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14761441 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14761441 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000966 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000966 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000966 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000966 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000966 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000966 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29047.359377 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29047.359377 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29047.359377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29047.359377 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1598.407560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.780472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.780472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 931 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30479761 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30479761 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15220036 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15220036 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15220036 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15220036 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15220036 # number of overall hits +system.cpu.icache.overall_hits::total 15220036 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14176 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14176 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14176 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14176 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14176 # number of overall misses +system.cpu.icache.overall_misses::total 14176 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 411369250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 411369250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 411369250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 411369250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 411369250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 411369250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15234212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15234212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15234212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15234212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15234212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15234212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000931 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000931 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000931 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000931 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000931 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000931 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29018.711202 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29018.711202 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29018.711202 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29018.711202 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 61.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2776 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2776 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2776 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2776 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2776 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2776 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11482 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11482 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11482 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11482 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11482 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11482 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306274750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306274750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306274750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306274750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306274750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306274750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000778 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000778 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000778 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26674.338094 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26674.338094 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2839 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2839 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2839 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2839 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2839 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2839 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11337 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11337 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11337 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11337 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11337 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11337 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 302662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 302662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302662500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 302662500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000744 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000744 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000744 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26696.877481 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26696.877481 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.001155 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8488 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.365004 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2409.556828 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8337 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.321637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.673690 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.868133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 379.459331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061397 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 17.688406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2013.956930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 377.911492 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061461 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011533 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116000 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116000 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8418 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8473 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8418 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 81 # 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Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114811 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114811 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8268 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8322 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8268 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8347 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8268 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2242 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12647.512935 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1456.991941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355711 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1456.621503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355620 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355620 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56220748 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56220748 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21606921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21606921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492872 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492872 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 225 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 225 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28099793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28099793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28099793 # number of overall hits -system.cpu.dcache.overall_hits::total 28099793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1002 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1002 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8231 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8231 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 56732342 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56732342 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21862715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21862715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492763 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 246 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 246 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28355478 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28355478 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28355478 # number of overall hits +system.cpu.dcache.overall_hits::total 28355478 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 985 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 985 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8340 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8340 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9233 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9233 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9233 # number of overall misses -system.cpu.dcache.overall_misses::total 9233 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62924000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62924000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 508720531 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 508720531 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9325 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9325 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9325 # number of overall misses +system.cpu.dcache.overall_misses::total 9325 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 61174750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 61174750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 507348010 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 507348010 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 571644531 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 571644531 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 571644531 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 571644531 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21607923 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21607923 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 568522760 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 568522760 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 568522760 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 568522760 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21863700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21863700 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 226 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 226 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28109026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28109026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28109026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28109026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001266 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001266 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004425 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004425 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62798.403194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62798.403194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61805.434455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61805.434455 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28364803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28364803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28364803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28364803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001283 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000329 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000329 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000329 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000329 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62106.345178 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62106.345178 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60833.094724 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60833.094724 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61913.195170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61913.195170 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23691 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60967.588204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60967.588204 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 27950 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.069971 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.942857 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109 # number of writebacks -system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 490 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6500 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6500 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6990 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6990 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6990 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6990 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 476 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 476 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6608 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6608 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7084 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7084 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7084 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7084 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36779750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36779750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124808747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124808747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2241 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2241 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2241 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2241 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36463750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36463750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124994997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124994997 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161588497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161588497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161588497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161588497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161458747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161458747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161458747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161458747 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004425 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004425 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71835.449219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71835.449219 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72102.106875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72102.106875 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004049 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004049 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71638.015717 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71638.015717 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72168.012125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72168.012125 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 03d137b4d..289d5c40d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,7 +699,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index ce396dba2..8dd189a74 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:25:13 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:53:28 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5949040 + 0: system.cpu.isa: ISA system set to: 0 0x4f074c0 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 @@ -22,4 +22,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 74219931000 because target called exit() +122 123 124 Exiting @ tick 74056845500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 59645b4d8..eafc895c2 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074209 # Number of seconds simulated -sim_ticks 74208571000 # Number of ticks simulated -final_tick 74208571000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074057 # Number of seconds simulated +sim_ticks 74056845500 # Number of ticks simulated +final_tick 74056845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109569 # Simulator instruction rate (inst/s) -host_op_rate 119969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47190079 # Simulator tick rate (ticks/s) -host_mem_usage 316768 # Number of bytes of host memory used -host_seconds 1572.55 # Real time elapsed on the host +host_inst_rate 115398 # Simulator instruction rate (inst/s) +host_op_rate 126351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49598898 # Simulator tick rate (ticks/s) +host_mem_usage 265028 # Number of bytes of host memory used +host_seconds 1493.11 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory -system.physmem.bytes_read::total 243264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3801 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1771440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1506672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3278112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1771440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1771440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1771440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1506672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3278112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3802 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 131840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::total 244032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131840 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2060 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3813 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1780254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1514944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3295198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1780254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1780254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1780254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1514944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3295198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3814 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3802 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3814 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 243328 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 244096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 243328 # Total read bytes from the system interface side +system.physmem.bytesReadSys 244096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 306 # Per bank write bursts -system.physmem.perBankRdBursts::1 216 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 307 # Per bank write bursts +system.physmem.perBankRdBursts::1 215 # Per bank write bursts system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 308 # Per bank write bursts -system.physmem.perBankRdBursts::4 298 # Per bank write bursts +system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::4 299 # Per bank write bursts system.physmem.perBankRdBursts::5 300 # Per bank write bursts system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::7 223 # Per bank write bursts system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::9 213 # Per bank write bursts system.physmem.perBankRdBursts::10 289 # Per bank write bursts -system.physmem.perBankRdBursts::11 192 # Per bank write bursts +system.physmem.perBankRdBursts::11 196 # Per bank write bursts system.physmem.perBankRdBursts::12 190 # Per bank write bursts -system.physmem.perBankRdBursts::13 208 # Per bank write bursts -system.physmem.perBankRdBursts::14 218 # Per bank write bursts -system.physmem.perBankRdBursts::15 200 # Per bank write bursts +system.physmem.perBankRdBursts::13 207 # Per bank write bursts +system.physmem.perBankRdBursts::14 219 # Per bank write bursts +system.physmem.perBankRdBursts::15 201 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74208552500 # Total gap between requests +system.physmem.totGap 74056827000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3802 # Read request sizes (log2) +system.physmem.readPktSize::6 3814 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,72 +186,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.649673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.993895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 311.806865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 244 31.90% 31.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 208 27.19% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 73 9.54% 68.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 46 6.01% 74.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29 3.79% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 70 9.15% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12 1.57% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15 1.96% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 68 8.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 765 # Bytes accessed per row activation -system.physmem.totQLat 30320750 # Total ticks spent queuing -system.physmem.totMemAccLat 101608250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19010000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7974.95 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.641290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.687696 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 311.293227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 258 33.29% 33.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189 24.39% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 11.23% 68.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 6.58% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41 5.29% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 4.00% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 5.55% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10 1.29% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 65 8.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 775 # Bytes accessed per row activation +system.physmem.totQLat 30109750 # Total ticks spent queuing +system.physmem.totMemAccLat 101622250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19070000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7894.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26724.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26644.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3030 # Number of row buffer hits during reads +system.physmem.readRowHits 3033 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.69 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19518293.66 # Average gap between requests -system.physmem.pageHitRate 79.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 70857777500 # Time in different power states -system.physmem.memoryStateTime::REF 2477800000 # Time in different power states +system.physmem.avgGap 19417101.99 # Average gap between requests +system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 70721348250 # Time in different power states +system.physmem.memoryStateTime::REF 2472860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 867720500 # Time in different power states +system.physmem.memoryStateTime::ACT 861203250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 3278112 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2731 # Transaction distribution -system.membus.trans_dist::ReadResp 2730 # Transaction distribution -system.membus.trans_dist::ReadExReq 1071 # Transaction distribution -system.membus.trans_dist::ReadExResp 1071 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7603 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7603 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243264 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 243264 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 243264 # Total data (bytes) +system.membus.throughput 3295198 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2737 # Transaction distribution +system.membus.trans_dist::ReadResp 2736 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 1077 # Transaction distribution +system.membus.trans_dist::ReadExResp 1077 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7631 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 244032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 244032 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 244032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4541000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35718000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35636248 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94830067 # Number of BP lookups -system.cpu.branchPred.condPredicted 74823235 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6280063 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44671635 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43055955 # Number of BTB hits +system.cpu.branchPred.lookups 95688557 # Number of BP lookups +system.cpu.branchPred.condPredicted 75485372 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6295432 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 45268261 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43530249 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.383208 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4354004 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88575 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.160639 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4420185 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 89338 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,240 +339,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148417143 # number of cpu cycles simulated +system.cpu.numCycles 148113692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39654365 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380231735 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94830067 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47409959 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80369944 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27285630 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7202415 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5794 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 40192835 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 385592009 # Number of instructions fetch has processed +system.cpu.fetch.Branches 95688557 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47950434 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81543775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28012255 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4465673 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36851066 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1832690 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148222429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37392446 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1863811 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 147907378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.849949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.160123 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68020985 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5256509 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10534999 7.11% 56.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10284828 6.94% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8666572 5.85% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6537070 4.41% 73.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6246175 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8016813 5.41% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24658478 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66535735 44.98% 44.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5361707 3.63% 48.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10726789 7.25% 55.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10405351 7.04% 62.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8725871 5.90% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6634741 4.49% 73.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6328592 4.28% 77.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8060301 5.45% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25128291 16.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148222429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638943 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561913 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45507597 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5871716 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74805608 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1201041 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20836467 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14340186 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164591 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392845308 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 733522 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20836467 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50894479 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722812 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 602318 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70557272 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4609081 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371354915 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 338748 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3656059 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631764461 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1588652531 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506975247 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3198470 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 147907378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.646048 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.603352 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45234948 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3964725 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76674416 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 488435 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21544854 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14463585 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165860 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 398867240 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 776962 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21544854 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 49978288 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80802 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 634035 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72417632 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3251767 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 377266574 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 64 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 883323 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2242172 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19804 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 7460 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 639899653 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1616068029 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1531504010 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3330597 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333720322 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25119 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25116 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13019783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012506 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16421309 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5620383 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3639856 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329245944 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47173 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249482695 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 793526 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139565421 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362544222 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1957 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148222429 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683164 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761970 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 341855514 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25341 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25337 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6011835 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44415560 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16956234 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6645157 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4213095 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334591306 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 251099486 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1072213 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 144899766 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 380484892 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2104 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147907378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.697681 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.790678 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56049781 37.81% 37.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22646407 15.28% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24808421 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20317592 13.71% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12547069 8.47% 92.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6521251 4.40% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4032352 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1118421 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181135 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56583019 38.26% 38.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 21897324 14.80% 53.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24121591 16.31% 69.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20330444 13.75% 83.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12466477 8.43% 91.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6673732 4.51% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4321605 2.92% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1302038 0.88% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 211148 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148222429 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147907378 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 964061 38.35% 38.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5595 0.22% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 96 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168003 46.46% 85.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 376162 14.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1040958 39.39% 39.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5589 0.21% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 97 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 356 0.01% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 45 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1222208 46.25% 85.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373303 14.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194908316 78.12% 78.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 978999 0.39% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164299 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255151 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76428 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465968 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206368 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71868 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38371220 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13950685 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 195834645 77.99% 77.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 981127 0.39% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33203 0.01% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 259909 0.10% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76654 0.03% 78.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 470113 0.19% 78.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206582 0.08% 78.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71910 0.03% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38922233 15.50% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14078361 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249482695 # Type of FU issued -system.cpu.iq.rate 1.680956 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2513965 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010077 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646755779 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466684925 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237894917 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3739531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2191886 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842592 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250120414 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1876246 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2009109 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 251099486 # Type of FU issued +system.cpu.iq.rate 1.695316 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2642556 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010524 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 650051417 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477257433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 239511768 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3769702 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2301296 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1862518 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 251853224 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1888818 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2264941 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163022 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11141 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18733 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3776675 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14566076 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14946 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20827 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4311600 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 115 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20836467 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18579 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 909 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329310121 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 781513 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012506 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16421309 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24765 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 190 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 272 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18733 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3888765 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3761308 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650073 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242977304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36862847 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6505391 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21544854 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1947 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2849 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334655682 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 756589 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44415560 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16956234 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2632 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20827 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3907560 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3770350 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7677910 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 244706645 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37396904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6392841 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17004 # number of nop insts executed -system.cpu.iew.exec_refs 50511963 # number of memory reference insts executed -system.cpu.iew.exec_branches 53432662 # Number of branches executed -system.cpu.iew.exec_stores 13649116 # Number of stores executed -system.cpu.iew.exec_rate 1.637124 # Inst execution rate -system.cpu.iew.wb_sent 240796428 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239737509 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148472463 # num instructions producing a value -system.cpu.iew.wb_consumers 267293668 # num instructions consuming a value +system.cpu.iew.exec_nop 17056 # number of nop insts executed +system.cpu.iew.exec_refs 51162912 # number of memory reference insts executed +system.cpu.iew.exec_branches 53733408 # Number of branches executed +system.cpu.iew.exec_stores 13766008 # Number of stores executed +system.cpu.iew.exec_rate 1.652154 # Inst execution rate +system.cpu.iew.wb_sent 242463171 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 241374286 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150213875 # num instructions producing a value +system.cpu.iew.wb_consumers 271770811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615295 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555466 # average fanout of values written-back +system.cpu.iew.wb_rate 1.629655 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552723 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140639228 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 145985060 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6126680 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127385962 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481096 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6141058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126362524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.493092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.207919 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57702305 45.30% 45.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31675528 24.87% 70.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13782422 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7634808 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4379316 3.44% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1319569 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1705598 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1313930 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7872486 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57333838 45.37% 45.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31277146 24.75% 70.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13531640 10.71% 80.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7550408 5.98% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4276360 3.38% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1325331 1.05% 91.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1692872 1.34% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1209518 0.96% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 8165411 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127385962 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126362524 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -616,229 +619,237 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction -system.cpu.commit.bw_lim_events 7872486 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 8165411 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448818394 # The number of ROB reads -system.cpu.rob.rob_writes 679565858 # The number of ROB writes -system.cpu.timesIdled 2789 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194714 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 452847863 # The number of ROB reads +system.cpu.rob.rob_writes 690972129 # The number of ROB writes +system.cpu.timesIdled 2844 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 206314 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.861373 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861373 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160937 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160937 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079497274 # number of integer regfile reads -system.cpu.int_regfile_writes 384888160 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912753 # number of floating regfile reads -system.cpu.fp_regfile_writes 2499155 # number of floating regfile writes -system.cpu.misc_regfile_reads 64874393 # number of misc regfile reads +system.cpu.cpi 0.859612 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.859612 # CPI: Total CPI of All Threads +system.cpu.ipc 1.163316 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.163316 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1087499674 # number of integer regfile reads +system.cpu.int_regfile_writes 386673292 # number of integer regfile writes +system.cpu.fp_regfile_reads 2922602 # number of floating regfile reads +system.cpu.fp_regfile_writes 2532629 # number of floating regfile writes +system.cpu.misc_regfile_reads 65625361 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5170292 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1081 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8239 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3733 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.throughput 5184342 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1084 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1084 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11985 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 383808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383808 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6548996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6552747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3099487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3102991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2388 # number of replacements -system.cpu.icache.tags.tagsinuse 1346.753946 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845676 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4119 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8945.296431 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2387 # number of replacements +system.cpu.icache.tags.tagsinuse 1349.069671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37387126 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9072.343121 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1346.753946 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.657595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.657595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1349.069671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658725 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658725 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1734 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73706251 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73706251 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36845676 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845676 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845676 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845676 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845676 # number of overall hits -system.cpu.icache.overall_hits::total 36845676 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5390 # number of overall misses -system.cpu.icache.overall_misses::total 5390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228751995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228751995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228751995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228751995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228751995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228751995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36851066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36851066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36851066 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36851066 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36851066 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36851066 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42440.073284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42440.073284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1596 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 547 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.846680 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 74789015 # Number of tag accesses +system.cpu.icache.tags.data_accesses 74789015 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 37387126 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37387126 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37387126 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37387126 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37387126 # number of overall hits +system.cpu.icache.overall_hits::total 37387126 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5320 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5320 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5320 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5320 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5320 # number of overall misses +system.cpu.icache.overall_misses::total 5320 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 224799997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 224799997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 224799997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 224799997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 224799997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 224799997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37392446 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37392446 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37392446 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37392446 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37392446 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37392446 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42255.638534 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42255.638534 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42255.638534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42255.638534 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1071 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1270 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1270 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1270 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1270 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1270 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1270 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4120 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4120 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4120 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4120 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4120 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4120 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167326504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 167326504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167326504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 167326504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167326504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 167326504 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40613.229126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40613.229126 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1196 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1196 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1196 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1196 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1196 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1196 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168596253 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168596253 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168596253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168596253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168596253 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168596253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000110 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000110 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000110 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40881.729631 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40881.729631 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1966.490721 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2149 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2739 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.784593 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1967.769315 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2148 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2745 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.782514 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.023907 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1424.627361 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839452 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 4.017679 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1427.875766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 535.875870 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043476 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.060013 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2739 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 607 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1969 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083588 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51788 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51788 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2061 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2148 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 19 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 19 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2061 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2158 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2061 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2158 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2059 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2748 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2059 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1760 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56257.195915 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 60 # number of replacements -system.cpu.dcache.tags.tagsinuse 1407.063073 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46801066 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1857 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25202.512655 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 56 # number of replacements +system.cpu.dcache.tags.tagsinuse 1410.171492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 47073011 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1860 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25308.070430 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1407.063073 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.343521 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.343521 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1410.171492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.344280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.344280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1804 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93623269 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 93623269 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34399630 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34399630 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356556 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356556 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.440430 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 94167216 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 94167216 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34671591 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34671591 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356534 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356534 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22477 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22477 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46756186 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46756186 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46756186 # number of overall hits -system.cpu.dcache.overall_hits::total 46756186 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1907 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1907 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7731 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7731 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 47028125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47028125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47028125 # number of overall hits +system.cpu.dcache.overall_hits::total 47028125 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1914 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1914 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7753 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7753 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9638 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9638 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9638 # number of overall misses -system.cpu.dcache.overall_misses::total 9638 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121525225 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121525225 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 489452496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 489452496 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9667 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9667 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9667 # number of overall misses +system.cpu.dcache.overall_misses::total 9667 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 120679977 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 120679977 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 501616998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 501616998 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 610977721 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 610977721 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 610977721 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 610977721 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34401537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34401537 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 622296975 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 622296975 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 622296975 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 622296975 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34673505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34673505 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22479 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22479 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46765824 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46765824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46765824 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46765824 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 47037792 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47037792 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47037792 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47037792 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63392.583627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63392.583627 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.545455 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64373.329368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64373.329368 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 99 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.428571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 99 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 19 # number of writebacks -system.cpu.dcache.writebacks::total 19 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1130 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1130 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6651 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6651 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6668 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6668 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7781 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7781 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7781 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7781 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7805 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7805 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7805 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7805 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1080 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1080 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52119013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52119013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75404498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75404498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 127523511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 127523511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 127523511 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 127523511 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1862 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1862 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1862 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1862 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51275761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51275761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75222996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75222996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126498757 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126498757 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126498757 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126498757 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index e8d7fb666..3c2ec0084 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -632,7 +634,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/x86/linux/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -674,27 +676,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 1e66bd991..dda302f8a 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 21:43:52 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:44:43 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 144463317000 because target called exit() +122 123 124 Exiting @ tick 145782984000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 8bb498da9..87a35ab50 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144620 # Number of seconds simulated -sim_ticks 144620050000 # Number of ticks simulated -final_tick 144620050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.145783 # Number of seconds simulated +sim_ticks 145782984000 # Number of ticks simulated +final_tick 145782984000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65513 # Simulator instruction rate (inst/s) -host_op_rate 109805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71737347 # Simulator tick rate (ticks/s) -host_mem_usage 319696 # Number of bytes of host memory used -host_seconds 2015.97 # Real time elapsed on the host +host_inst_rate 75578 # Simulator instruction rate (inst/s) +host_op_rate 126676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83424852 # Simulator tick rate (ticks/s) +host_mem_usage 276072 # Number of bytes of host memory used +host_seconds 1747.48 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory -system.physmem.bytes_read::total 342656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1501977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 867376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2369353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1501977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1501977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1501977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 867376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2369353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5356 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 219712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125824 # Number of bytes read from this memory +system.physmem.bytes_read::total 345536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219712 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3433 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1966 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1507117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 863091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2370208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1507117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1507117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1507117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 863091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2370208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5399 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5356 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5399 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 342784 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 345536 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 342784 # Total read bytes from the system interface side +system.physmem.bytesReadSys 345536 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 131 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 288 # Per bank write bursts -system.physmem.perBankRdBursts::1 358 # Per bank write bursts -system.physmem.perBankRdBursts::2 449 # Per bank write bursts -system.physmem.perBankRdBursts::3 356 # Per bank write bursts -system.physmem.perBankRdBursts::4 330 # Per bank write bursts -system.physmem.perBankRdBursts::5 328 # Per bank write bursts -system.physmem.perBankRdBursts::6 400 # Per bank write bursts -system.physmem.perBankRdBursts::7 378 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 225 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 296 # Per bank write bursts +system.physmem.perBankRdBursts::1 360 # Per bank write bursts +system.physmem.perBankRdBursts::2 450 # Per bank write bursts +system.physmem.perBankRdBursts::3 362 # Per bank write bursts +system.physmem.perBankRdBursts::4 334 # Per bank write bursts +system.physmem.perBankRdBursts::5 327 # Per bank write bursts +system.physmem.perBankRdBursts::6 402 # Per bank write bursts +system.physmem.perBankRdBursts::7 379 # Per bank write bursts system.physmem.perBankRdBursts::8 340 # Per bank write bursts -system.physmem.perBankRdBursts::9 277 # Per bank write bursts -system.physmem.perBankRdBursts::10 231 # Per bank write bursts -system.physmem.perBankRdBursts::11 276 # Per bank write bursts -system.physmem.perBankRdBursts::12 208 # Per bank write bursts -system.physmem.perBankRdBursts::13 466 # Per bank write bursts -system.physmem.perBankRdBursts::14 385 # Per bank write bursts -system.physmem.perBankRdBursts::15 286 # Per bank write bursts +system.physmem.perBankRdBursts::9 280 # Per bank write bursts +system.physmem.perBankRdBursts::10 232 # Per bank write bursts +system.physmem.perBankRdBursts::11 283 # Per bank write bursts +system.physmem.perBankRdBursts::12 213 # Per bank write bursts +system.physmem.perBankRdBursts::13 468 # Per bank write bursts +system.physmem.perBankRdBursts::14 388 # Per bank write bursts +system.physmem.perBankRdBursts::15 285 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 144620007000 # Total gap between requests +system.physmem.totGap 145782934000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5356 # Read request sizes (log2) +system.physmem.readPktSize::6 5399 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.933845 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.223116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.208962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 368 35.28% 35.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 248 23.78% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 102 9.78% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.56% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 4.03% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 5.66% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.63% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 23 2.21% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 126 12.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1043 # Bytes accessed per row activation -system.physmem.totQLat 35519000 # Total ticks spent queuing -system.physmem.totMemAccLat 135944000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6631.63 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.768881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.938334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.481688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 421 38.31% 38.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241 21.93% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 100 9.10% 69.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.91% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 5.10% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 54 4.91% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 19 1.73% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 1.82% 88.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 123 11.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation +system.physmem.totQLat 41267750 # Total ticks spent queuing +system.physmem.totMemAccLat 142499000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7643.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25381.63 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26393.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s @@ -214,279 +214,280 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4304 # Number of row buffer hits during reads +system.physmem.readRowHits 4296 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27001494.96 # Average gap between requests -system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 138334279250 # Time in different power states -system.physmem.memoryStateTime::REF 4828980000 # Time in different power states +system.physmem.avgGap 27001839.97 # Average gap between requests +system.physmem.pageHitRate 79.57 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 139294402000 # Time in different power states +system.physmem.memoryStateTime::REF 4867980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1451861250 # Time in different power states +system.physmem.memoryStateTime::ACT 1619857750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2368911 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3823 # Transaction distribution -system.membus.trans_dist::ReadResp 3820 # Transaction distribution -system.membus.trans_dist::UpgradeReq 131 # Transaction distribution -system.membus.trans_dist::UpgradeResp 131 # Transaction distribution -system.membus.trans_dist::ReadExReq 1533 # Transaction distribution -system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10971 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10971 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10971 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342592 # Total data (bytes) +system.membus.throughput 2370208 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3862 # Transaction distribution +system.membus.trans_dist::ReadResp 3862 # Transaction distribution +system.membus.trans_dist::UpgradeReq 225 # Transaction distribution +system.membus.trans_dist::UpgradeResp 225 # Transaction distribution +system.membus.trans_dist::ReadExReq 1537 # Transaction distribution +system.membus.trans_dist::ReadExResp 1537 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11248 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 345536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 345536 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 345536 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6960500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6776000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50659869 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50906775 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18663045 # Number of BP lookups -system.cpu.branchPred.condPredicted 18663045 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1489785 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11444584 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10797822 # Number of BTB hits +system.cpu.branchPred.lookups 19251245 # Number of BP lookups +system.cpu.branchPred.condPredicted 19251245 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1503864 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11794147 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11185323 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.348750 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1319901 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22895 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.837914 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1363914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22896 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289523031 # number of cpu cycles simulated +system.cpu.numCycles 291881234 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23473938 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206858197 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18663045 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12117723 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54247835 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15552938 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178336695 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7706 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22368694 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223698 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269869756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.267902 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.756065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 24212208 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 214052436 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19251245 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12549237 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55985392 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 16840264 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 177008858 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1283 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7024 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 65 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 23136044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282405 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 272277792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.296795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.780007 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 217061517 80.43% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2847740 1.06% 81.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2315002 0.86% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640494 0.98% 83.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3217056 1.19% 84.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3387561 1.26% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3839682 1.42% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2560696 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32000008 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 217778926 79.98% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2920418 1.07% 81.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2383762 0.88% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2729411 1.00% 82.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3335214 1.22% 84.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3498463 1.28% 85.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4001053 1.47% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2671434 0.98% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32959111 12.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269869756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064461 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.714479 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36939117 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167279649 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41594778 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10253994 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13802218 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336245393 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13802218 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45020160 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116775107 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31642 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42714880 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51525749 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329872428 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 11092 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26167242 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22759273 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382595093 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 918331708 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 606342575 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4133173 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 272277792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065956 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.733355 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35864450 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167881983 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44786392 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8682005 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15062962 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 346567500 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15062962 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42671339 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116778023 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 37081 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 45654825 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 52073562 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 340013592 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22387 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 45742154 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 5966467 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 137065 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 393960742 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 945391670 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 624205941 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4453971 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 123165643 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2073 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105277588 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84554246 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30134710 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58533931 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19035455 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322937953 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4364 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260608849 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 101196304 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210593531 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3119 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269869756 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.965684 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.342187 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 134531292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2243 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2238 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90830827 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 87006444 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31074157 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 61167406 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20316475 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 332092429 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4572 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 263265541 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 182587 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 110344895 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 231927910 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3327 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 272277792 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966901 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.357293 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143519297 53.18% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55647203 20.62% 73.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34229884 12.68% 86.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19073202 7.07% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10874136 4.03% 97.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4113724 1.52% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1802263 0.67% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476846 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 133201 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 146114169 53.66% 53.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54798888 20.13% 73.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34241976 12.58% 86.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18986540 6.97% 93.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11181244 4.11% 97.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4283756 1.57% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1956251 0.72% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 577925 0.21% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137043 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269869756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 272277792 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 125646 4.63% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2288183 84.39% 89.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 297636 10.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 142962 5.08% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2337044 83.10% 88.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 332186 11.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210826 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162119129 62.21% 62.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788294 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035677 2.70% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1444684 0.55% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65441941 25.11% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22568298 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210901 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 164273729 62.40% 62.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789732 0.30% 63.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035869 2.67% 65.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1461918 0.56% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65849141 25.01% 91.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22644251 8.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260608849 # Type of FU issued -system.cpu.iq.rate 0.900132 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2711465 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010404 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 789025856 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420800342 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255248449 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4885616 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3622403 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349194 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259650836 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2458652 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18874838 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 263265541 # Type of FU issued +system.cpu.iq.rate 0.901961 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2812192 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010682 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 796857032 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 438700759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 257701720 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4946621 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4039797 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2377852 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262377827 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2489005 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18800853 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27904659 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26471 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 289699 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9618993 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30356857 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 304082 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10558440 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49872 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13802218 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85051562 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5443180 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322942317 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133815 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84554246 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30134710 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2043 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2682047 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14716 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 289699 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 640019 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 900364 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540383 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258834349 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64663337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1774500 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15062962 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 84436601 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5827541 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 332097001 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 93155 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 87006444 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31074157 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2159 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2868922 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 287074 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 304082 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 649398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 907392 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1556790 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 261390422 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65051182 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1875119 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87028906 # number of memory reference insts executed -system.cpu.iew.exec_branches 14271418 # Number of branches executed -system.cpu.iew.exec_stores 22365569 # Number of stores executed -system.cpu.iew.exec_rate 0.894003 # Inst execution rate -system.cpu.iew.wb_sent 258197839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257597643 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206027195 # num instructions producing a value -system.cpu.iew.wb_consumers 369217293 # num instructions consuming a value +system.cpu.iew.exec_refs 87491108 # number of memory reference insts executed +system.cpu.iew.exec_branches 14410736 # Number of branches executed +system.cpu.iew.exec_stores 22439926 # Number of stores executed +system.cpu.iew.exec_rate 0.895537 # Inst execution rate +system.cpu.iew.wb_sent 260730148 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 260079572 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208603284 # num instructions producing a value +system.cpu.iew.wb_consumers 373821854 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.889731 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.558011 # average fanout of values written-back +system.cpu.iew.wb_rate 0.891046 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.558029 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101647922 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110904752 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1490935 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 256067538 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.864473 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651889 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1504927 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 257214830 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.860617 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.643182 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156617936 61.16% 61.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57255270 22.36% 83.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14082261 5.50% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12088609 4.72% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4189643 1.64% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2964480 1.16% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 903129 0.35% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1051661 0.41% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6914549 2.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157256344 61.14% 61.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57715541 22.44% 83.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14223073 5.53% 89.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12060500 4.69% 93.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4224463 1.64% 95.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2956145 1.15% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 920096 0.36% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048300 0.41% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6810368 2.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 256067538 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 257214830 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -532,241 +533,241 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6914549 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6810368 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 572164295 # The number of ROB reads -system.cpu.rob.rob_writes 659850863 # The number of ROB writes -system.cpu.timesIdled 5930649 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19653275 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 582672598 # The number of ROB reads +system.cpu.rob.rob_writes 679632792 # The number of ROB writes +system.cpu.timesIdled 5976195 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19603442 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.192174 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.192174 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451375343 # number of integer regfile reads -system.cpu.int_regfile_writes 234032598 # number of integer regfile writes -system.cpu.fp_regfile_reads 3213912 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009037 # number of floating regfile writes -system.cpu.cc_regfile_reads 102846049 # number of cc regfile reads -system.cpu.cc_regfile_writes 59805449 # number of cc regfile writes -system.cpu.misc_regfile_reads 133386978 # number of misc regfile reads +system.cpu.cpi 2.210030 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.210030 # CPI: Total CPI of All Threads +system.cpu.ipc 0.452483 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.452483 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 453366407 # number of integer regfile reads +system.cpu.int_regfile_writes 236319036 # number of integer regfile writes +system.cpu.fp_regfile_reads 3248620 # number of floating regfile reads +system.cpu.fp_regfile_writes 2037591 # number of floating regfile writes +system.cpu.cc_regfile_reads 102911292 # number of cc regfile reads +system.cpu.cc_regfile_writes 59928663 # number of cc regfile writes +system.cpu.misc_regfile_reads 134914047 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3852301 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7153 # Transaction distribution +system.cpu.toL2Bus.throughput 4027905 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7618 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13245 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17531 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 419584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 548608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 548608 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8512 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4433000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeReq 226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1544 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1544 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14075 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 18565 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 443136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 572736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 572736 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 14464 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4714500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10626750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11320000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3450631 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3508475 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4592 # number of replacements -system.cpu.icache.tags.tagsinuse 1628.049417 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22359876 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6557 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3410.077169 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4955 # number of replacements +system.cpu.icache.tags.tagsinuse 1627.815791 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23126816 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6924 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3340.094743 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1628.049417 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.794946 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.794946 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 44744077 # Number of tag accesses -system.cpu.icache.tags.data_accesses 44744077 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22359876 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22359876 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22359876 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22359876 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22359876 # number of overall hits -system.cpu.icache.overall_hits::total 22359876 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8818 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8818 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8818 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8818 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8818 # number of overall misses -system.cpu.icache.overall_misses::total 8818 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 365022750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 365022750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 365022750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 365022750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 365022750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 365022750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22368694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22368694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22368694 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22368694 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22368694 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22368694 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000394 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000394 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000394 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000394 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000394 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000394 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41395.185983 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41395.185983 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41395.185983 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41395.185983 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 701 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1627.815791 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.794832 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.794832 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1969 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 748 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.961426 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 46279236 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46279236 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23126816 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23126816 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23126816 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23126816 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23126816 # number of overall hits +system.cpu.icache.overall_hits::total 23126816 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9227 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9227 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9227 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9227 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9227 # number of overall misses +system.cpu.icache.overall_misses::total 9227 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 376330999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 376330999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 376330999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 376330999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 376330999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 376330999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23136043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23136043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23136043 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23136043 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23136043 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23136043 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40785.845779 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40785.845779 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40785.845779 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40785.845779 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40785.845779 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40785.845779 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1569 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.733333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 98.062500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2129 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2129 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2129 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2129 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2129 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2129 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6689 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6689 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6689 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6689 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6689 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6689 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 269490250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 269490250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 269490250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 269490250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 269490250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 269490250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40288.570788 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40288.570788 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2076 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2076 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2076 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2076 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2076 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2076 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7151 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7151 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7151 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7151 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7151 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7151 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279771249 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 279771249 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 279771249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 279771249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 279771249 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 279771249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000309 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000309 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000309 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39123.374213 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39123.374213 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39123.374213 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39123.374213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39123.374213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39123.374213 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2549.629926 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3205 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3824 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.838128 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2580.073748 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3536 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3865 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.914877 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.731773 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2236.346523 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 311.551630 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068248 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009508 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.077809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3824 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2568 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116699 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 75020 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 75020 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3162 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3200 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1.848072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2267.439437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 310.786239 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000056 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069197 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009484 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.078738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3865 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55458.360442 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55458.360442 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56625.509610 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57552.390641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56962.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56625.509610 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57552.390641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56962.962963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 59 # number of replacements -system.cpu.dcache.tags.tagsinuse 1435.036669 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66148000 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2003 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33024.463305 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 57 # number of replacements +system.cpu.dcache.tags.tagsinuse 1441.863444 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66606870 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33104.806163 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1435.036669 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.350351 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.350351 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 430 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 132302857 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 132302857 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45633758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45633758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514059 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514059 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66147817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66147817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66147817 # number of overall hits -system.cpu.dcache.overall_hits::total 66147817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1672 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1672 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses -system.cpu.dcache.overall_misses::total 2610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59941301 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59941301 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 112492631 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 112492631 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 172433932 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 172433932 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 172433932 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 172433932 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45634696 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45634696 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.863444 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352017 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352017 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1955 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.477295 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 133220616 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 133220616 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46092554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46092554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513960 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513960 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66606514 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66606514 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66606514 # number of overall hits +system.cpu.dcache.overall_hits::total 66606514 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1017 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1017 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1771 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1771 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2788 # number of overall misses +system.cpu.dcache.overall_misses::total 2788 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 61229380 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 61229380 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 115680725 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115680725 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 176910105 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 176910105 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 176910105 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 176910105 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46093571 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46093571 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66150427 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66150427 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66150427 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66150427 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63903.305970 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63903.305970 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67280.281699 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67280.281699 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66066.640613 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66066.640613 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 66609302 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66609302 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66609302 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66609302 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60205.880039 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60205.880039 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65319.438171 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65319.438171 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63454.126614 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63454.126614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63454.126614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63454.126614 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 94 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 470 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 547 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 547 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 472 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 472 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 472 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1670 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1670 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32985750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32985750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108417619 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 108417619 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141403369 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 141403369 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 141403369 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 141403369 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 549 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 549 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 549 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 549 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1769 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1769 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2239 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2239 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2239 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2239 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111361525 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 111361525 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145474525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 145474525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145474525 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 145474525 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000081 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000081 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70482.371795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70482.371795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64920.729940 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64920.729940 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72580.851064 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72580.851064 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62951.681741 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62951.681741 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64972.990174 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64972.990174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64972.990174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64972.990174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |