diff options
| author | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-07-23 16:09:05 -0500 |
|---|---|---|
| committer | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-07-23 16:09:05 -0500 |
| commit | 5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d (patch) | |
| tree | 0b8cdef424988f3486a9f2cebbb49f76b74ae8f9 /tests/long/se | |
| parent | 0e8a90f06bd3db00f700891a33458353478cce76 (diff) | |
| download | gem5-5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d.tar.xz | |
cpu: Minor CPU add regression tests for ARM and ALPHA
This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
Diffstat (limited to 'tests/long/se')
52 files changed, 22234 insertions, 0 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..e291e1e5a --- /dev/null +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/mcf +gid=100 +input=/arm/projectscratch/pd/sysrandd/dist/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=55300000000 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:268435455 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..1a4f96712 --- /dev/null +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..aed824289 --- /dev/null +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout @@ -0,0 +1,29 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 16:03:40 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x11aa5150 +info: Entering event queue @ 0. Starting simulation... + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +Exiting @ tick 61276704500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..ec3cdc9eb --- /dev/null +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,695 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 61269894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 246086 # Simulator instruction rate (inst/s) +host_mem_usage 426904 # Number of bytes of host memory used +host_op_rate 247853 # Simulator op (including micro ops) rate (op/s) +host_seconds 368.18 # Real time elapsed on the host +host_tick_rate 166415131 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 90602849 # Number of instructions simulated +sim_ops 91253402 # Number of ops (including micro ops) simulated +sim_seconds 0.061270 # Number of seconds simulated +sim_ticks 61269894500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.707356 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 8859613 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8975636 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1020 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 765388 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 17116903 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20794461 # Number of BP lookups +system.cpu.branchPred.usedRAS 54785 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 90602849 # Number of instructions committed +system.cpu.committedOps 91253402 # Number of ops (including micro ops) committed +system.cpu.cpi 1.352494 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 22606743 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22606743 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13018.894340 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13018.894340 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11024.761855 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.761855 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 21691800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21691800 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11911546244 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11911546244 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040472 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040472 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 914943 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11527 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11527 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9959946256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9959946256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.039962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903416 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903416 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31690.074425 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31690.074425 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28535.254491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.254491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 4661081 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4661081 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2341896500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2341896500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015607 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015607 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 73900 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73900 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334308500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334308500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009875 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009875 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46760 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46760 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 27341724 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27341724 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14414.262673 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 26352881 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26352881 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 14253442744 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14253442744 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.036166 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036166 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 988843 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 988843 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 38667 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38667 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11294254756 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11294254756 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034752 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 950176 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950176 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 27341724 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27341724 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14414.262673 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 26352881 # number of overall hits +system.cpu.dcache.overall_hits::total 26352881 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 14253442744 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14253442744 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.036166 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036166 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 988843 # number of overall misses +system.cpu.dcache.overall_misses::total 988843 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 38667 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38667 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11294254756 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11294254756 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034752 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 950176 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950176 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2200 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 27.742918 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 55649172 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.532737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.883431 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883431 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 946080 # number of replacements +system.cpu.dcache.tags.sampled_refs 950176 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 55649172 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 3618.532737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26360655 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20496262250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 943298 # number of writebacks +system.cpu.dcache.writebacks::total 943298 # number of writebacks +system.cpu.discardedOps 2065378 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 27818907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27818907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68915.429630 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68915.429630 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66500.619753 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66500.619753 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 27818097 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27818097 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55821498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55821498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 810 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 810 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53865502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53865502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 810 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 810 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 27818907 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27818907 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68915.429630 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 27818097 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27818097 # number of demand (read+write) hits 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27818097 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 55821498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55821498 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 810 # number of overall misses +system.cpu.icache.overall_misses::total 810 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53865502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53865502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 810 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 810 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 748 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 34343.329630 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 55638624 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 696.774140 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.340222 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.340222 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id 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ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46760 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46760 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65946.757667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65946.757667 # average ReadExReq miss latency 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ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772095750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310992 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310992 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14542 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14542 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 904226 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904226 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69821.699905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69821.699905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57393.301435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57393.301435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 903173 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903173 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 73522250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 73522250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001165 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001165 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 1053 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1053 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59976000 # 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MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832071750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 832071750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15587 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15587 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 950986 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses 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+system.cpu.toL2Bus.throughput 1978690791 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121234176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 904226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46760 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46760 # Transaction distribution +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 997568 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31174 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 21774500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 149672750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 16281536 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 997568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 997568 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1045 # Transaction distribution +system.membus.trans_dist::ReadResp 1045 # Transaction distribution +system.membus.trans_dist::ReadExReq 14542 # Transaction distribution +system.membus.trans_dist::ReadExResp 14542 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 3930827.39 # Average gap between requests +system.physmem.avgMemAccLat 23360.33 # Average memory access latency per DRAM burst +system.physmem.avgQLat 4610.33 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 816845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 816845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 16281536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16281536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16281536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16281536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1547 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 643.557854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 434.536592 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 403.240998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 258 16.68% 16.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 197 12.73% 29.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 72 4.65% 34.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 3.68% 37.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 69 4.46% 42.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 102 6.59% 48.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.78% 51.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 57 3.68% 55.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 692 44.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1547 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 997568 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 997568 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 50048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50048 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 997568 # Number of bytes read from this memory +system.physmem.bytes_read::total 997568 # Number of bytes read from this memory +system.physmem.memoryStateTime::IDLE 55978709750 # Time in different power states +system.physmem.memoryStateTime::REF 2045680000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 3241107750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 15587 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15587 # Number of read requests responded to by this memory +system.physmem.pageHitRate 90.01 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 994 # Per bank write bursts +system.physmem.perBankRdBursts::1 891 # Per bank write bursts +system.physmem.perBankRdBursts::2 951 # Per bank write bursts +system.physmem.perBankRdBursts::3 1028 # Per bank write bursts +system.physmem.perBankRdBursts::4 1052 # Per bank write bursts +system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::6 1088 # Per bank write bursts +system.physmem.perBankRdBursts::7 1088 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts +system.physmem.perBankRdBursts::9 962 # Per bank write bursts +system.physmem.perBankRdBursts::10 941 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::13 869 # Per bank write bursts +system.physmem.perBankRdBursts::14 877 # Per bank write bursts +system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.rdQLenPdf::0 15468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 15587 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 15587 # Read request sizes (log2) +system.physmem.readReqs 15587 # Number of read requests accepted +system.physmem.readRowHitRate 90.01 # Row buffer hit rate for reads +system.physmem.readRowHits 14030 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 77935000 # Total ticks spent in databus transfers +system.physmem.totGap 61269806500 # Total gap between requests +system.physmem.totMemAccLat 364117500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 71861250 # Total ticks spent queuing +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 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+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini new file mode 100644 index 000000000..f1b635684 --- /dev/null +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini @@ -0,0 +1,718 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/parser +gid=100 +input=/arm/projectscratch/pd/sysrandd/dist/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr new file mode 100644 index 000000000..506aa6e28 --- /dev/null +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout new file mode 100644 index 000000000..6e5c2e80e --- /dev/null +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout @@ -0,0 +1,71 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:41:53 +gem5 started May 7 2014 16:13:15 +gem5 executing on cz3212c2d7 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. + + Reading the dictionary files: ************************************************* + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 409513954500 because target called exit() diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt new file mode 100644 index 000000000..3677da8b6 --- /dev/null +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,670 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 409828126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 259766 # Simulator instruction rate (inst/s) +host_mem_usage 250424 # Number of bytes of host memory used +host_op_rate 259766 # Simulator op (including micro ops) rate (op/s) +host_seconds 2355.59 # Real time elapsed on the host +host_tick_rate 173981398 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 611901617 # Number of instructions simulated +sim_ops 611901617 # Number of ops (including micro ops) simulated +sim_seconds 0.409828 # Number of seconds simulated +sim_ticks 409828126500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 94.066276 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 67266528 # Number of BTB hits +system.cpu.branchPred.BTBLookups 71509717 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1120898 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 6389580 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 87724444 # Number of conditional branches predicted +system.cpu.branchPred.lookups 123843348 # Number of BP lookups +system.cpu.branchPred.usedRAS 14941692 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 611901617 # Number of instructions committed +system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed +system.cpu.cpi 1.339523 # CPI: cycles per instruction +system.cpu.dcache.ReadReq_accesses::cpu.inst 148791104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148791104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19067.269367 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19067.269367 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17118.543589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17118.543589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 146883081 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146883081 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36380788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36380788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012824 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012824 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 1908023 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908023 # number of ReadReq misses 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29178.748051 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29178.748051 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27324.419197 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27324.419197 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 55666185 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666185 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45047581000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45047581000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 1543849 # number of WriteReq misses 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number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098147 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.098147 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 173359 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 173359 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10448278750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10448278750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098147 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098147 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173359 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 173359 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 2340003 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2340003 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 2340003 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2340003 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 2544474 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544474 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72056.258158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72056.258158 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59338.816794 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59338.816794 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 2164498 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2164498 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 27379648750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27379648750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149334 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149334 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 379976 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 379976 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22547326250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22547326250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149334 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149334 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 379976 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 379976 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 2544474 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544474 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72056.258158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72056.258158 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59338.816794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59338.816794 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 2164498 # number of overall hits +system.cpu.l2cache.overall_hits::total 2164498 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 27379648750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27379648750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149334 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149334 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 379976 # number of overall misses +system.cpu.l2cache.overall_misses::total 379976 # number of overall misses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22547326250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22547326250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149334 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149334 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 379976 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 379976 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18830 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 9.773812 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 40233665 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 21416.051201 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8077.270621 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.653566 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246499 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.900065 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 347265 # number of replacements +system.cpu.l2cache.tags.sampled_refs 379689 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 40233665 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 29493.321822 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3711009 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 188556996000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 292560 # number of writebacks +system.cpu.l2cache.writebacks::total 292560 # number of writebacks +system.cpu.numCycles 819656253 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 737909003 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 312606528 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10008 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7418943 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7428951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4782241500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 8058500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3891611750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 762774704 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 320256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312286272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 312606528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1766314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340003 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution +system.cpu.workload.num_syscalls 485 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 43042304 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052512 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052512 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 3207663500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3609435250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 105025256 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43042304 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43042304 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 173359 # Transaction distribution +system.membus.trans_dist::ReadResp 173359 # Transaction distribution +system.membus.trans_dist::Writeback 292560 # Transaction distribution +system.membus.trans_dist::ReadExReq 206617 # Transaction distribution +system.membus.trans_dist::ReadExResp 206617 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 609377.11 # Average gap between requests +system.physmem.avgMemAccLat 29335.98 # Average memory access latency per DRAM burst +system.physmem.avgQLat 10585.98 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 59.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 45.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.69 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 21.08 # Average write queue length when enqueuing +system.physmem.busUtil 0.82 # Data bus utilization in percentage +system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 416487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 416487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 59338202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59338202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45687055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59338202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 105025256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 45687055 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45687055 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 141722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.513414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.917362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.228374 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50747 35.81% 35.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38472 27.15% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12956 9.14% 72.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8075 5.70% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5903 4.17% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3858 2.72% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2996 2.11% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2531 1.79% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16184 11.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 141722 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 24294464 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 24318464 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722176 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 18723840 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 170688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170688 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 24318464 # Number of bytes read from this memory +system.physmem.bytes_read::total 24318464 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 18723840 # Number of bytes written to this memory +system.physmem.bytes_written::total 18723840 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 275306446750 # Time in different power states +system.physmem.memoryStateTime::REF 13684840000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 120830469500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 379976 # Number of read requests responded to by this memory +system.physmem.num_reads::total 379976 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292560 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292560 # Number of write requests responded to by this memory +system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 23726 # Per bank write bursts +system.physmem.perBankRdBursts::1 23205 # Per bank write bursts +system.physmem.perBankRdBursts::2 23510 # Per bank write bursts +system.physmem.perBankRdBursts::3 24533 # Per bank write bursts +system.physmem.perBankRdBursts::4 25455 # Per bank write bursts +system.physmem.perBankRdBursts::5 23583 # Per bank write bursts +system.physmem.perBankRdBursts::6 23677 # Per bank write bursts +system.physmem.perBankRdBursts::7 23976 # Per bank write bursts +system.physmem.perBankRdBursts::8 23173 # Per bank write bursts +system.physmem.perBankRdBursts::9 23944 # Per bank write bursts +system.physmem.perBankRdBursts::10 24673 # Per bank write bursts +system.physmem.perBankRdBursts::11 22745 # Per bank write bursts +system.physmem.perBankRdBursts::12 23724 # Per bank write bursts +system.physmem.perBankRdBursts::13 24416 # Per bank write bursts +system.physmem.perBankRdBursts::14 22797 # Per bank write bursts +system.physmem.perBankRdBursts::15 22464 # Per bank write bursts +system.physmem.perBankWrBursts::0 17752 # Per bank write bursts +system.physmem.perBankWrBursts::1 17432 # Per bank write bursts +system.physmem.perBankWrBursts::2 17901 # Per bank write bursts +system.physmem.perBankWrBursts::3 18769 # Per bank write bursts +system.physmem.perBankWrBursts::4 19443 # Per bank write bursts +system.physmem.perBankWrBursts::5 18535 # Per bank write bursts +system.physmem.perBankWrBursts::6 18682 # Per bank write bursts +system.physmem.perBankWrBursts::7 18571 # Per bank write bursts +system.physmem.perBankWrBursts::8 18355 # Per bank write bursts +system.physmem.perBankWrBursts::9 18833 # Per bank write bursts +system.physmem.perBankWrBursts::10 19130 # Per bank write bursts +system.physmem.perBankWrBursts::11 17964 # Per bank write bursts +system.physmem.perBankWrBursts::12 18225 # Per bank write bursts +system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::14 17147 # Per bank write bursts +system.physmem.perBankWrBursts::15 17101 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 17247 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.008465 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.376560 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17237 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17247 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 378215 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 379976 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 379976 # Read request sizes (log2) +system.physmem.readReqs 379976 # Number of read requests accepted +system.physmem.readRowHitRate 82.98 # Row buffer hit rate for reads +system.physmem.readRowHits 314993 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 1898005000 # Total ticks spent in databus transfers +system.physmem.totGap 409828045500 # Total gap between requests +system.physmem.totMemAccLat 11135967500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4018448750 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 17247 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.961443 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.889231 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.813189 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17030 98.74% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 169 0.98% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17247 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 292560 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 292560 # Write request sizes (log2) +system.physmem.writeReqs 292560 # Number of write requests accepted +system.physmem.writeRowHitRate 73.63 # Row buffer hit rate for writes +system.physmem.writeRowHits 215411 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..0276b8a93 --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 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+opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] 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+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/parser +gid=100 +input=/arm/projectscratch/pd/sysrandd/dist/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..5d8946ede --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..7e896fb1e --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout @@ -0,0 +1,73 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 15:30:22 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x1e6be7a0 +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +info: Increasing stack size by one page. +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 377875396500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..8bc6ffa49 --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,738 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 377848323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 209721 # Simulator instruction rate (inst/s) +host_mem_usage 298084 # Number of bytes of host memory used +host_op_rate 236376 # Simulator op (including micro ops) rate (op/s) +host_seconds 2415.51 # Real time elapsed on the host +host_tick_rate 156426000 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 506582155 # Number of instructions simulated +sim_ops 570968717 # Number of ops (including micro ops) simulated +sim_seconds 0.377848 # Number of seconds simulated +sim_ticks 377848323500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 88.099044 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 66115419 # Number of BTB hits +system.cpu.branchPred.BTBLookups 75046693 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 20332 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 6724593 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 104577278 # Number of conditional branches predicted +system.cpu.branchPred.lookups 137186083 # Number of BP lookups +system.cpu.branchPred.usedRAS 8950727 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 506582155 # Number of instructions committed +system.cpu.committedOps 570968717 # Number of ops (including micro ops) committed +system.cpu.cpi 1.491755 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 123498792 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 123498792 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16388.035885 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16388.035885 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.902943 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.902943 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 122622654 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 122622654 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 14358180984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14358180984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007094 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007094 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 876138 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 876138 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 88069 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 88069 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11252760763 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252760763 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006381 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006381 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 788069 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 788069 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29400.581233 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29400.581233 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28261.554772 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28261.554772 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 53538382 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538382 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20607573000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20607573000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012923 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012923 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 700924 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700924 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344621 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344621 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10069676750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10069676750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356303 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356303 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 177738098 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 177738098 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22171.451715 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 176161036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176161036 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 34965753984 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34965753984 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.008873 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008873 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 1577062 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1577062 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 432690 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 432690 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21322437513 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21322437513 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006439 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1144372 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1144372 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 177738098 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 177738098 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22171.451715 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 176161036 # number of overall hits +system.cpu.dcache.overall_hits::total 176161036 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 34965753984 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34965753984 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.008873 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008873 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 1577062 # number of overall misses +system.cpu.dcache.overall_misses::total 1577062 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 432690 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 432690 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21322437513 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21322437513 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006439 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1144372 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1144372 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3508 # Occupied blocks per task id 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# Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 204480200 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 204480200 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23608.753898 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23608.753898 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.715773 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.715773 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 204459741 # number of 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accesses +system.cpu.icache.overall_misses::cpu.inst 20459 # number of overall misses +system.cpu.icache.overall_misses::total 20459 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440701504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 440701504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 20459 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 20459 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 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Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # 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Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356556 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356556 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70944.376455 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70944.376455 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58283.052569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58283.052569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 255641 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255641 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7159351750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7159351750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283027 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283027 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 100915 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100915 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5881634250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5881634250 # number of ReadExReq MSHR miss cycles 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ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053685 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053685 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43392 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43392 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 1068741 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1068741 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 1068741 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1068741 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 1164831 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1164831 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71983.027536 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 1020509 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1020509 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 10388734500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10388734500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123900 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123900 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 144322 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144322 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8560629500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8560629500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123887 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 144307 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144307 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 1164831 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1164831 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71983.027536 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 1020509 # number of overall hits +system.cpu.l2cache.overall_hits::total 1020509 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 10388734500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10388734500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123900 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123900 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 144322 # number of overall misses +system.cpu.l2cache.overall_misses::total 144322 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8560629500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8560629500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123887 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 144307 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144307 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4944 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 11.811039 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 18367876 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 23534.473696 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4154.581244 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.718215 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.126788 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.845003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31193 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951935 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 111551 # number of replacements +system.cpu.l2cache.tags.sampled_refs 142744 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 18367876 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 27689.054939 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1685955 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 168523988500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 96655 # number of writebacks +system.cpu.l2cache.writebacks::total 96655 # number of writebacks +system.cpu.numCycles 755696647 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 718839335 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 142948608 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3357485 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3398403 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2185527000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 31384496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1745291987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 378322727 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1309376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141639232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 142948608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 808275 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 808275 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356556 # Transaction distribution +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 15421568 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385269 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 385269 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 1076098500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1364495500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 40814176 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15421568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15421568 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43392 # Transaction distribution +system.membus.trans_dist::ReadResp 43392 # Transaction distribution +system.membus.trans_dist::Writeback 96655 # Transaction distribution +system.membus.trans_dist::ReadExReq 100915 # Transaction distribution +system.membus.trans_dist::ReadExResp 100915 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 1568082.50 # Average gap between requests +system.physmem.avgMemAccLat 29316.89 # Average memory access latency per DRAM burst +system.physmem.avgQLat 10566.89 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 24.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 24.44 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrBW 16.37 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.37 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing +system.physmem.busUtil 0.32 # Data bus utilization in percentage +system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 599436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 599436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 24442739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 24442739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16371437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 24442739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40814176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 16371437 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16371437 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 65344 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.879530 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.532408 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.691059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24749 37.87% 37.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18254 27.94% 65.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7150 10.94% 76.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7883 12.06% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2042 3.12% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1102 1.69% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 756 1.16% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 612 0.94% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2796 4.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65344 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 9229248 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 9235648 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue +system.physmem.bytesWritten 6184768 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 6185920 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 9235648 # Number of bytes read from this memory +system.physmem.bytes_read::total 9235648 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 6185920 # Number of bytes written to this memory +system.physmem.bytes_written::total 6185920 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 265986637250 # Time in different power states +system.physmem.memoryStateTime::REF 12617020000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 99239970250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 144307 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144307 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96655 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96655 # Number of write requests responded to by this memory +system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 9328 # Per bank write bursts +system.physmem.perBankRdBursts::1 8986 # Per bank write bursts +system.physmem.perBankRdBursts::2 9010 # Per bank write bursts +system.physmem.perBankRdBursts::3 8718 # Per bank write bursts +system.physmem.perBankRdBursts::4 9475 # Per bank write bursts +system.physmem.perBankRdBursts::5 9358 # Per bank write bursts +system.physmem.perBankRdBursts::6 8951 # Per bank write bursts +system.physmem.perBankRdBursts::7 8100 # Per bank write bursts +system.physmem.perBankRdBursts::8 8572 # Per bank write bursts +system.physmem.perBankRdBursts::9 8669 # Per bank write bursts +system.physmem.perBankRdBursts::10 8784 # Per bank write bursts +system.physmem.perBankRdBursts::11 9499 # Per bank write bursts +system.physmem.perBankRdBursts::12 9376 # Per bank write bursts +system.physmem.perBankRdBursts::13 9538 # Per bank write bursts +system.physmem.perBankRdBursts::14 8741 # Per bank write bursts +system.physmem.perBankRdBursts::15 9102 # Per bank write bursts +system.physmem.perBankWrBursts::0 6202 # Per bank write bursts +system.physmem.perBankWrBursts::1 6099 # Per bank write bursts +system.physmem.perBankWrBursts::2 6021 # Per bank write bursts +system.physmem.perBankWrBursts::3 5821 # Per bank write bursts +system.physmem.perBankWrBursts::4 6172 # Per bank write bursts +system.physmem.perBankWrBursts::5 6184 # Per bank write bursts +system.physmem.perBankWrBursts::6 6018 # Per bank write bursts +system.physmem.perBankWrBursts::7 5493 # Per bank write bursts +system.physmem.perBankWrBursts::8 5732 # Per bank write bursts +system.physmem.perBankWrBursts::9 5815 # Per bank write bursts +system.physmem.perBankWrBursts::10 5965 # Per bank write bursts +system.physmem.perBankWrBursts::11 6456 # Per bank write bursts +system.physmem.perBankWrBursts::12 6307 # Per bank write bursts +system.physmem.perBankWrBursts::13 6282 # Per bank write bursts +system.physmem.perBankWrBursts::14 6014 # Per bank write bursts +system.physmem.perBankWrBursts::15 6056 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 5563 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.922344 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.692234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5559 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5563 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 143841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 144307 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 144307 # Read request sizes (log2) +system.physmem.readReqs 144307 # Number of read requests accepted +system.physmem.readRowHitRate 76.88 # Row buffer hit rate for reads +system.physmem.readRowHits 110862 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 721035000 # Total ticks spent in databus transfers +system.physmem.totGap 377848294500 # Total gap between requests +system.physmem.totMemAccLat 4227701250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1523820000 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 5563 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.371382 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.273622 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.337365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2499 44.92% 44.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2925 52.58% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 45 0.81% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 18 0.32% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 19 0.34% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 16 0.29% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 12 0.22% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 7 0.13% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.05% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 4 0.07% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 4 0.07% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5563 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 96655 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 96655 # Write request sizes (log2) +system.physmem.writeReqs 96655 # Number of write requests accepted +system.physmem.writeRowHitRate 66.87 # Row buffer hit rate for writes +system.physmem.writeRowHits 64630 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini new file mode 100644 index 000000000..e4aa5eab5 --- /dev/null +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini @@ -0,0 +1,718 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/eon +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr new file mode 100644 index 000000000..abe1622a9 --- /dev/null +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr @@ -0,0 +1,51 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout new file mode 100644 index 000000000..2951870e8 --- /dev/null +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout @@ -0,0 +1,16 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:41:53 +gem5 started May 7 2014 10:42:15 +gem5 executing on cz3212c2d7 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +OO-style eon Time= 0.216667 +Exiting @ tick 220685290500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt new file mode 100644 index 000000000..12f448f86 --- /dev/null +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,631 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 220685053500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 266134 # Simulator instruction rate (inst/s) +host_mem_usage 254064 # Number of bytes of host memory used +host_op_rate 266134 # Simulator op (including micro ops) rate (op/s) +host_seconds 1497.99 # Real time elapsed on the host +host_tick_rate 147321061 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 398664665 # Number of instructions simulated +sim_ops 398664665 # Number of ops (including micro ops) simulated +sim_seconds 0.220685 # Number of seconds simulated +sim_ticks 220685053500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 83.751650 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 21330181 # Number of BTB hits +system.cpu.branchPred.BTBLookups 25468371 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1012944 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 26708480 # Number of conditional branches predicted +system.cpu.branchPred.lookups 46221019 # Number of BP lookups +system.cpu.branchPred.usedRAS 8327448 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 398664665 # Number of instructions committed +system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed +system.cpu.cpi 1.107121 # CPI: cycles per instruction +system.cpu.dcache.ReadReq_accesses::cpu.inst 94494338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94494338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68449.404762 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68449.404762 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66089.617769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66089.617769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 94493162 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94493162 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 80496500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80496500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 63974750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63974750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66549.865343 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66549.865343 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67934.000626 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67934.000626 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 73514789 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514789 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 395372750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 395372750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 5941 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5941 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2744 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 217185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 217185000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 168015068 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168015068 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66863.741745 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66863.741745 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67505.342137 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67505.342137 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 168007951 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168007951 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 475869250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 475869250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 7117 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7117 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 2952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281159750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281159750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 168015068 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168015068 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66863.741745 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66863.741745 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67505.342137 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67505.342137 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 168007951 # number of overall hits +system.cpu.dcache.overall_hits::total 168007951 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 475869250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 475869250 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 7117 # number of overall misses +system.cpu.dcache.overall_misses::total 7117 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 2952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281159750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281159750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 40338.043457 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 336034301 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.724304 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.803644 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803644 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 771 # number of replacements +system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 336034301 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 3291.724304 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168007951 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 654 # number of writebacks +system.cpu.dcache.writebacks::total 654 # number of writebacks +system.cpu.discardedOps 4407642 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dtb.data_accesses 169201829 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 169200862 # DTB hits +system.cpu.dtb.data_misses 967 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 95596602 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 95596493 # DTB read hits +system.cpu.dtb.read_misses 109 # DTB read misses +system.cpu.dtb.write_accesses 73605227 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 73604369 # DTB write hits +system.cpu.dtb.write_misses 858 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 98039875 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98039875 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56706.988208 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56706.988208 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54392.373864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54392.373864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 98034702 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98034702 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293345250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293345250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281371750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281371750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5173 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5173 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 98039875 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98039875 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56706.988208 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56706.988208 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54392.373864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54392.373864 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 98034702 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98034702 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 293345250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293345250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281371750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281371750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses 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overall hits +system.cpu.icache.overall_hits::total 98034702 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 293345250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293345250 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses +system.cpu.icache.overall_misses::total 5173 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281371750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281371750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses 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misses +system.cpu.itb.fetch_accesses 98041099 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 98039875 # ITB hits +system.cpu.itb.fetch_misses 1224 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68031.548757 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68031.548757 # average ReadExReq miss latency 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miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173781500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980932 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68618.957146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68618.957146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56083.175005 # average ReadReq mshr miss latency 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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4737 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 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+system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 538531000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 538531000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 7875 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439447500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 439447500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 9338 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9338 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68384.888889 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68384.888889 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55802.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55802.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 1463 # number of overall hits +system.cpu.l2cache.overall_hits::total 1463 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 538531000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 538531000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses +system.cpu.l2cache.overall_misses::total 7875 # number of overall misses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439447500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 439447500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 88409 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 373.078063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.561025 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 88409 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 4427.639089 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.numCycles 441370107 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 437376569 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 639488 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 8573250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6973250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 2897740 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # Transaction distribution +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 504000 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 9402000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 73919000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 2283798 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 4737 # Transaction distribution +system.membus.trans_dist::ReadResp 4737 # Transaction distribution +system.membus.trans_dist::ReadExReq 3138 # Transaction distribution +system.membus.trans_dist::ReadExResp 3138 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 28023488.51 # Average gap between requests +system.physmem.avgMemAccLat 25444.19 # Average memory access latency per DRAM burst +system.physmem.avgQLat 6694.19 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 1130154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1130154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2283798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2283798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2283798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2283798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.859118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.497740 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.655221 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 518 34.10% 34.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 348 22.91% 57.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 182 11.98% 68.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 96 6.32% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 4.15% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.16% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 42 2.76% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 38 2.50% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 504000 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 504000 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 249408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 504000 # Number of bytes read from this memory +system.physmem.bytes_read::total 504000 # Number of bytes read from this memory +system.physmem.memoryStateTime::IDLE 211586881750 # Time in different power states +system.physmem.memoryStateTime::REF 7368920000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1722369500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory +system.physmem.pageHitRate 80.58 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 551 # Per bank write bursts +system.physmem.perBankRdBursts::1 675 # Per bank write bursts +system.physmem.perBankRdBursts::2 471 # Per bank write bursts +system.physmem.perBankRdBursts::3 633 # Per bank write bursts +system.physmem.perBankRdBursts::4 475 # Per bank write bursts +system.physmem.perBankRdBursts::5 478 # Per bank write bursts +system.physmem.perBankRdBursts::6 564 # Per bank write bursts +system.physmem.perBankRdBursts::7 560 # Per bank write bursts +system.physmem.perBankRdBursts::8 471 # Per bank write bursts +system.physmem.perBankRdBursts::9 437 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 324 # Per bank write bursts +system.physmem.perBankRdBursts::12 430 # Per bank write bursts +system.physmem.perBankRdBursts::13 556 # Per bank write bursts +system.physmem.perBankRdBursts::14 473 # Per bank write bursts +system.physmem.perBankRdBursts::15 423 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.rdQLenPdf::0 6827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7875 # Read request sizes (log2) +system.physmem.readReqs 7875 # Number of read requests accepted +system.physmem.readRowHitRate 80.58 # Row buffer hit rate for reads +system.physmem.readRowHits 6346 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers +system.physmem.totGap 220684972000 # Total gap between requests +system.physmem.totMemAccLat 200373000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 52716750 # Total ticks spent queuing +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..396ce5f1d --- /dev/null +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/eon +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..956bfed52 --- /dev/null +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr @@ -0,0 +1,57 @@ +warn: Sockets disabled, not accepting gdb connections +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +warn: User mode does not have SPSR +warn: User mode does not have SPSR +col 0. . . +col 1. . . +col 2. . . +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..6f527f164 --- /dev/null +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout @@ -0,0 +1,19 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 12:10:42 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0xc928260 +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Eon, Version 1.1 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +OO-style eon Time= 0.220000 +Exiting @ tick 227450162000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..0a05ac469 --- /dev/null +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,699 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 227445516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 153700 # Simulator instruction rate (inst/s) +host_mem_usage 303376 # Number of bytes of host memory used +host_op_rate 196498 # Simulator op (including micro ops) rate (op/s) +host_seconds 1776.44 # Real time elapsed on the host +host_tick_rate 128034740 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 273037854 # Number of instructions simulated +sim_ops 349065592 # Number of ops (including micro ops) simulated +sim_seconds 0.227446 # Number of seconds simulated +sim_ticks 227445516000 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 83.362247 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 16723894 # Number of BTB hits +system.cpu.branchPred.BTBLookups 20061712 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 121 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1671536 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 21059526 # Number of conditional branches predicted +system.cpu.branchPred.lookups 35363260 # Number of BP lookups +system.cpu.branchPred.usedRAS 6617396 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 273037854 # Number of instructions committed +system.cpu.committedOps 349065592 # Number of ops (including micro ops) committed +system.cpu.cpi 1.666037 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 95145110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 95145110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 95143025 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 95143025 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128748208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128748208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 2085 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2085 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102352040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 102352040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1661 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1661 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 82047473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047473 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 356313750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 356313750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000063 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000063 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 5204 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5204 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2344 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2344 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 196350750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 196350750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 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number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7289 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 2768 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2768 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298702790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298702790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4521 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4521 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed 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# Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 77471042 # number of ReadReq accesses(hits+misses) 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accesses +system.cpu.icache.ReadReq_misses::cpu.inst 41430 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 41430 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 655630002 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 655630002 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 41430 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 41430 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access 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hits +system.cpu.icache.demand_hits::total 77429612 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 739892998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739892998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 41430 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 41430 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 655630002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 655630002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 41430 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 41430 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 77471042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 77471042 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17858.870336 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency +system.cpu.icache.overall_hits::cpu.inst 77429612 # number of overall hits +system.cpu.icache.overall_hits::total 77429612 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 739892998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739892998 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 41430 # number of overall misses +system.cpu.icache.overall_misses::total 41430 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 655630002 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 655630002 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 41430 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 41430 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 288 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1478 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 1868.971300 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 154983513 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1927.026996 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1941 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.947754 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 39488 # number of replacements +system.cpu.icache.tags.sampled_refs 41429 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 154983513 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 1927.026996 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 77429612 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 4029946 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.600227 # IPC: instructions per cycle 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misses +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2860 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2860 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 193299750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 193299750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994406 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994406 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 2844 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2844 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 157555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994406 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994406 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2844 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2844 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 43091 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 43091 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 38266 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 38266 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 332214000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 332214000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111972 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.111972 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 4825 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4825 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 42 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 269721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 269721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.110998 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.110998 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4783 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4783 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 1013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 1013 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1013 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 45951 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 45951 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 38282 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 38282 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 525513750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 525513750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166895 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.166895 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 7669 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7669 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 42 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 427276750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 427276750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165981 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7627 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7627 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 45951 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 45951 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 38282 # number of overall hits +system.cpu.l2cache.overall_hits::total 38282 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 525513750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 525513750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166895 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.166895 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 7669 # number of overall misses +system.cpu.l2cache.overall_misses::total 7669 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 42 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 42 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 427276750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 427276750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165981 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7627 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7627 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4305 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 6.727368 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 384272 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 356.812936 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3883.048925 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010889 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.118501 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.129390 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5700 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173950 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.sampled_refs 5700 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 384272 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 4239.861860 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 38346 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.numCycles 454891032 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 450861086 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 3005632 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 82859 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10055 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 92914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 24495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 62845998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 7514710 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 13214734 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2651456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 354176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 3005632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 43091 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 43090 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2860 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2860 # Transaction distribution +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 488128 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15254 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15254 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 8910000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 71341750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 2146132 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 488128 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 488128 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 4783 # Transaction distribution +system.membus.trans_dist::ReadResp 4783 # Transaction distribution +system.membus.trans_dist::ReadExReq 2844 # Transaction distribution +system.membus.trans_dist::ReadExResp 2844 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 29821084.57 # Average gap between requests +system.physmem.avgMemAccLat 25580.41 # Average memory access latency per DRAM burst +system.physmem.avgQLat 6830.41 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 974721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 974721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2146132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2146132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2146132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2146132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 315.689119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.950751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.584238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 593 38.41% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 326 21.11% 59.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 172 11.14% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 76 4.92% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.60% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 58 3.76% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 38 2.46% 86.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.81% 88.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 182 11.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 488128 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 488128 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 488128 # Number of bytes read from this memory +system.physmem.bytes_read::total 488128 # Number of bytes read from this memory +system.physmem.memoryStateTime::IDLE 217468466000 # Time in different power states +system.physmem.memoryStateTime::REF 7594860000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 2381096500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 7627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7627 # Number of read requests responded to by this memory +system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 637 # Per bank write bursts +system.physmem.perBankRdBursts::1 850 # Per bank write bursts +system.physmem.perBankRdBursts::2 633 # Per bank write bursts +system.physmem.perBankRdBursts::3 541 # Per bank write bursts +system.physmem.perBankRdBursts::4 470 # Per bank write bursts +system.physmem.perBankRdBursts::5 350 # Per bank write bursts +system.physmem.perBankRdBursts::6 175 # Per bank write bursts +system.physmem.perBankRdBursts::7 229 # Per bank write bursts +system.physmem.perBankRdBursts::8 210 # Per bank write bursts +system.physmem.perBankRdBursts::9 309 # Per bank write bursts +system.physmem.perBankRdBursts::10 346 # Per bank write bursts +system.physmem.perBankRdBursts::11 428 # Per bank write bursts +system.physmem.perBankRdBursts::12 552 # Per bank write bursts +system.physmem.perBankRdBursts::13 714 # Per bank write bursts +system.physmem.perBankRdBursts::14 639 # Per bank write bursts +system.physmem.perBankRdBursts::15 544 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.rdQLenPdf::0 6680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 7627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7627 # Read request sizes (log2) +system.physmem.readReqs 7627 # Number of read requests accepted +system.physmem.readRowHitRate 79.70 # Row buffer hit rate for reads +system.physmem.readRowHits 6079 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 38135000 # Total ticks spent in databus transfers +system.physmem.totGap 227445412000 # Total gap between requests +system.physmem.totMemAccLat 195101750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 52095500 # Total ticks spent queuing +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 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+system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini new file mode 100644 index 000000000..0f4e284a7 --- /dev/null +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini @@ -0,0 +1,718 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int 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+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/perlbmk +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr new file mode 100644 index 000000000..b38cab2f9 --- /dev/null +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr @@ -0,0 +1,6 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(0, 1, ...) +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout new file mode 100644 index 000000000..0fcd7392a --- /dev/null +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout @@ -0,0 +1,1390 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:41:53 +gem5 started May 7 2014 15:12:23 +gem5 executing on cz3212c2d7 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. 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b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,659 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 1191522940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 293885 # Simulator instruction rate (inst/s) +host_mem_usage 258084 # Number of bytes of host memory used +host_op_rate 293885 # Simulator op (including micro ops) rate (op/s) +host_seconds 6837.45 # Real time elapsed on the host +host_tick_rate 174264280 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2009421070 # Number of instructions simulated +sim_ops 2009421070 # Number of ops (including micro ops) simulated +sim_seconds 1.191523 # Number of seconds simulated +sim_ticks 1191522940000 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 80.283547 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 179637334 # Number of BTB hits +system.cpu.branchPred.BTBLookups 223753609 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 24504 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 26222048 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 174812836 # Number of conditional branches predicted +system.cpu.branchPred.lookups 271009171 # Number of BP lookups +system.cpu.branchPred.usedRAS 40320873 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 2009421070 # Number of instructions committed +system.cpu.committedOps 2009421070 # Number of ops (including micro ops) committed +system.cpu.cpi 1.185937 # CPI: cycles per instruction +system.cpu.dcache.ReadReq_accesses::cpu.inst 484973463 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 484973463 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 29869.727061 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 29869.727061 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 27793.909016 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27793.909016 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 483514457 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 483514457 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 43580111000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 43580111000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003008 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003008 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 1459006 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1459006 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 621 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 621 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 40534220000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40534220000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1458385 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1458385 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses::cpu.inst 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64653.542435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64653.542435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62992.275671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62992.275671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 210652621 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210652621 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9198582750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9198582750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000675 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000675 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 142275 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 142275 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70327 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 70327 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4532168250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4532168250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 71948 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71948 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 695768359 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 695768359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 32960.294758 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32960.294758 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29448.746286 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29448.746286 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 694167078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694167078 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 52778693750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 52778693750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002301 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002301 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 1601281 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1601281 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 70948 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 70948 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 45066388250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45066388250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002199 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002199 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1530333 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1530333 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 695768359 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 695768359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 32960.294758 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32960.294758 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29448.746286 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29448.746286 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 694167078 # number of overall hits +system.cpu.dcache.overall_hits::total 694167078 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 52778693750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 52778693750 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002301 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002301 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 1601281 # number of overall misses +system.cpu.dcache.overall_misses::total 1601281 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 70948 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 70948 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 45066388250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45066388250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002199 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002199 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1530333 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1530333 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 948 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1258 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1618 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 453.605247 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 1393067051 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.559536 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999648 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999648 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 1526237 # number of replacements +system.cpu.dcache.tags.sampled_refs 1530333 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 1393067051 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 4094.559536 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694167078 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 828837250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 95962 # number of writebacks +system.cpu.dcache.writebacks::total 95962 # number of writebacks +system.cpu.discardedOps 54230447 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dtb.data_accesses 722376032 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 721933722 # DTB hits +system.cpu.dtb.data_misses 442310 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 511558478 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 511131393 # DTB read hits +system.cpu.dtb.read_misses 427085 # DTB read misses +system.cpu.dtb.write_accesses 210817554 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 210802329 # DTB write hits +system.cpu.dtb.write_misses 15225 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 683609242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 683609242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20652.120610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20652.120610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18596.962668 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18596.962668 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 683586607 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 683586607 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 467460750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 467460750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 22635 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 22635 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 420942250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 420942250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 22635 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 22635 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 683609242 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 683609242 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20652.120610 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20652.120610 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18596.962668 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18596.962668 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 683586607 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 683586607 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 467460750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 467460750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 22635 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 22635 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 420942250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 420942250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 22635 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 22635 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 683609242 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 683609242 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20652.120610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20652.120610 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18596.962668 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18596.962668 # average overall mshr miss latency +system.cpu.icache.overall_hits::cpu.inst 683586607 # number of overall hits +system.cpu.icache.overall_hits::total 683586607 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 467460750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 467460750 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 22635 # number of overall misses +system.cpu.icache.overall_misses::total 22635 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 420942250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 420942250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 22635 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 22635 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1573 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 30201.758726 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 1367241118 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1688.672888 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.824547 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.824547 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1741 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 20893 # number of replacements +system.cpu.icache.tags.sampled_refs 22634 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 1367241118 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 1688.672888 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 683586607 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 103732278 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.843215 # IPC: instructions per cycle +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 683609362 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 683609242 # ITB hits +system.cpu.itb.fetch_misses 120 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 71948 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71948 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65940.521766 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65940.521766 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53018.517549 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53018.517549 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 5079 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4409376750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4409376750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.929407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.929407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 66869 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66869 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3545295250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3545295250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.929407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66869 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66869 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1481020 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1481020 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70256.406419 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70256.406419 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57611.646625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57611.646625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 1071704 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1071704 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 28757071250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28757071250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.276374 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.276374 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 409316 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 409316 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23581368750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23581368750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.276374 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.276374 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 409316 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409316 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 95962 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 95962 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 95962 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 95962 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 1552968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1552968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69650.341779 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69650.341779 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56966.649516 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56966.649516 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 1076783 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1076783 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 33166448000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33166448000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.306629 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.306629 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 476185 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 476185 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27126664000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27126664000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.306629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.306629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 476185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 1552968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1552968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69650.341779 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69650.341779 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56966.649516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56966.649516 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 1076783 # number of overall hits +system.cpu.l2cache.overall_hits::total 1076783 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 33166448000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33166448000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.306629 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.306629 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 476185 # number of overall misses +system.cpu.l2cache.overall_misses::total 476185 # number of overall misses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27126664000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27126664000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.306629 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.306629 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 476185 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476185 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2674 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29455 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 2.311701 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 13739527 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 1349.197229 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 31332.044596 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.041174 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956178 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997352 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 443405 # number of replacements +system.cpu.l2cache.tags.sampled_refs 476139 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 13739527 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 32681.241826 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1100691 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks +system.cpu.l2cache.writebacks::total 66908 # number of writebacks +system.cpu.numCycles 2383045880 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 2279313602 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 105531456 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45269 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3201897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 920427000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 34576250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2370536750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 88568547 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1448576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104082880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 105531456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1481020 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1481019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71948 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 71948 # Transaction distribution +system.cpu.workload.num_syscalls 39 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 34757888 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019276 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 1283589500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 4535569500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 29170977 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34757888 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34757888 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 409315 # Transaction distribution +system.membus.trans_dist::ReadResp 409315 # Transaction distribution +system.membus.trans_dist::Writeback 66908 # Transaction distribution +system.membus.trans_dist::ReadExReq 66869 # Transaction distribution +system.membus.trans_dist::ReadExResp 66869 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 2193961.36 # Average gap between requests +system.physmem.avgMemAccLat 26986.02 # Average memory access latency per DRAM burst +system.physmem.avgQLat 8236.02 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 25.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 3.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.59 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 24.44 # Average write queue length when enqueuing +system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 156519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 25577163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25577163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3593814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25577163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29170977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3593814 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3593814 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 196329 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 176.935328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 127.479402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 206.642311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 75423 38.42% 38.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 90953 46.33% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 17208 8.76% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 945 0.48% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 960 0.49% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 641 0.33% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1086 0.55% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 966 0.49% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8147 4.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 196329 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 30457664 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 30475776 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue +system.physmem.bytesWritten 4280512 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 186496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186496 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 30475776 # Number of bytes read from this memory +system.physmem.bytes_read::total 30475776 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory +system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 593665055500 # Time in different power states +system.physmem.memoryStateTime::REF 39787540000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 558069752500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 476184 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476184 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory +system.physmem.pageHitRate 63.83 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 29463 # Per bank write bursts +system.physmem.perBankRdBursts::1 29813 # Per bank write bursts +system.physmem.perBankRdBursts::2 29826 # Per bank write bursts +system.physmem.perBankRdBursts::3 29780 # Per bank write bursts +system.physmem.perBankRdBursts::4 29692 # Per bank write bursts +system.physmem.perBankRdBursts::5 29773 # Per bank write bursts +system.physmem.perBankRdBursts::6 29849 # Per bank write bursts +system.physmem.perBankRdBursts::7 29830 # Per bank write bursts +system.physmem.perBankRdBursts::8 29753 # Per bank write bursts +system.physmem.perBankRdBursts::9 29878 # Per bank write bursts +system.physmem.perBankRdBursts::10 29844 # Per bank write bursts +system.physmem.perBankRdBursts::11 29908 # Per bank write bursts +system.physmem.perBankRdBursts::12 29785 # Per bank write bursts +system.physmem.perBankRdBursts::13 29573 # Per bank write bursts +system.physmem.perBankRdBursts::14 29507 # Per bank write bursts +system.physmem.perBankRdBursts::15 29627 # Per bank write bursts +system.physmem.perBankWrBursts::0 4125 # Per bank write bursts +system.physmem.perBankWrBursts::1 4164 # Per bank write bursts +system.physmem.perBankWrBursts::2 4223 # Per bank write bursts +system.physmem.perBankWrBursts::3 4160 # Per bank write bursts +system.physmem.perBankWrBursts::4 4142 # Per bank write bursts +system.physmem.perBankWrBursts::5 4099 # Per bank write bursts +system.physmem.perBankWrBursts::6 4262 # Per bank write bursts +system.physmem.perBankWrBursts::7 4226 # Per bank write bursts +system.physmem.perBankWrBursts::8 4233 # Per bank write bursts +system.physmem.perBankWrBursts::9 4334 # Per bank write bursts +system.physmem.perBankWrBursts::10 4223 # Per bank write bursts +system.physmem.perBankWrBursts::11 4241 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4100 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4157 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 4057 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 115.306631 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.801532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1128.564145 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4038 99.53% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 6 0.15% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 12 0.30% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4057 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 475416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 476184 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 476184 # Read request sizes (log2) +system.physmem.readReqs 476184 # Number of read requests accepted +system.physmem.readRowHitRate 62.16 # Row buffer hit rate for reads +system.physmem.readRowHits 295815 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 2379505000 # Total ticks spent in databus transfers +system.physmem.totGap 1191522864500 # Total gap between requests +system.physmem.totMemAccLat 12842674500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3919530750 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 4057 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.485827 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.464369 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.858223 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3072 75.72% 75.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 984 24.25% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4057 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66908 # Write request sizes (log2) +system.physmem.writeReqs 66908 # Number of write requests accepted +system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes +system.physmem.writeRowHits 50635 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..67ce4f8b9 --- /dev/null +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/perlbmk +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..2de5e2759 --- /dev/null +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: fcntl64(3, 2) passed through to host diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..ca66069ba --- /dev/null +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout @@ -0,0 +1,1391 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 14:12:56 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x1273de40 +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +1375000: 2038431008 +1374000: 3487365506 +1373000: 4184770123 +1372000: 1943746837 +1371000: 2651673663 +1370000: 1493817016 +1369000: 2894014801 +1368000: 1932092157 +1367000: 1670009799 +1366000: 828662248 +1365000: 1816650195 +1364000: 4173139012 +1363000: 3990577549 +1362000: 1330366815 +1361000: 3316935553 +1360000: 961300001 +1359000: 344963924 +1358000: 1930356625 +1357000: 1640964266 +1356000: 3777883312 +1355000: 1651132665 +1354000: 1971433151 +1353000: 3024027448 +1352000: 1956387036 +1351000: 1490224841 +1350000: 3286956460 +1349000: 2793131848 +1348000: 2529224907 +1347000: 2622295253 +1346000: 1414103189 +1345000: 3861617587 +1344000: 3506378216 +1343000: 1667466720 +1342000: 2899224065 +1341000: 1681491556 +1340000: 1076311729 +1339000: 4066972664 +1338000: 3438059028 +1337000: 2938359730 +1336000: 1214615378 +1335000: 3814432458 +1334000: 2944038793 +1333000: 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4163248735 +35000: 943584186 +34000: 387069186 +33000: 3519377243 +32000: 3861206003 +31000: 2378381393 +30000: 3259365221 +29000: 3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 +Exiting @ tick 1253145998500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..3a1bb990b --- /dev/null +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,725 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 1252658454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 126529 # Simulator instruction rate (inst/s) +host_mem_usage 303852 # Number of bytes of host memory used +host_op_rate 172315 # Simulator op (including micro ops) rate (op/s) +host_seconds 10941.24 # Real time elapsed on the host +host_tick_rate 114489637 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1384383018 # Number of instructions simulated +sim_ops 1885337770 # Number of ops (including micro ops) simulated +sim_seconds 1.252658 # Number of seconds simulated +sim_ticks 1252658454500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 92.275361 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 183176705 # Number of BTB hits +system.cpu.branchPred.BTBLookups 198510960 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 2809 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 27775706 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 271023918 # Number of conditional branches predicted +system.cpu.branchPred.lookups 347774230 # Number of BP lookups +system.cpu.branchPred.usedRAS 40383236 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 1384383018 # Number of instructions committed +system.cpu.committedOps 1885337770 # Number of ops (including micro ops) committed +system.cpu.cpi 1.809699 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 9985 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 622157845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 622157845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30504.122168 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30504.122168 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28441.732178 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28441.732178 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 620694666 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 620694666 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 44632990969 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44632990969 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002352 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002352 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 1463179 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1463179 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 1721 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1721 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41566397026 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41566397026 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1461458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1461458 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 9985 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64418.412606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64418.412606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62661.295309 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62661.295309 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 276792059 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276792059 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9251708000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9251708000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000519 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000519 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 143619 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 143619 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70841 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 70841 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4560363750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4560363750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 72778 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72778 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 899093523 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 899093523 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33535.453099 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 897486725 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 897486725 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 53884698969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53884698969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.001787 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001787 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 1606798 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1606798 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 72562 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72562 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 46126760776 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46126760776 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001706 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1534236 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534236 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 899093523 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 899093523 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33535.453099 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 897486725 # number of overall hits +system.cpu.dcache.overall_hits::total 897486725 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 53884698969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53884698969 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.001787 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001787 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 1606798 # number of overall misses +system.cpu.dcache.overall_misses::total 1606798 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 72562 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72562 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 46126760776 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46126760776 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001706 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1534236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534236 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1240 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1699 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 584.986075 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 1799761222 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.531713 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999642 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999642 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 1530140 # number of replacements +system.cpu.dcache.tags.sampled_refs 1534236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 1799761222 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 4094.531713 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 897506695 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 756574250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 96100 # number of writebacks +system.cpu.dcache.writebacks::total 96100 # number of writebacks +system.cpu.discardedOps 58655042 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 655834828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 655834828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15794.863845 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15794.863845 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13774.677486 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13774.677486 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 655779494 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 655779494 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 873992996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 873992996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 55334 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 55334 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 762208004 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 762208004 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadReq accesses 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1727.262157 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 655779494 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 103571975 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.552578 # IPC: instructions per cycle +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times 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# Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 72778 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72778 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66889.147375 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66889.147375 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54354.270691 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54354.270691 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 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1107826 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29733407500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29733407500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269626 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.269626 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 408966 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 408966 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 30 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24591047000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24591047000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269606 # mshr miss rate for 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(read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 34154111250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34154111250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.298858 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.298858 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 475056 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 475056 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 30 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28183320750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28183320750 # number of demand (read+write) MSHR miss cycles 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 1114514 # number of overall hits +system.cpu.l2cache.overall_hits::total 1114514 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 34154111250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34154111250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.298858 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.298858 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 475056 # number of overall misses +system.cpu.l2cache.overall_misses::total 475056 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 30 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28183320750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28183320750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.298839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 475026 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 475026 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2580 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29670 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 2.395162 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 14033128 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 1330.818076 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 31344.832788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.040613 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956568 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997182 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 442246 # number of replacements +system.cpu.l2cache.tags.sampled_refs 474990 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 14033128 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 32675.650864 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1137678 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks +system.cpu.l2cache.writebacks::total 66099 # number of writebacks +system.cpu.numCycles 2505316909 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 2401744934 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 107882816 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 110667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3164572 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3275239 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 938935000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 83558996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2375968224 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 86123089 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3541312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104341504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 107882816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1516792 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1516791 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72778 # Transaction distribution +system.cpu.workload.num_syscalls 1411 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 34631936 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1016149 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1016149 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 1205459500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 4468586250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 27646751 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34631936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34631936 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 408935 # Transaction distribution +system.membus.trans_dist::ReadResp 408935 # Transaction distribution +system.membus.trans_dist::Writeback 66099 # Transaction distribution +system.membus.trans_dist::ReadExReq 66090 # Transaction distribution +system.membus.trans_dist::ReadExResp 66090 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 2314919.25 # Average gap between requests +system.physmem.avgMemAccLat 29362.18 # Average memory access latency per DRAM burst +system.physmem.avgQLat 10612.18 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 24.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 24.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.38 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 26.46 # Average write queue length when enqueuing +system.physmem.busUtil 0.22 # Data bus utilization in percentage +system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 133348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 133348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 24269664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 24269664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3377087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 24269664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 27646751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3377087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3377087 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 204371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 169.307779 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 122.893449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.869772 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 84097 41.15% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 91184 44.62% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16888 8.26% 94.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 803 0.39% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1089 0.53% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1331 0.65% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 576 0.28% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 520 0.25% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7883 3.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 204371 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 30374976 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 30401600 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 26624 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 4230336 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 30401600 # Number of bytes read from this memory +system.physmem.bytes_read::total 30401600 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 639262116250 # Time in different power states +system.physmem.memoryStateTime::REF 41828800000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 571561257500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 475025 # Number of read requests responded to by this memory +system.physmem.num_reads::total 475025 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.pageHitRate 62.20 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 29837 # Per bank write bursts +system.physmem.perBankRdBursts::1 29647 # Per bank write bursts +system.physmem.perBankRdBursts::2 29757 # Per bank write bursts +system.physmem.perBankRdBursts::3 29702 # Per bank write bursts +system.physmem.perBankRdBursts::4 29776 # Per bank write bursts +system.physmem.perBankRdBursts::5 29847 # Per bank write bursts +system.physmem.perBankRdBursts::6 29613 # Per bank write bursts +system.physmem.perBankRdBursts::7 29430 # Per bank write bursts +system.physmem.perBankRdBursts::8 29457 # Per bank write bursts +system.physmem.perBankRdBursts::9 29488 # Per bank write bursts +system.physmem.perBankRdBursts::10 29541 # Per bank write bursts +system.physmem.perBankRdBursts::11 29643 # Per bank write bursts +system.physmem.perBankRdBursts::12 29678 # Per bank write bursts +system.physmem.perBankRdBursts::13 29796 # Per bank write bursts +system.physmem.perBankRdBursts::14 29601 # Per bank write bursts +system.physmem.perBankRdBursts::15 29796 # Per bank write bursts +system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankWrBursts::1 4100 # Per bank write bursts +system.physmem.perBankWrBursts::2 4137 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4224 # Per bank write bursts +system.physmem.perBankWrBursts::5 4225 # Per bank write bursts +system.physmem.perBankWrBursts::6 4171 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4093 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::14 4094 # Per bank write bursts +system.physmem.perBankWrBursts::15 4138 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.067006 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 508.980201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 474221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 475025 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 475025 # Read request sizes (log2) +system.physmem.readReqs 475025 # Number of read requests accepted +system.physmem.readRowHitRate 60.31 # Row buffer hit rate for reads +system.physmem.readRowHits 286253 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 416 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 2373045000 # Total ticks spent in databus transfers +system.physmem.totGap 1252658366500 # Total gap between requests +system.physmem.totMemAccLat 13935557250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 5036638500 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.489144 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.467620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859483 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3026 75.52% 75.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2 0.05% 75.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 66099 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66099 # Write request sizes (log2) +system.physmem.writeReqs 66099 # Number of write requests accepted +system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes +system.physmem.writeRowHits 50044 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini new file mode 100644 index 000000000..608f400a3 --- /dev/null +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini @@ -0,0 +1,718 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr new file mode 100644 index 000000000..506aa6e28 --- /dev/null +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout new file mode 100644 index 000000000..bfc5e794b --- /dev/null +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout @@ -0,0 +1,13 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:41:53 +gem5 started May 7 2014 11:01:25 +gem5 executing on cz3212c2d7 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 58222132000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt new file mode 100644 index 000000000..8796e7316 --- /dev/null +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,660 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 58437370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 298644 # Simulator instruction rate (inst/s) +host_mem_usage 257212 # Number of bytes of host memory used +host_op_rate 298644 # Simulator op (including micro ops) rate (op/s) +host_seconds 296.13 # Real time elapsed on the host +host_tick_rate 197335322 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 88438073 # Number of instructions simulated +sim_ops 88438073 # Number of ops (including micro ops) simulated +sim_seconds 0.058437 # Number of seconds simulated +sim_ticks 58437370000 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 63.309910 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 6368851 # Number of BTB hits +system.cpu.branchPred.BTBLookups 10059801 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 72966 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 375118 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 9451361 # Number of conditional branches predicted +system.cpu.branchPred.lookups 14600308 # Number of BP lookups +system.cpu.branchPred.usedRAS 1701571 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 88438073 # Number of instructions committed +system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed +system.cpu.cpi 1.321543 # CPI: cycles per instruction +system.cpu.dcache.ReadReq_accesses::cpu.inst 20357517 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20357517 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49316.405682 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49316.405682 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39545.722557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39545.722557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 20268112 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20268112 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4409133250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4409133250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004392 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004392 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 89405 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89405 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28095 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28095 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2424548250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2424548250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses 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ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7976415750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 215815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 215815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72877.172362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72877.172362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60213.094339 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60213.094339 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 180082 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 180082 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2604120000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2604120000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.165572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 35733 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35733 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2151594500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2151594500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35733 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35733 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 168548 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168548 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 168548 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168548 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 359381 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 359381 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73615.868114 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73615.868114 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.270277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60787.270277 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 192767 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 192767 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 12265434250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12265434250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463614 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.463614 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 166614 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166614 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10128010250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10128010250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.463614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 166614 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166614 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 359381 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 359381 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73615.868114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73615.868114 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.270277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60787.270277 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 192767 # number of overall hits +system.cpu.l2cache.overall_hits::total 192767 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 12265434250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12265434250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463614 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.463614 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 166614 # number of overall misses +system.cpu.l2cache.overall_misses::total 166614 # number of overall misses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10128010250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10128010250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.463614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 166614 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166614 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 993 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12007 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18840 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 1.331233 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 4531761 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 26227.699402 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4243.729621 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.800406 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129508 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.929914 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 132687 # number of replacements +system.cpu.l2cache.tags.sampled_refs 164763 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 4531761 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 30471.429023 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 219338 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 114047 # number of writebacks +system.cpu.l2cache.writebacks::total 114047 # number of writebacks +system.cpu.numCycles 116874740 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 91164624 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 33787392 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887309 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 432512500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 233318246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 343226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 578181256 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9888320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 33787392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 215815 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 215814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168548 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143566 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143566 # Transaction distribution +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 17962240 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447273 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 1301422000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1600112750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 307375914 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17962240 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 35732 # Transaction distribution +system.membus.trans_dist::ReadResp 35732 # Transaction distribution +system.membus.trans_dist::Writeback 114047 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 208214.01 # Average gap between requests +system.physmem.avgMemAccLat 30471.23 # Average memory access latency per DRAM burst +system.physmem.avgQLat 11721.23 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 182.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 182.47 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 124.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 124.90 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 24.17 # Average write queue length when enqueuing +system.physmem.busUtil 2.40 # Data bus utilization in percentage +system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 8825038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8825038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 182472825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 182472825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 124903089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 182472825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 307375914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 124903089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 124903089 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 54430 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.948631 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.734417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.314792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19369 35.59% 35.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11718 21.53% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5622 10.33% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3646 6.70% 74.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2769 5.09% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2059 3.78% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1651 3.03% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1489 2.74% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6107 11.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54430 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 10662720 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 10663232 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7296960 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 515712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515712 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 10663232 # Number of bytes read from this memory +system.physmem.bytes_read::total 10663232 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 31940805250 # Time in different power states +system.physmem.memoryStateTime::REF 1951300000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 24543978500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 166613 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166613 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory +system.physmem.pageHitRate 80.59 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 10468 # Per bank write bursts +system.physmem.perBankRdBursts::1 10509 # Per bank write bursts +system.physmem.perBankRdBursts::2 10311 # Per bank write bursts +system.physmem.perBankRdBursts::3 10091 # Per bank write bursts +system.physmem.perBankRdBursts::4 10432 # Per bank write bursts +system.physmem.perBankRdBursts::5 10432 # Per bank write bursts +system.physmem.perBankRdBursts::6 9848 # Per bank write bursts +system.physmem.perBankRdBursts::7 10303 # Per bank write bursts +system.physmem.perBankRdBursts::8 10590 # Per bank write bursts +system.physmem.perBankRdBursts::9 10643 # Per bank write bursts +system.physmem.perBankRdBursts::10 10591 # Per bank write bursts +system.physmem.perBankRdBursts::11 10256 # Per bank write bursts +system.physmem.perBankRdBursts::12 10303 # Per bank write bursts +system.physmem.perBankRdBursts::13 10654 # Per bank write bursts +system.physmem.perBankRdBursts::14 10527 # Per bank write bursts +system.physmem.perBankRdBursts::15 10647 # Per bank write bursts +system.physmem.perBankWrBursts::0 7087 # Per bank write bursts +system.physmem.perBankWrBursts::1 7261 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::4 7126 # Per bank write bursts +system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::6 6771 # Per bank write bursts +system.physmem.perBankWrBursts::7 7085 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6938 # Per bank write bursts +system.physmem.perBankWrBursts::10 7096 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 6965 # Per bank write bursts +system.physmem.perBankWrBursts::13 7289 # Per bank write bursts +system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 7018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.736820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.923098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7017 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7018 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 164979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 166613 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 166613 # Read request sizes (log2) +system.physmem.readReqs 166613 # Number of read requests accepted +system.physmem.readRowHitRate 86.96 # Row buffer hit rate for reads +system.physmem.readRowHits 144887 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 833025000 # Total ticks spent in databus transfers +system.physmem.totGap 58437343500 # Total gap between requests +system.physmem.totMemAccLat 5076659000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1952815250 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.246082 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.230651 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.740530 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 89.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 591 8.42% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 122 1.74% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.37% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 114047 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114047 # Write request sizes (log2) +system.physmem.writeReqs 114047 # Number of write requests accepted +system.physmem.writeRowHitRate 71.29 # Row buffer hit rate for writes +system.physmem.writeRowHits 81299 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..4cb5c8ea2 --- /dev/null +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..1a4f96712 --- /dev/null +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..0b495a4c8 --- /dev/null +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -0,0 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 17:09:29 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0xcee8df0 +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 64581408500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..ce74a2918 --- /dev/null +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,729 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 178791 # Simulator instruction rate (inst/s) +host_mem_usage 302756 # Number of bytes of host memory used +host_op_rate 253719 # Simulator op (including micro ops) rate (op/s) +host_seconds 396.64 # Real time elapsed on the host +host_tick_rate 162280857 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 70915127 # Number of instructions simulated +sim_ops 100634375 # Number of ops (including micro ops) simulated +sim_seconds 0.064367 # Number of seconds simulated +sim_ticks 64366581500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits +system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted +system.cpu.branchPred.lookups 16883830 # Number of BP lookups +system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 70915127 # Number of instructions committed +system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed +system.cpu.cpi 1.815313 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38199.338598 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38199.338598 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.609683 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.609683 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169340439 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2169340439 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001786311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001786311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73771.399808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73771.399808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.202050 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.202050 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315459000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15315459000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591658250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591658250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.854128 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66130.854128 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59601.049701 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59601.049701 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 17484799439 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17484799439 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593444561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9593444561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.854128 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66130.854128 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59601.049701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59601.049701 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits +system.cpu.dcache.overall_hits::total 47220249 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 17484799439 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17484799439 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses +system.cpu.dcache.overall_misses::total 264397 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593444561 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9593444561 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 156865 # number of replacements +system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks +system.cpu.dcache.writebacks::total 128565 # number of writebacks +system.cpu.discardedOps 2952330 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 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due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19971.672117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19971.672117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17929.897070 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17929.897070 # average ReadReq mshr miss latency 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54991298 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 1864.297147 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 19565206 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.550869 # IPC: instructions per cycle +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 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due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.821477 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.821477 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.466837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.466837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436940250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7436940250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6118068750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6118068750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102267 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102267 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74187.493019 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74187.493019 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61477.049578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61477.049578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits 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(read+write) hits +system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 9429393750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9429393750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 129124 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 129124 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7764793000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7764793000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 129053 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 129053 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73025.880162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73025.880162 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60167.473829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60167.473829 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits +system.cpu.l2cache.overall_hits::total 77402 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 9429393750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9429393750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses +system.cpu.l2cache.overall_misses::total 129124 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7764793000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7764793000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 129053 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 129053 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 26739.141291 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.835051 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 95911 # number of replacements +system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 30027.976342 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 83957 # number of writebacks +system.cpu.l2cache.writebacks::total 83957 # number of writebacks +system.cpu.numCycles 128733163 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 109167957 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 269478939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 13632576 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 975516000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1243562500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 211795868 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 26785 # Transaction distribution +system.membus.trans_dist::ReadResp 26785 # Transaction distribution +system.membus.trans_dist::Writeback 83957 # Transaction distribution +system.membus.trans_dist::ReadExReq 102267 # Transaction distribution +system.membus.trans_dist::ReadExResp 102267 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 302177.61 # Average gap between requests +system.physmem.avgMemAccLat 30050.93 # Average memory access latency per DRAM burst +system.physmem.avgQLat 11300.93 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing +system.physmem.busUtil 1.65 # Data bus utilization in percentage +system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.915649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.657943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2766 7.13% 71.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2568 6.62% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1673 4.31% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1314 3.38% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1198 3.09% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4478 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory +system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory +system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 37439884750 # Time in different power states +system.physmem.memoryStateTime::REF 2149160000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 24772371500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory +system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory +system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 8196 # Per bank write bursts +system.physmem.perBankRdBursts::1 8381 # Per bank write bursts +system.physmem.perBankRdBursts::2 8249 # Per bank write bursts +system.physmem.perBankRdBursts::3 8185 # Per bank write bursts +system.physmem.perBankRdBursts::4 8327 # Per bank write bursts +system.physmem.perBankRdBursts::5 8459 # Per bank write bursts +system.physmem.perBankRdBursts::6 8094 # Per bank write bursts +system.physmem.perBankRdBursts::7 7981 # Per bank write bursts +system.physmem.perBankRdBursts::8 8076 # Per bank write bursts +system.physmem.perBankRdBursts::9 7644 # Per bank write bursts +system.physmem.perBankRdBursts::10 7831 # Per bank write bursts +system.physmem.perBankRdBursts::11 7843 # Per bank write bursts +system.physmem.perBankRdBursts::12 7891 # Per bank write bursts +system.physmem.perBankRdBursts::13 7884 # Per bank write bursts +system.physmem.perBankRdBursts::14 7977 # Per bank write bursts +system.physmem.perBankRdBursts::15 8027 # Per bank write bursts +system.physmem.perBankWrBursts::0 5181 # Per bank write bursts +system.physmem.perBankWrBursts::1 5375 # Per bank write bursts +system.physmem.perBankWrBursts::2 5284 # Per bank write bursts +system.physmem.perBankWrBursts::3 5155 # Per bank write bursts +system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::5 5517 # Per bank write bursts +system.physmem.perBankWrBursts::6 5201 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::8 5034 # Per bank write bursts +system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5146 # Per bank write bursts +system.physmem.perBankWrBursts::12 5344 # Per bank write bursts +system.physmem.perBankWrBursts::13 5363 # Per bank write bursts +system.physmem.perBankWrBursts::14 5451 # Per bank write bursts +system.physmem.perBankWrBursts::15 5227 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 129052 # Read request sizes (log2) +system.physmem.readReqs 129052 # Number of read requests accepted +system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads +system.physmem.readRowHits 112129 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers +system.physmem.totGap 64366550000 # Total gap between requests +system.physmem.totMemAccLat 3877921750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1458328000 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 83957 # Write request sizes (log2) +system.physmem.writeReqs 83957 # Number of write requests accepted +system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes +system.physmem.writeRowHits 62016 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini new file mode 100644 index 000000000..18aec7159 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini @@ -0,0 +1,718 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=bzip2 input.source 1 +cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/bzip2 +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr new file mode 100644 index 000000000..506aa6e28 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout new file mode 100644 index 000000000..f1d88cff2 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout @@ -0,0 +1,28 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:41:53 +gem5 started May 7 2014 12:11:11 +gem5 executing on cz3212c2d7 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 1184839137500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt new file mode 100644 index 000000000..8b5bdef98 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,669 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 1183291184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 268503 # Simulator instruction rate (inst/s) +host_mem_usage 248104 # Number of bytes of host memory used +host_op_rate 268503 # Simulator op (including micro ops) rate (op/s) +host_seconds 6802.08 # Real time elapsed on the host +host_tick_rate 173960186 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1826378509 # Number of instructions simulated +sim_ops 1826378509 # Number of ops (including micro ops) simulated +sim_seconds 1.183291 # Number of seconds simulated +sim_ticks 1183291184500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.726550 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 164028132 # Number of BTB hits +system.cpu.branchPred.BTBLookups 166143892 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 101063 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 15659000 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 184956948 # Number of conditional branches predicted +system.cpu.branchPred.lookups 244507485 # Number of BP lookups +system.cpu.branchPred.usedRAS 18318035 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 1826378509 # Number of instructions committed +system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed +system.cpu.cpi 1.295779 # CPI: cycles per instruction +system.cpu.dcache.ReadReq_accesses::cpu.inst 448787942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 448787942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24412.387640 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24412.387640 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22378.762178 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22378.762178 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 441498317 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 441498317 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177957151250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177957151250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016243 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016243 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 7289625 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289625 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50799 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50799 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 161995965500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 161995965500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016130 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016130 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238826 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238826 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45036.490101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45036.490101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40206.712752 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40206.712752 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 158490258 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158490258 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100802653750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 100802653750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013926 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013926 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238244 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238244 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350933 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 350933 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75882571250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75882571250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887311 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887311 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 609516444 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 609516444 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29257.308743 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29257.308743 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26065.632890 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26065.632890 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 599988575 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 599988575 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 278759805000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 278759805000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015632 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015632 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 9527869 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9527869 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 401732 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 401732 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237878536750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 237878536750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014973 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014973 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126137 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 609516444 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 609516444 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29257.308743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29257.308743 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26065.632890 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26065.632890 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 599988575 # number of overall hits +system.cpu.dcache.overall_hits::total 599988575 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 278759805000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 278759805000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015632 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015632 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 9527869 # number of overall misses +system.cpu.dcache.overall_misses::total 9527869 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 401732 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 401732 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237878536750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 237878536750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014973 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014973 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126137 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1591 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2338 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 65.743981 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 1228159025 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.562725 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.996231 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996231 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 9122041 # number of replacements +system.cpu.dcache.tags.sampled_refs 9126137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 1228159025 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 4080.562725 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 599988575 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16716397000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 3700613 # number of writebacks +system.cpu.dcache.writebacks::total 3700613 # number of writebacks +system.cpu.discardedOps 50078248 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dtb.data_accesses 620722700 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 614030991 # DTB hits +system.cpu.dtb.data_misses 6691709 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 457660877 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 452677890 # DTB read hits +system.cpu.dtb.read_misses 4982987 # DTB read misses +system.cpu.dtb.write_accesses 163061823 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 161353101 # DTB write hits +system.cpu.dtb.write_misses 1708722 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 592077907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 592077907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74367.693111 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74367.693111 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71956.941545 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71956.941545 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 592076949 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 592076949 # number of ReadReq hits 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+system.cpu.icache.demand_avg_miss_latency::total 74367.693111 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71956.941545 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71956.941545 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 592076949 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 592076949 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 71244250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71244250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68934750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 68934750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 592077907 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 592077907 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74367.693111 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74367.693111 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71956.941545 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71956.941545 # average overall mshr miss latency +system.cpu.icache.overall_hits::cpu.inst 592076949 # number of overall hits +system.cpu.icache.overall_hits::total 592076949 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 71244250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71244250 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses +system.cpu.icache.overall_misses::total 958 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68934750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 68934750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 618034.393528 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 1184156772 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 750.687488 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366547 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366547 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 1184156772 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 750.687488 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 592076949 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 321001841 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.771737 # IPC: instructions per cycle +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 592077926 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 592077907 # ITB hits +system.cpu.itb.fetch_misses 19 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887311 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1887311 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80641.484731 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80641.484731 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68018.096944 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68018.096944 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107870 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107870 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 62855279500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 62855279500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 779441 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 779441 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53016093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53016093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779441 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779441 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239784 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7239784 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79744.744851 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79744.744851 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67168.011379 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67168.011379 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 6058181 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6058181 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94226629750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94226629750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 1181603 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1181603 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79365923750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79365923750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181603 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181603 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 3700613 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700613 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 3700613 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700613 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 9127095 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9127095 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80101.165119 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80101.165119 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67505.888318 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67505.888318 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 7166051 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7166051 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 157081909250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 157081909250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214860 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214860 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 1961044 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1961044 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132382017250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 132382017250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214860 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 9127095 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9127095 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80101.165119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80101.165119 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67505.888318 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67505.888318 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 7166051 # number of overall hits +system.cpu.l2cache.overall_hits::total 7166051 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 157081909250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 157081909250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214860 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214860 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 1961044 # number of overall misses +system.cpu.l2cache.overall_misses::total 1961044 # number of overall misses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132382017250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 132382017250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214860 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961044 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961044 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1231 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12870 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15515 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 4.586945 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 106467088 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 14930.905733 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15810.667479 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455655 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938158 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 1928309 # number of replacements +system.cpu.l2cache.tags.sampled_refs 1958113 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 106467088 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 30741.573213 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8981756 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 88668325250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 1018252 # number of writebacks +system.cpu.l2cache.writebacks::total 1018252 # number of writebacks +system.cpu.numCycles 2366582369 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 2045580528 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 820973312 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954803 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10114467000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1633750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14012915250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 693804976 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820912000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 820973312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887311 # Transaction distribution +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 190674944 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940340 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940340 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 11933306500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 18491731750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 161139495 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190674944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190674944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1181603 # Transaction distribution +system.membus.trans_dist::ReadResp 1181603 # Transaction distribution +system.membus.trans_dist::Writeback 1018252 # Transaction distribution +system.membus.trans_dist::ReadExReq 779441 # Transaction distribution +system.membus.trans_dist::ReadExResp 779441 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 397171.37 # Average gap between requests +system.physmem.avgMemAccLat 37373.81 # Average memory access latency per DRAM burst +system.physmem.avgQLat 18623.81 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 106.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.07 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrBW 55.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 55.07 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing +system.physmem.busUtil 1.26 # Data bus utilization in percentage +system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 51815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 106065876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106065876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55073619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106065876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 161139495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 55073619 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55073619 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1832587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.000528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.206567 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.424181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1451916 79.23% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 263842 14.40% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49021 2.67% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20912 1.14% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12920 0.71% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7284 0.40% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5395 0.29% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4101 0.22% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17196 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1832587 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 125427328 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 125506816 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 79488 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166528 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 65168128 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 125506816 # Number of bytes read from this memory +system.physmem.bytes_read::total 125506816 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 65168128 # Number of bytes written to this memory +system.physmem.bytes_written::total 65168128 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 388135850750 # Time in different power states +system.physmem.memoryStateTime::REF 39512460000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 755636161750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 1961044 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961044 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018252 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018252 # Number of write requests responded to by this memory +system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 118755 # Per bank write bursts +system.physmem.perBankRdBursts::1 114099 # Per bank write bursts +system.physmem.perBankRdBursts::2 116230 # Per bank write bursts +system.physmem.perBankRdBursts::3 117769 # Per bank write bursts +system.physmem.perBankRdBursts::4 117839 # Per bank write bursts +system.physmem.perBankRdBursts::5 117521 # Per bank write bursts +system.physmem.perBankRdBursts::6 119889 # Per bank write bursts +system.physmem.perBankRdBursts::7 124535 # Per bank write bursts +system.physmem.perBankRdBursts::8 126979 # Per bank write bursts +system.physmem.perBankRdBursts::9 130093 # Per bank write bursts +system.physmem.perBankRdBursts::10 128642 # Per bank write bursts +system.physmem.perBankRdBursts::11 130358 # Per bank write bursts +system.physmem.perBankRdBursts::12 126048 # Per bank write bursts +system.physmem.perBankRdBursts::13 125260 # Per bank write bursts +system.physmem.perBankRdBursts::14 122592 # Per bank write bursts +system.physmem.perBankRdBursts::15 123193 # Per bank write bursts +system.physmem.perBankWrBursts::0 61221 # Per bank write bursts +system.physmem.perBankWrBursts::1 61486 # Per bank write bursts +system.physmem.perBankWrBursts::2 60571 # Per bank write bursts +system.physmem.perBankWrBursts::3 61239 # Per bank write bursts +system.physmem.perBankWrBursts::4 61663 # Per bank write bursts +system.physmem.perBankWrBursts::5 63103 # Per bank write bursts +system.physmem.perBankWrBursts::6 64150 # Per bank write bursts +system.physmem.perBankWrBursts::7 65615 # Per bank write bursts +system.physmem.perBankWrBursts::8 65333 # Per bank write bursts +system.physmem.perBankWrBursts::9 65778 # Per bank write bursts +system.physmem.perBankWrBursts::10 65294 # Per bank write bursts +system.physmem.perBankWrBursts::11 65644 # Per bank write bursts +system.physmem.perBankWrBursts::12 64163 # Per bank write bursts +system.physmem.perBankWrBursts::13 64209 # Per bank write bursts +system.physmem.perBankWrBursts::14 64571 # Per bank write bursts +system.physmem.perBankWrBursts::15 64187 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 59249 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.075495 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 165.201868 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59213 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 59249 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 1833824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 1961044 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1961044 # Read request sizes (log2) +system.physmem.readReqs 1961044 # Number of read requests accepted +system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads +system.physmem.readRowHits 729960 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 1242 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 9799010000 # Total ticks spent in databus transfers +system.physmem.totGap 1183291074500 # Total gap between requests +system.physmem.totMemAccLat 73245258000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 36498970500 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 59249 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.185556 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.149947 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.108422 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 25999 43.88% 43.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1383 2.33% 46.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 27359 46.18% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4006 6.76% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 414 0.70% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 70 0.12% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59249 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 59953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 1018252 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1018252 # Write request sizes (log2) +system.physmem.writeReqs 1018252 # Number of write requests accepted +system.physmem.writeRowHitRate 40.80 # Row buffer hit rate for writes +system.physmem.writeRowHits 415473 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..f226b0fa2 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=bzip2 input.source 1 +cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/bzip2 +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..5d8946ede --- /dev/null +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..903745948 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout @@ -0,0 +1,30 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 11:11:49 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x1f2b7940 +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 1135900642500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..7b16ef532 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,733 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 1134079016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 227824 # Simulator instruction rate (inst/s) +host_mem_usage 293824 # Number of bytes of host memory used +host_op_rate 254155 # Simulator op (including micro ops) rate (op/s) +host_seconds 6779.62 # Real time elapsed on the host +host_tick_rate 167277674 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1544563087 # Number of instructions simulated +sim_ops 1723073900 # Number of ops (including micro ops) simulated +sim_seconds 1.134079 # Number of seconds simulated +sim_ticks 1134079016500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 87.938151 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 122192107 # Number of BTB hits +system.cpu.branchPred.BTBLookups 138952327 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 14597136 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 197361074 # Number of conditional branches predicted +system.cpu.branchPred.lookups 250285818 # Number of BP lookups +system.cpu.branchPred.usedRAS 13226889 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 1544563087 # Number of instructions committed +system.cpu.committedOps 1723073900 # Number of ops (including micro ops) committed +system.cpu.cpi 1.468479 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 485955700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 485955700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24973.063686 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24973.063686 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22917.493937 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22917.493937 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 478618690 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 478618690 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183227617996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183227617996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 7337010 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7337010 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 222 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168140794504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168140794504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015098 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015098 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336788 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45215.138055 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45215.138055 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40855.687627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40855.687627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 170348428 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170348428 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101174252000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101174252000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012965 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012965 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 2237619 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2237619 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 346681 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 346681 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77255572250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77255572250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890938 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 658541747 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 658541747 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29703.696091 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 648967118 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 648967118 # number of demand (read+write) hits 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 648967118 # number of overall hits +system.cpu.dcache.overall_hits::total 648967118 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 284401869996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 284401869996 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.014539 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014539 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 9574629 # number of overall misses +system.cpu.dcache.overall_misses::total 9574629 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 346903 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 346903 # number of overall MSHR hits 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blocks. +system.cpu.dcache.tags.data_accesses 1326311464 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.294010 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997386 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997386 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 9223630 # number of replacements +system.cpu.dcache.tags.sampled_refs 9227726 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 1326311464 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 4085.294010 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 648967240 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 10338720250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 3700800 # number of writebacks +system.cpu.dcache.writebacks::total 3700800 # number of writebacks +system.cpu.discardedOps 51251418 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 0 # DTB accesses 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+system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 468616075 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 468616075 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency 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(read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56848251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56848251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 468616075 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 468616075 # number of overall (read+write) accesses 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percentage was hit. +system.cpu.idleCycles 378561103 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.680977 # IPC: instructions per cycle +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 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+system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890938 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890938 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80530.523230 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80530.523230 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67904.363586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67904.363586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090908 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090908 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64426834500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 64426834500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423086 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423086 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 800030 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 800030 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54325528000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54325528000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423086 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423086 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800030 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800030 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337614 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7337614 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79650.729800 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79650.729800 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67079.515524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67079.515524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 6081653 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6081653 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100038210250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 100038210250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171167 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171167 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 1255961 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1255961 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84248920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84248920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171167 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171167 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255956 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255956 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 3700800 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700800 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 3700800 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700800 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 9228552 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9228552 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79993.076210 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 7172561 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7172561 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 164465044750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 164465044750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222786 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222786 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 2055991 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2055991 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138574448000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138574448000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222785 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055986 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055986 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 9228552 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9228552 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79993.076210 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 7172561 # number of overall hits +system.cpu.l2cache.overall_hits::total 7172561 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 164465044750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 164465044750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222786 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222786 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 2055991 # number of overall misses +system.cpu.l2cache.overall_misses::total 2055991 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138574448000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138574448000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222785 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055986 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055986 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12891 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15554 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 4.376215 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 107378812 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 14921.737919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 16303.939645 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455375 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.497557 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.952932 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 2023282 # number of replacements +system.cpu.l2cache.tags.sampled_refs 2053058 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 107378812 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 31225.677564 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984623 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 62285743250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 1046478 # number of writebacks +system.cpu.l2cache.writebacks::total 1046478 # number of writebacks +system.cpu.numCycles 2268158033 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 1889596930 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 827478528 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22157904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10165476000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1402249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14183973746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 729648037 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827425664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 827478528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7337614 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337614 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890938 # Transaction distribution +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 198557696 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158450 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5158450 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 12256366000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 19378736500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.7 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 175082770 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198557696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 198557696 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255956 # Transaction distribution +system.membus.trans_dist::ReadResp 1255956 # Transaction distribution +system.membus.trans_dist::Writeback 1046478 # Transaction distribution +system.membus.trans_dist::ReadExReq 800030 # Transaction distribution +system.membus.trans_dist::ReadExResp 800030 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 365541.37 # Average gap between requests +system.physmem.avgMemAccLat 37274.24 # Average memory access latency per DRAM burst +system.physmem.avgQLat 18524.24 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 115.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.03 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrBW 59.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.06 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing +system.physmem.busUtil 1.37 # Data bus utilization in percentage +system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 44808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 116026399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116026399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59056372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 116026399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 175082770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 59056372 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59056372 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1917061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.528140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.739842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.452866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1492586 77.86% 77.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305285 15.92% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52052 2.72% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21496 1.12% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13307 0.69% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7031 0.37% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5522 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4121 0.21% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15661 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1917061 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 131498944 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 131583104 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 84160 # Total number of bytes read from write queue +system.physmem.bytesWritten 66972672 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 66974592 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 131583104 # Number of bytes read from this memory +system.physmem.bytes_read::total 131583104 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 66974592 # Number of bytes written to this memory +system.physmem.bytes_written::total 66974592 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 321867794250 # Time in different power states +system.physmem.memoryStateTime::REF 37869260000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 774338779750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 2055986 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055986 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046478 # Number of write requests responded to by this memory +system.physmem.pageHitRate 38.18 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 127958 # Per bank write bursts +system.physmem.perBankRdBursts::1 125105 # Per bank write bursts +system.physmem.perBankRdBursts::2 122165 # Per bank write bursts +system.physmem.perBankRdBursts::3 124186 # Per bank write bursts +system.physmem.perBankRdBursts::4 123280 # Per bank write bursts +system.physmem.perBankRdBursts::5 123449 # Per bank write bursts +system.physmem.perBankRdBursts::6 123880 # Per bank write bursts +system.physmem.perBankRdBursts::7 124388 # Per bank write bursts +system.physmem.perBankRdBursts::8 131994 # Per bank write bursts +system.physmem.perBankRdBursts::9 133987 # Per bank write bursts +system.physmem.perBankRdBursts::10 132463 # Per bank write bursts +system.physmem.perBankRdBursts::11 133769 # Per bank write bursts +system.physmem.perBankRdBursts::12 133910 # Per bank write bursts +system.physmem.perBankRdBursts::13 133839 # Per bank write bursts +system.physmem.perBankRdBursts::14 129945 # Per bank write bursts +system.physmem.perBankRdBursts::15 130353 # Per bank write bursts +system.physmem.perBankWrBursts::0 65810 # Per bank write bursts +system.physmem.perBankWrBursts::1 64091 # Per bank write bursts +system.physmem.perBankWrBursts::2 62337 # Per bank write bursts +system.physmem.perBankWrBursts::3 62824 # Per bank write bursts +system.physmem.perBankWrBursts::4 62831 # Per bank write bursts +system.physmem.perBankWrBursts::5 62991 # Per bank write bursts +system.physmem.perBankWrBursts::6 64303 # Per bank write bursts +system.physmem.perBankWrBursts::7 65302 # Per bank write bursts +system.physmem.perBankWrBursts::8 67082 # Per bank write bursts +system.physmem.perBankWrBursts::9 67591 # Per bank write bursts +system.physmem.perBankWrBursts::10 67285 # Per bank write bursts +system.physmem.perBankWrBursts::11 67661 # Per bank write bursts +system.physmem.perBankWrBursts::12 67090 # Per bank write bursts +system.physmem.perBankWrBursts::13 67416 # Per bank write bursts +system.physmem.perBankWrBursts::14 66182 # Per bank write bursts +system.physmem.perBankWrBursts::15 65652 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 60782 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.755668 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.633297 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60741 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60782 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 1924013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 130641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 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0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2055986 # Read request sizes (log2) +system.physmem.readReqs 2055986 # Number of read requests accepted +system.physmem.readRowHitRate 37.77 # Row buffer hit rate for reads +system.physmem.readRowHits 776076 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 1315 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 10273355000 # Total ticks spent in databus transfers +system.physmem.totGap 1134078928500 # Total gap between requests +system.physmem.totMemAccLat 76586290250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 38061209000 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 60782 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.216413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.182090 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.086488 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 25426 41.83% 41.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1488 2.45% 44.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29643 48.77% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3806 6.26% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 363 0.60% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.08% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60782 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 33627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61437 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What 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write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 1046478 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1046478 # Write request sizes (log2) +system.physmem.writeReqs 1046478 # Number of write requests accepted +system.physmem.writeRowHitRate 38.99 # Row buffer hit rate for writes +system.physmem.writeRowHits 407972 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini new file mode 100644 index 000000000..4c4f72a25 --- /dev/null +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini @@ -0,0 +1,718 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 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+[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr new file mode 100644 index 000000000..506aa6e28 --- /dev/null +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout new file mode 100644 index 000000000..4d57fab87 --- /dev/null +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout @@ -0,0 +1,28 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:41:53 +gem5 started May 7 2014 15:05:33 +gem5 executing on cz3212c2d7 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 51810251500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt new file mode 100644 index 000000000..98d3f1024 --- /dev/null +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,633 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 51810521500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 191326 # Simulator instruction rate (inst/s) +host_mem_usage 251752 # Number of bytes of host memory used +host_op_rate 191326 # Simulator op (including micro ops) rate (op/s) +host_seconds 480.35 # Real time elapsed on the host +host_tick_rate 107860315 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 91903089 # Number of instructions simulated +sim_ops 91903089 # Number of ops (including micro ops) simulated +sim_seconds 0.051811 # Number of seconds simulated +sim_ticks 51810521500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 79.960972 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 5346983 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6686991 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 788623 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 8172556 # Number of conditional branches predicted +system.cpu.branchPred.lookups 11403069 # Number of BP lookups +system.cpu.branchPred.usedRAS 1173096 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 91903089 # Number of instructions committed +system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed +system.cpu.cpi 1.127503 # CPI: cycles per instruction +system.cpu.dcache.ReadReq_accesses::cpu.inst 20044127 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20044127 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 69928.365385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69928.365385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 68014.432990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68014.432990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 20043607 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20043607 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36362750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36362750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 520 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 32987000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32987000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67476.975945 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67476.975945 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68165.329513 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68165.329513 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 6498193 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196358000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196358000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 2910 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1165 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118948500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 118948500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1745 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 26545230 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26545230 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67848.615160 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67848.615160 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68132.511211 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68132.511211 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 26541800 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26541800 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 232720750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 232720750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151935500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151935500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 26545230 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26545230 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67848.615160 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67848.615160 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68132.511211 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68132.511211 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 26541800 # number of overall hits +system.cpu.dcache.overall_hits::total 26541800 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 232720750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 232720750 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses +system.cpu.dcache.overall_misses::total 3430 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 1200 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151935500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151935500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 11902.152466 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 53092690 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.584633 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.353658 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353658 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 53092690 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 1448.584633 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26541800 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.discardedOps 2238069 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dtb.data_accesses 27017530 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 26970236 # DTB hits +system.cpu.dtb.data_misses 47294 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 20437728 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 20390711 # DTB read hits +system.cpu.dtb.read_misses 47017 # DTB read misses +system.cpu.dtb.write_accesses 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of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 2226173 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.886915 # IPC: instructions per cycle +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 22978996 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 22978908 # ITB hits +system.cpu.itb.fetch_misses 88 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 16168 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68200.931332 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68200.931332 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55638.518210 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55638.518210 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 12571 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 12571 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245318750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245318750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.222476 # miss rate for ReadReq accesses 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accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 17913 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17913 # number of demand (read+write) accesses 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# number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5316 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295534250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 295534250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296768 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.296768 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 17913 # number of overall (read+write) accesses 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accesses +system.cpu.l2cache.overall_misses::cpu.inst 5316 # number of overall misses +system.cpu.l2cache.overall_misses::total 5316 # number of overall misses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295534250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 295534250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296768 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.296768 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5316 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5316 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id 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task id +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.sampled_refs 3663 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 149568 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 2479.792302 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12585 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.numCycles 103621043 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 101394870 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 1153280 # Total data (bytes) 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+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1003712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1153280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 16168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 340224 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10632 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 6066000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 49708250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 6566697 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 340224 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3597 # Transaction distribution +system.membus.trans_dist::ReadResp 3597 # Transaction distribution +system.membus.trans_dist::ReadExReq 1719 # Transaction distribution +system.membus.trans_dist::ReadExResp 1719 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 9746132.43 # Average gap between requests +system.physmem.avgMemAccLat 25349.60 # Average memory access latency per DRAM burst +system.physmem.avgQLat 6599.60 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 6.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.57 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 3909631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3909631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6566697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6566697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6566697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6566697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 980 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 346.710204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.810529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.902824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 318 32.45% 32.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 196 20.00% 52.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 101 10.31% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 95 9.69% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 76 7.76% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 3.78% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.24% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 2.14% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 114 11.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 980 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 340224 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 340224 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 202560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202560 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 340224 # Number of bytes read from this memory +system.physmem.bytes_read::total 340224 # Number of bytes read from this memory +system.physmem.memoryStateTime::IDLE 48729835000 # Time in different power states +system.physmem.memoryStateTime::REF 1730040000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1350106250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 5316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5316 # Number of read requests responded to by this memory +system.physmem.pageHitRate 81.55 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 469 # Per bank write bursts +system.physmem.perBankRdBursts::1 295 # Per bank write bursts +system.physmem.perBankRdBursts::2 307 # Per bank write bursts +system.physmem.perBankRdBursts::3 523 # Per bank write bursts +system.physmem.perBankRdBursts::4 224 # Per bank write bursts +system.physmem.perBankRdBursts::5 238 # Per bank write bursts +system.physmem.perBankRdBursts::6 222 # Per bank write bursts +system.physmem.perBankRdBursts::7 289 # Per bank write bursts +system.physmem.perBankRdBursts::8 251 # Per bank write bursts +system.physmem.perBankRdBursts::9 282 # Per bank write bursts +system.physmem.perBankRdBursts::10 255 # Per bank write bursts +system.physmem.perBankRdBursts::11 260 # Per bank write bursts +system.physmem.perBankRdBursts::12 409 # Per bank write bursts +system.physmem.perBankRdBursts::13 344 # Per bank write bursts +system.physmem.perBankRdBursts::14 500 # Per bank write bursts +system.physmem.perBankRdBursts::15 448 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.rdQLenPdf::0 4911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 5316 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5316 # Read request sizes (log2) +system.physmem.readReqs 5316 # Number of read requests accepted +system.physmem.readRowHitRate 81.55 # Row buffer hit rate for reads +system.physmem.readRowHits 4335 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 26580000 # Total ticks spent in databus transfers +system.physmem.totGap 51810440000 # Total gap between requests +system.physmem.totMemAccLat 134758500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 35083500 # Total ticks spent queuing +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..990a8e3a4 --- /dev/null +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..1a4f96712 --- /dev/null +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..6876fac87 --- /dev/null +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout @@ -0,0 +1,29 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 13:16:45 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2 +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x1c024750 +info: Entering event queue @ 0. Starting simulation... + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University +info: Increasing stack size by one page. + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 Exiting @ tick 133578736500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..6b1426f89 --- /dev/null +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,699 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 133576129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 174502 # Simulator instruction rate (inst/s) +host_mem_usage 298144 # Number of bytes of host memory used +host_op_rate 191062 # Simulator op (including micro ops) rate (op/s) +host_seconds 987.48 # Real time elapsed on the host +host_tick_rate 135269038 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 172317809 # Number of instructions simulated +sim_ops 188671292 # Number of ops (including micro ops) simulated +sim_seconds 0.133576 # Number of seconds simulated +sim_ticks 133576129500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 95.468318 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 23338838 # Number of BTB hits +system.cpu.branchPred.BTBLookups 24446684 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 1344 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 5759272 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 40186958 # Number of conditional branches predicted +system.cpu.branchPred.lookups 50197812 # Number of BP lookups +system.cpu.branchPred.usedRAS 1870133 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 172317809 # Number of instructions committed +system.cpu.committedOps 188671292 # Number of ops (including micro ops) committed +system.cpu.cpi 1.550346 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 30104490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30104490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68315.588308 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68315.588308 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66514.624478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66514.624478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 30103686 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30103686 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54925733 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 54925733 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 804 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 804 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47824015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47824015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 719 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 719 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70061.205847 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70061.205847 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70028.942571 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70028.942571 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 12362645 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362645 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115040500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115040500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 1642 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1642 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 545 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 545 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76821750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76821750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1097 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1097 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 42468777 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42468777 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69487.421504 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69487.421504 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68637.535793 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68637.535793 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 42466331 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42466331 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 169966233 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 169966233 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000058 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000058 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 2446 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2446 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124645765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 124645765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1816 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1816 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 42468777 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42468777 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69487.421504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69487.421504 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68637.535793 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68637.535793 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 42466331 # number of overall hits +system.cpu.dcache.overall_hits::total 42466331 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 169966233 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 169966233 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000058 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000058 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 2446 # number of overall misses +system.cpu.dcache.overall_misses::total 2446 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124645765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 124645765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1816 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1816 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 272 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1362 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 23409.220815 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 85028998 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 1381.804492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.337355 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.337355 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1774 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.433105 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 42 # number of replacements +system.cpu.dcache.tags.sampled_refs 1816 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 85028998 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 1381.804492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42511145 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.discardedOps 12279677 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 71932968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71932968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39567.186956 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39567.186956 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37371.415126 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37371.415126 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 71928261 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71928261 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186242749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186242749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 4707 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4707 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175907251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175907251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4707 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4707 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 71932968 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71932968 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39567.186956 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39567.186956 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37371.415126 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37371.415126 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 71928261 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71928261 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 186242749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186242749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 4707 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4707 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175907251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175907251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 4707 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4707 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 71932968 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71932968 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39567.186956 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39567.186956 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37371.415126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37371.415126 # average overall mshr miss latency +system.cpu.icache.overall_hits::cpu.inst 71928261 # number of overall hits +system.cpu.icache.overall_hits::total 71928261 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 186242749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186242749 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 4707 # number of overall misses +system.cpu.icache.overall_misses::total 4707 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175907251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175907251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 4707 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4707 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1065 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 15284.373353 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 143870642 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1433.013825 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.699714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.699714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1803 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.880371 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 2903 # number of replacements +system.cpu.icache.tags.sampled_refs 4706 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 143870642 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 1433.013825 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71928261 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 6392324 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.645017 # IPC: instructions per cycle +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1097 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1097 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69461.202938 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69461.202938 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56942.378329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56942.378329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75643250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75643250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992707 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992707 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 1089 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1089 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62010250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62010250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1089 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1089 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5426 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5426 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68229.765708 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68229.765708 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55711.085327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55711.085327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 2609 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2609 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 192203250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 192203250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519167 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.519167 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 2817 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2817 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156046750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 156046750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.516218 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.516218 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2801 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2801 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 6523 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6523 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68573.092678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68573.092678 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56055.784062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56055.784062 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 2617 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2617 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 267846500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 267846500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.598804 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598804 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 3906 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3906 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218057000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218057000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596351 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.596351 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3890 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3890 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 6523 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6523 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68573.092678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68573.092678 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56055.784062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56055.784062 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 2617 # number of overall hits +system.cpu.l2cache.overall_hits::total 2617 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 267846500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 267846500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.598804 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598804 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 3906 # number of overall misses +system.cpu.l2cache.overall_misses::total 3906 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218057000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218057000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596351 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.596351 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3890 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3890 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 538 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2015 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 0.929487 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 56217 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 3.030772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.746792 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061302 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061395 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2808 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.sampled_refs 2808 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 56217 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 2011.777563 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2610 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.numCycles 267152259 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 260759935 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 418432 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13061 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3285500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7520749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3003735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 3132536 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 117248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 418432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 5426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1097 # Transaction distribution +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 248896 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7778 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 4560000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 36404000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 1863327 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 248896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 248896 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 2800 # Transaction distribution +system.membus.trans_dist::ReadResp 2800 # Transaction distribution +system.membus.trans_dist::ReadExReq 1089 # Transaction distribution +system.membus.trans_dist::ReadExResp 1089 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 34347143.61 # Average gap between requests +system.physmem.avgMemAccLat 25898.62 # Average memory access latency per DRAM burst +system.physmem.avgQLat 7148.62 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 1.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.86 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.busUtil 0.01 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 1042102 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1042102 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1863327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1863327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1863327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1863327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 942 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 263.473461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.306387 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.627261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 286 30.36% 30.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 373 39.60% 69.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 8.60% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 48 5.10% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 26 2.76% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 28 2.97% 89.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 20 2.12% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.91% 93.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62 6.58% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 942 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 248896 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 248896 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 139200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 139200 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 248896 # Number of bytes read from this memory +system.physmem.bytes_read::total 248896 # Number of bytes read from this memory +system.physmem.memoryStateTime::IDLE 127581858000 # Time in different power states +system.physmem.memoryStateTime::REF 4460300000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1531687500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 3889 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3889 # Number of read requests responded to by this memory +system.physmem.pageHitRate 75.67 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 305 # Per bank write bursts +system.physmem.perBankRdBursts::1 217 # Per bank write bursts +system.physmem.perBankRdBursts::2 139 # Per bank write bursts +system.physmem.perBankRdBursts::3 312 # Per bank write bursts +system.physmem.perBankRdBursts::4 309 # Per bank write bursts +system.physmem.perBankRdBursts::5 306 # Per bank write bursts +system.physmem.perBankRdBursts::6 273 # Per bank write bursts +system.physmem.perBankRdBursts::7 225 # Per bank write bursts +system.physmem.perBankRdBursts::8 249 # Per bank write bursts +system.physmem.perBankRdBursts::9 218 # Per bank write bursts +system.physmem.perBankRdBursts::10 300 # Per bank write bursts +system.physmem.perBankRdBursts::11 202 # Per bank write bursts +system.physmem.perBankRdBursts::12 183 # Per bank write bursts +system.physmem.perBankRdBursts::13 219 # Per bank write bursts +system.physmem.perBankRdBursts::14 228 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.rdQLenPdf::0 3640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # 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Read request sizes (log2) +system.physmem.readReqs 3889 # Number of read requests accepted +system.physmem.readRowHitRate 75.67 # Row buffer hit rate for reads +system.physmem.readRowHits 2943 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 19445000 # Total ticks spent in databus transfers +system.physmem.totGap 133576041500 # Total gap between requests +system.physmem.totMemAccLat 100719750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 27801000 # Total ticks spent queuing +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- |